Final report NTI FPGA&RTOS&Cadeance ICFB&

Higher technology institute Electrical & computers Dept
Report on /
Advanced Electronics Training In NTI
Industrial training /
ITR 103
Submitted to : Examiners Committee
Submitted by : Name / Islam nabil mahmoud mohamed ID / 20130890
Supervised by : Prof.Dr / Tayel Dabos ( HTI )
Dr/ Mohamed Elzorkany (NTI)
August 2016
Islam Nabil Mahmoud 20130890 1 Electrical&computers Dept Industrial Training 3 ITR 103

Abstract
What is FPGA ?
FPGA vs Microcontroller
Hardware Description Languages
Flow OF FPGA Xilinx
What is PsoC & RTOS ?
Real Time Operating Systems
How RTOS work ?
IDE
RTOS Supported architectures
Labs of coding
Uart
Integrated circuit design
Cadence Flow
OrCAD Flow

Detailed Content
Contents
CH1 (FPGA).........................................................................................................................................3
History..................................................................................................................................................4
Modern developments..........................................................................................................................4
Gates.....................................................................................................................................................5
Applications..........................................................................................................................................5
FPGA vs Microcontroller.....................................................................................................................6
Hardware Description Languages........................................................................................................9
one-Bit Wide 2 to 1 Multiplexer.........................................................................................................11
one-Bit Wide 2 to 1 Multiplexer.........................................................................................................12
Four-Bit Wide 2 to 1 Multiplexer.......................................................................................................14
Multiplexers in VHDL.......................................................................................................................15
Flow OF FPGA Xilinx ISE 12.2.......................................................................................................15
Creating a Schematic..........................................................................................................................21
Simulating Circuit:.............................................................................................................................25
Synthesizing your circuit to the Xilinx FPGA...................................................................................28
Overview of the Procedure.................................................................................................................42
CH2 (PsoC & RTOS).........................................................................................................................43
Overview............................................................................................................................................43
Configurable analog and digital blocks..............................................................................................44
Programmable routing and interconnect............................................................................................45
Series..................................................................................................................................................45
Development tools..............................................................................................................................46
PSoC Designer.......................................................................................................................46
Summary............................................................................................................................................46
Real Time Systems types:..................................................................................................................47
Real Time Operating Systems (RTOS)..............................................................................................48
Design Philosophy..............................................................................................................................48
Real Time Task Priorities...................................................................................................................49
How RTOS work :..............................................................................................................................49
RTOS Supported architectures :.........................................................................................................50
Related projects..................................................................................................................................50
SafeRTOS................................................................................................................................50
OpenRTOS...............................................................................................................................51
Implementation...................................................................................................................................51
Key features........................................................................................................................................52
IDE.....................................................................................................................................................52
Coding with RTOS.............................................................................................................................52
Lab1....................................................................................................................................................52
lab 2 counting.....................................................................................................................................55
lab 3 uart.............................................................................................................................................57
CH3....................................................................................................................................................59
Integrated circuit design.....................................................................................................................59
Fundamentals......................................................................................................................................60
Design steps........................................................................................................................................61
Design Process...................................................................................................................................62
Microarchitecture and System-level Design..............................................................62
RTL design.........................................................................................................................................62

Physical design...................................................................................................................................63
Analog design.....................................................................................................................................63
Coping with variability.......................................................................................................................64
Vendors...............................................................................................................................................64
Cadence Flow.....................................................................................................................................64
2. Schematic.......................................................................................................................................67
simulation...........................................................................................................................................78
Layout.................................................................................................................................................86
CH4 PCB Design with ( OrCAD )...................................................................................................108
OrCAD PCB Designer.....................................................................................................................108
Introduction......................................................................................................................................108
OrCAD Flow....................................................................................................................................109
About Libraries and Parts.................................................................................................................110
2- Creating a Schematic Parts Library..............................................................................................111
3- Creating Schematic Symbols.......................................................................................................112
4- Schematic Entry...........................................................................................................................114
5- Preparing for Layout....................................................................................................................115
References:.......................................................................................................................................116

CH1 (FPGA)
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured
by a customer or a designer after manufacturing – hence "field-programmable". The FPGA
configuration is generally specified using a hardware description language (HDL), similar to that
used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to
specify the configuration, as they were for ASICs, but this is increasingly rare.)
A Spartan FPGA from Xilinx
FPGAs contain an array of programmable logic blocks, and a hierarchy of reconfigurable
interconnects that allow the blocks to be "wired together", like many logic gates that can
be inter-wired in different configurations. Logic blocks can be configured to perform
complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs,
logic blocks also include memory elements, which may be simple flip-flops or more
complete blocks of memory
History
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic
devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a
factory or in the field (field-programmable). However, programmable logic was hard-wired
between logic gates.
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve
Casselman to develop a computer that would implement 600,000 reprogrammable gates.
Casselman was successful and a patent related to the system was issued in 1992.
Some of the industry's foundational concepts and technologies for programmable logic arrays,
gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R.
Peterson in 1985.
Altera was founded in 1983 and delivered the industry’s first reprogrammable logic device
in 1984 – the EP300 – which featured a quartz window in the package that allowed users to
shine an ultra-violet lamp on the die to erase the EPROM cells that held the device
configuration.
Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first commercially
viable field-programmable gate array in 1985 – the XC2064.The XC2064 had programmable
gates and programmable interconnects between gates, the beginnings of a new
technology and market.The XC2064 had 64 configurable logic blocks (CLBs), with two

three-input lookup tables (LUTs). More than 20 years later, Freeman was entered into
the National Inventors Hall of Fame for his invention.
Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s,
when competitors sprouted up, eroding significant market share. By 1993, Actel
(now Microsemi) was serving about 18 percent of the market. By 2010, Altera (31 percent),
Actel (10 percent) and Xilinx (36 percent) together represented approximately 77 percent
of the FPGA market.
The 1990s were an explosive period of time for FPGAs, both in sophistication and the
volume of production. In the early 1990s, FPGAs were primarily used in
telecommunications and networking. By the end of the decade, FPGAs found their way into
consumer, automotive, and industrial applications.
Modern developments
A recent[when?] trend has been to take the coarse-grained architectural approach a step
further by combining the logic blocks and interconnects of traditional FPGAs with
embedded microprocessors and related peripherals to form a complete "system on a
programmable chip". This work mirrors the architecture by Ron Perlof and Hana Potash of
Burroughs Advanced Systems Group which combined a reconfigurable CPU architecture on
a single chip called the SB24. That work was done in 1982. Examples of such hybrid
technologies can be found in the Xilinx Zynq-7000 All Programmable SoC, which includes a
1.0 GHz dual-core ARM Cortex-A9 MPCore processor embedded within the FPGA's logic
fabric or in the Altera Arria V FPGA, which includes an 800 MHz dual-core ARM Cortex-A9
MPCore. The Atmel FPSLIC is another such device, which uses an AVR processor in
combination with Atmel's programmable logic architecture.
The Microsemi SmartFusion devices incorporate an ARM Cortex-M3 hard processor core (with
up to 512 kB of flash and 64 kB of RAM) and analog peripherals such as a multi-channel
ADC and DACs to their flash-based FPGA fabric.
In 2010, Xilinx Inc introduced the first All Programmable System on a Chip branded
Zynq™-7000 that fused features of an ARM high-end microcontroller (hard-core
implementations of a 32-bit processor, memory, and I/O) with an 28 nm FPGA fabric to
make it easier for embedded designers to use. The extensible processing platform enables
system architects and embedded software developers to apply a combination of serial and
parallel processing to their embedded system designs, for which the general trend has
been to progressively increasing complexity. The high level of integration helps to reduce
power consumption and dissipation, and the reduced parts count versus using an FPGA
with a separate CPU chip leads to a lower parts cost, a smaller system, and higher
reliability since most failures in modern electronics occur on PCBs in the connections
between chips instead of within the chips themselves.
An alternate approach to using hard-macro processors is to make use of soft
processor cores that are implemented within the FPGA logic. Nios II, MicroBlaze and Mico32are
examples of popular softcore processors.
As previously mentioned, many modern FPGAs have the ability to be reprogrammed at
"run time", and this is leading to the idea of reconfigurable computing or reconfigurable
systems – CPUs that reconfigure themselves to suit the task at hand.
Additionally, new, non-FPGA architectures are beginning to emerge. Software-configurable
microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array
of processor cores and FPGA-like programmable cores on the same chip.

Companies like Microsoft have started to use FPGA to accelerate high-performance,
computationally intensive systems (like the data centers that operate their Bing search
engine), due to the performance per Watt advantage FPGAs deliver
Gates
1982: 8192 gates, Burroughs Advances Systems Group, integrated into the S-Type 24-bit
processor for reprogrammable I/O.
1987: 9,000 gates, Xilinx[
1992: 600,000, Naval Surface Warfare Department
Early 2000s: Millions
Applications
An FPGA can be used to solve any problem which is computable. This is trivially proven by the
fact FPGA can be used to implement a soft microprocessor, such as the Xilinx MicroBlaze or
Altera Nios II. Their advantage lies in that they are sometimes significantly faster for some
applications because of their parallel nature and optimality in terms of the number of gates
used for a certain process.
Specific applications of FPGAs include digital signal processing, software-defined
radio, ASIC prototyping, medical imaging, computer vision, speech
recognition,cryptography, bioinformatics, computer hardware emulation, radio astronomy, metal detection
and a growing range of other areas.
FPGAs originally began as competitors to CPLDs and competed in a similar space, that
of glue logic for PCBs. As their size, capabilities, and speed increased, they began to take
over larger and larger functions to the point where some are now marketed as full systems
on chips (SoC). Particularly with the introduction of dedicated multipliers into FPGA
architectures in the late 1990s, applications which had traditionally been the sole reserve
of DSPs began to incorporate FPGAs instead.
Another trend on the usage of FPGAs is hardware acceleration, where one can use the
FPGA to accelerate certain parts of an algorithm and share part of the computation
between the FPGA and a generic processor.
Traditionally, FPGAs have been reserved for specific vertical applications where the volume of
production is small. For these low-volume applications, the premium that companies pay in
hardware costs per unit for a programmable chip is more affordable than the development
resources spent on creating an ASIC for a low-volume application. Today, new cost and
performance dynamics have broadened the range of viable applications.

FPGA VS microcontroller
As for the difference between a microcontroller and a FPGA, you can consider a
microcontroller to be an ASIC which basically processes code in FLASH/ROM
sequentially. You can make microcontrollers with FPGAs even if it's not optimised,
but not the opposite. FPGAs are wired just like electronic circuits so you can have
truly parallel circuits, not like in a microcontroller where the processor jumps from
a piece of code to another to simulate good-enough parallelism. However because
FPGAs have been designed for parallel tasks, it's not as easy to write sequential
code as in a microcontroller.
For example, typically if you write in pseudocode "let C be A XOR B", on a FPGA
that will be translated into "build a XOR gate with the lego bricks contained
(lookup tables and latches), and connect A/B as inputs and C as output" which will
be updated every clock cycle regardless of whether C is used or not. Whereas on a
microcontroller that will be translated into "read instruction - it's a XOR of
variables at address A and address B of RAM, result to store at address C. Load
arithmetic logic units registers, then ask the ALU to do a XOR, then copy the
output register at address C of RAM". On the user side though, both instructions
were 1 line of code. If we were to do this, THEN something else, in HDL we would
have to define what is called a Process to artificially do sequences - separate from
the parallel code. Whereas in a microcontroller there is nothing to do. On the other
hand, to get "parallelism" (tuning in and out really) out of a microcontroller, you
would need to juggle with threads which is not trivial. Different ways of working,
different purposes.
FPGA vs Microcontroller
When I first learned about FPGAs, all I really knew about before was microcontrollers. So first it is
important to understand that they are very different devices. With a microcontroller, like an Arduino, the
chip is already designed for you. You simply write some software, usually in C or C++, and compile it to
a hex file that you load onto the microcontroller. The microcontroller stores the program in flash memory
and will store it until it is erased or replaced. With microcontrollers you have control over the software.
FPGAs are different. You are the one designing the circuit. There is no processor to run software on, at
least until you design one! You can configure an FPGA to be something as simple as an and gate, or
something as complex as a multi-core processor. To create your design, you write some HDL
(Hardware Description Language). The two most popular HDLs are Verilog and VHDL. You
then synthesize your HDL into a bit file which you can use to configure the FPGA. A slight downside to

FPGAs is that they store their configuration in RAM, not flash, meaning that once they lose power they
lose their configuration. They must be configured every time power is applied.
That is not as bad as it seems as there are flash chips you can use that will automatically configure the
stored bit file on power up. There are also some development boards which don't require a programmer
at all and will configure the FPGA at startup.
With FPGAs you have control over the hardware.
How it Began : PLA
• Programmable Logic Array
• First programmable device
• 2-level and-or structure
• One time programmable
SPLD – CPLD
Simple Programmable logic device
Single AND Level
• Flip-Flops and feedbacks
Complex Programmable logic device
Several PLDs Stacked together
FPGA - Field Programmable Gate Array
Programmable logic blocks (Logic Element “LE”)
Implement combinatorial and sequential logic. Based on LUT and DFF.
Programmable I/O blocks
Configurable I/Os for external connections supports various voltages and tri-states.
Programmable interconnect
Wires to connect inputs , outputs and logic blocks.clocks
short distance local connections
long distance connections across chip

Xilinx Programmable Gate Arrays
CLB - Configurable Logic Block
5-input, 1 output function or 2 4-input, 1 output functions
◦ optional register on outputs Built-in fast carry logic
Can be used as memory Three types of routing direct
◦ general-purpose
◦ long lines of various lengths
RAM-programmable
can be reconfigured
Configuring LUT
LUT is a RAM with data width of 1bit.
The contents are programmed at power up
Xilinx Spartan-3E Starter Kit

Hardware Description Languages
• Hardware description languages (HDL)
Language to describe hardware
• Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware Description Language
Developed by DoD (United States Department of Defense )from 1983
IEEE Standard 1076-1987/1993/200x
Based on the ADA language
• Verilog
IEEE Standard 1364-1995/2001/2005
Based on the C language
Applications of HDL
• Model and document digital systems
• Different levels of abstraction
• Behavioral, structural, etc.
• Verify design
• Synthesize circuits
• Convert from higher abstraction levels to lower abstraction levels

VHDL Introduction
• VHDL is NOT Case-Sensitive
Begin = begin = beGiN
• Semicolon “ ; ” terminates declarations or statements.
• After a double minus sign (--) the rest of the line is treated as a comment
Built-in Datatypes
Scalar (single valued) signal types:
• bit
• boolean
• integer
Examples:
• A: in bit;
• G: out boolean;
• K: out integer range -2**4 to 2**4-1;
Aggregate (collection) signal types:
• bit_vector: array of bits representing binary numbers
Examples:
• D: in bit_vector(0 to 7);
• E: in bit_vector(7 downto 0);
VHDL Architecture
VHDL description (sequential behavior):
architecture arch_name of Mux21 is
begin
p1: process (A,B,S)
begin
if (S=‘0’) then
X <= A;
else
X <= B;
end if;
end process p1;
end;

VHDL Architecture
VHDL description (concurrent behavior):
architecture behav_conc of Mux21 is
begin
X <= A when (S=‘0’) else
B;
end ;
Complete Example
one-Bit Wide 2 to 1 Multiplexer

one-Bit Wide 2 to 1 Multiplexer

Four-Bit Wide 2 to 1 Multiplexer

Multiplexers in VHDL

Flow OF FPGA Xilinx ISE 12.2
Setting up a New Project and specifying a circuit in Verilog
1. Start the ISE 12.2 tool from Xilinx.

2. Create a new project. The Create New Project wizard will prompt you for a
location for your project. Note that by default this will be in the ISE folder
the very first time you start up. You’ll probably want to change this to
something in your own folder tree.

3. On the second page of the Create New Project dialog, make sure that
you use the Spartan3e Device Family, XC3S500 Device, FG320
Package, -5 Speed Grade. You can also specify HDL as the Top-Level
Source Type with XST as the Synthesis Tool, ISE as the Simulator, and Verilog as the language.
These aren’t critical, but they do save time later.
4- You can skip the other parts of the dialog, or you can use them to create
new Verilog file templates for your project. I usually just skip them and
create my own files later.

5-Now you want to open a new source file. Use the Project►NewSource
menu choice. This first one will be a Verilog file so make sure you’ve
selected Verilog Module as the type and give it a name. I’m calling my
example mynand.
6-When you press Next you’ll get a dialog box that lets you define the inputs
and outputs of your new module. I’m adding two inputs (A and B), and one
output named Y. Remember that Verilog is case sensitive!

7-When you Finish, you’ll have a template for a Verilog module that you can
fill in with your Verilog code. It looks like this (note that you can also fill in
the spots in the comment header with more information):
8- Now you can fill in the rest of the Verilog module to implement some
Boolean function. I’ll implement a NAND for this example. You can use any of the Verilog
techniques that you know about. (see the Brown &Vranesic text from 3700, for example, or any
number of Verilog tutorialson the web.) Note that ISE 10.1 uses Verilog 2001 syntax where
theinputs and outputs are defined right in the argument definition line. I’ll usea continuous
assignment statement: assign Y = ~(A & B); as shown
below, then I’ll save the file.

9- In order to use this Verilog code in a schematic, you’ll need to create a
schematic symbol. Select the mynand.v file in the Sources window, then
in the Processes window select Create Schematic Symbol under the
Design Utilities.
Creating a Schematic
1- Start by going to Project►NewSource and this time choosing schematicas the type. I’m calling
this fulladd. You can probably guess where this is going...

2- In the schematic window you’ll see a frame in which you can put your
schematic components. You can select components by selecting theSymbols tab in the Sources
pane. The first one I like to add is under General Category and is the Title component for the
schematic. You can fill in the fields of the Title by double clicking on it. Then I’ll add three copies
of mynand from my example library, and two copies of the xor2component from the Logic
Category.

Now I’ll use the wiring tool to connect up the components to make a FullAdder.
Save the schematic. You are now ready to simulate the circuit that
consists of part schematics (using xor2 from the Xilinx library), and part
Verilog (your mynand.v code). If you go back to the Sources pane and
expand the fulladd schematic you will see that it includes three copies of mynand.v.

Simulating Circuit:
To simulate the fulladd circuit:
1. Go to the top left pane (design) and change the View field to be
Simulation. This changes the view to include sources that are interesting
for simulation, and also changes the options in the bottom Processes
pane to show the simulation options.
2. You can go to the Project►NewSource menu again, or you can select
the Create New Source widget.
This will bring up the New Source
Wizard. In that dialog type in the name of your testbench file, and make
sure to select Verilog Test Fixture in the list on the left. I will name my
testbench fulladd_tb (where the tb stands for testbench). The box looks like:
The Next dialog asks you which source you want the testbench

constructed from. I’ll choose fulladd, of course. The code that gets generated includes an instance of
the fulladd schematic named UUT (for Unit Under Test).

Note that the generated template has some code with an ‘ifdef for
initializing things. I don’t use the ‘ifdef code. Instead I write my own initial
block and driving code for testing the circuit. Remember that good
testbenches ALWAYS use $display statements and “if” checks so
that the testbench is self-checking! You could enumerate all eight
possibilities of the inputs and check the outputs. I’m going to get a tiny bit
tricky with a concatenation and a loop.

Synthesizing circuit to the Xilinx FPGA
Now that you have a correctly simulating Verilog module, you will have the ISE
Once you fill in the testbench with Verilog code to drive the
simulation, you
can check the syntax and run the simulation from the
Processes tab.
The output will be displayed as waveforms, and the $display
data will
show up in the console as shown (after zooming out to see all
the
waveforms). You can see that not only do the waveforms show
the results
of the simulation, but the $display statements have printed
data, and
because the circuit is correctly functioning, no error statements
were
printed.
Synthesizing your circuit to the Xilinx FPGA
(webPACK) tool synthesize your Verilog to something that can be mapped to the
Xilinx FPGA. That is, the Verilog code will be converted by ISE to some gates
that are on the FPGA. To be even more specific, ISE will convert the
schematic/Verilog project description into a set of configuration bits that are used
to program the Xilinx part. Those configuration bits are in a .bit file and are
downloaded to the Xilinx part in this section of the tutorial.
You will use your Spartan-3E board for this part of the tutorial. This is known as
the “Spartan 3E Starter Kit” and is a board produced by Xilinx. It is a very feature-
laden board with a Spartan 3e XC3S500E FPGA, 64Mbytes of SDRAM,
128Mbits of flash EPROM, A/D and D/A converters, RS232 drivers, VGA, PS/2,
USB, and Ethernet connectors, a 16 character two-line LCD, and a lot more

Specifically we will need to:
Assign A, B, and Y to the correct pins on the FPGA that connect to the
switches and LEDs on the S3E board
Synthesize the Verilog code into FPGA configuration
Generate a programming file with all this information (.bit file)
Use the impact tools from Xilinx (part of WebPACK) to configure the FPGA
through the USB connection.
1. Back in the Design pane, return to the
Implementation view and select
your fulladd schematic. Now in the bottom
(Processes) pane you will see
some options including User Constraints,
Synthesize, and Implement
Design. The first thing we’ll do is assign pins using
the User Constraints
tab. Expand that tab and select the I/O Pin Planning
(PlanAhead) – Pre-
Synthesis choice. This will let us assign our signals
to pins on the Xilinx
part using the PlanAhead tool.
Because we’re headed towards putting this on the Xilinx FPGA on the Spartan-3E board, we need
to set some constraints. In particular, we need to tell ISE which pins on the Xilinx chip we want A,
B, Cin assigned to so that we can access those from switches, and where we want Cout and
Sum so we can see those on the LEDs on the Spartan-3E board.
This will open a whole new tool called PlanAhead which you can use to set your pin constraints.
You may have to agree to add a UCF (UniversalConstraints File) file to your project. You should
agree to this.The PlanAhead tools lets you set a number of different types of constraints on how the
circuit is mapped to the Xilinx part. For now we’ll just use the pin constraints in the UCF file

You can see a list of the I/O ports from your
schematic in the RTL pane
(click on the I/I Ports tab in the upper left window).
You can set which
Xilinx pin they are attached to using the Site field.
3. Clicking on each I/O Port in turn will open the
I/O Port Properties pane
where you an update the Site field to say which
Xilinx pin should be used for that I/O signal.

and the UCF info is:
This tells you how to fill out the information in PlanAhead for the switches.
I’ll put A, B and Cin on Sw3, Sw2, and Sw1.
Synthesize – XST. Double click on this to synthesize your circuit. After a
while you will (hopefully) get the “Process ‘Synthesize’ completed
successfully” message in the console. If you’ve already simulated your
circuit and found it to do what you want, there’s every chance that this will
synthesize correctly without problems.
In any case, there is lots of interesting information in the synthesis report
(the data in the console window). It’s worth looking at, although for this
amazingly simple example there isn’t anything that fascinating.
Make sure that you end the process with a green check for this process. If
you get something else, especially a red X, you’ll need to fix errors and re-
synthesize.

With your source file selected (fulladder in this case), double
click the
Implement Design process in the Processes tab. This will
translate the
design to something that can physically be mapped to the
particular FPGA
that’s on our board (the xc3s500e-5fg320 in this case). You
should see a
green check mark if this step finishes without issues. If there
are issues,
you need to read them for clues about what went wrong and what you
should look at to fix things.
If you expand this Implement Design tab (which is not necessary)
you will
see that the Implement Design process actually consists of three
parts:
a. Translate: Translate is the first step in the implementation
process.
The Translate process merges all of the input netlists and design
constraint information and outputs a Xilinx NGD (Native Generic
Database) file. The output NGD file can then be mapped to the
targeted FPGA device.
b. Map: Mapping is the process of assigning a design’s logic elements
to the specific physical elements that actually implement logic
functions in a device. The Map process creates an NCD (Native
Circuit Description) file. The NCD file will be used by the PAR
process.

c. Place and Route (PAR): PAR uses the NCD file created by the
Map process to place and route your design. PAR outputs an NCD
file that is used by the bitstream generator (BitGen) to create a (.bit)
file. The Bit file (see the next step) is what’s used to actually
program the FPGA.
At this point you can look at the Design Summary to find out all sorts of
things about your circuit. One thing that you might want to check is to click
on the Pinout Report and check that your signals were correctly assigned
to the pins you wanted them to be assigned to
Now double click the process: Generate Programming File. This will
generate the actual configuration bits into a .bit file that you can use to
program your Spartan-3E board to behave like your circuit (in this case a
full adder).
Now that you have the programming file, you can program the Spartan-3E
board using the iMPACT tool and the USB cable on your PC/laptop. First,
make sure that the jumpers on your Spartan-3E board are installed
correctly. In particular, check that the configuration options are correctly
set. The configuration options are at the top of the board near the RS232
interfaces.
The

jumpers on the J30 headers must be set for JTAG programming. This
means that only the middle pins of the header should have a jumper on
them. See the following illustration from the User Guide. Your board
should look like this!

Now that you have the jumpers set correctly, you can plug in the power to
your Spartan-3E board, and connect the USB cable between the Spartan-
3E and your PC. Then when you turn on the power, the PC should
recognize the Xilinx cable/board and install the drivers.
Once the PC has recognized the USB connection to the Spartan-3E
board, you can use the Process Configure Target Device to start up the
iMPACT tool to program the FPGA.
The first time you Configure Target Device for a new project, you’ll get
the following message about setting up an iMPACT file. You can click OK
here and start up the iMPACT tool.
You’ll now get yet another tool – the iMPACT device configuration and
programming tool:

Double-click the Boundary Scan button to configure the Xilinx part for
programming. Boundary Scan is the technique that is used on these
devices for uploading the bit file to the Xilinx part through the USB cable.
You will be prompted to Right Click to Add Device or Initialize JTAG
Chain. JTAG is the acronym for the boundary scan standard that is used
for programming in this case. When you right-click you get a menu. What
Select Initialize Chain. There are actually three programmable parts on
the Spartan3 board and they are organized in a chain passing the bits
from one device to the other. This is the chain that is being initialized.
Note that you MUST have your board plugged in to the USB cable and
turned on for this step! The initialization procedure sends a query out on
the USB cable to see what chips are out there. If you have everything
plugged in and turned on it will see the chips and initialize the chain.
You should continue and assign a configuration file:

You will now be asked to choose a configuration file (which will be a .bit
file) or each of the programmable chips on the Spartan-3E board. Note
that there are three of them, but the xc3s500e is the only one you should
program. The other two are already programmed with supporting tasks on
the board. Choose the file that you want programmed into the FPGA. In
this case that’s fulladd.bit.
You will also be asked if you want to attach an SPI or BPI PROM to the
device. For now you should say No. There is a 16Mbit SPI PROM
attached to the Xilinx part and later on you may want to include a PROM
data file here so that the bitstream will also load that prom.

For each of the other chips you can choose to open a file (attach a .bit file
to that chip), or to bypass. You should choose bypass for the other chips
(the xcf04s and the xc2c64).
The summary looks like this:
In the iMPACT screen you should now see the
following window that
shows the programmable chips and the
associated bit files or bypass
configurations.
Now you can select the Spartan-3E (the xc3s500e) and right click to get a
dialog. Select Program in this dialog to program the FPGA.

You should see the following indication that the programming has
succeeded. You should also see the xc-done LED (a little yellow LED
underneath the J30 jumper on the board) light up if the programming is
successful.
Your circuit should now be running on the Spartan-3E board. If you’ve
followed this tutorial you should now be able to set the sw3, sw2, and sw1
switches and look for the full adder output on LDE1 and LED0.
If you make changes and want to reload the bit file to the FPGA (after
making changes, for example), you can restart the iMPACT tool using the
Manage Configuration Project (iMPACT) option under Configure
Target Device.

Overview of the Procedure
1. Design the circuit that you would like to map to the Xilinx part on the
FPGA. You can use schematics, or Verilog, or a mixture of both.
2. Simulate your circuit using the ISE Simulator and a Verilog testbench to
provide inputs to the circuit. Use “if” statements in your testbench to make
it self-checking.
3. Generate a UCF file to hold constraints such as pin assignments (later
we’ll use the UCF file for other constraints like timing and speed). Use the
PlanAhead tool to generate this file.
4. Assign the I/O pins in your design to the pins on the FPGA that you want
them connected to.
5. Synthesize the design for the FPGA using the XST synthesis tool.
6. Implement the design to map it to the specific FPGA on the Spartan-3E
board
7. Generate the programming .bit file that has the bitstream that configures
the FPGA.
8. Connect your Spartan3 board to the computer and use theiMPACT tool to
program the FPGA using the bitstream.

CH2 (PsoC & RTOS)
PSoC (Programmable System-on-Chip) is a family of microcontroller integrated
circuits by Cypress Semiconductor. These chips include a CPU core and mixed-
signal arrays of configurable integrated analog and digital peripherals.
In 2002, Cypress began shipping commercial quantities of the PSoC 1.[1] To promote the
PSoC, Cypress sponsored a "PSoC Design Challenge" in Circuit Cellar magazine in 2002
and 2004.[2]
In April 2013, Cypress released the fourth generation, PSoC 4. The PSoC 4 features a 32-
bit ARM Cortex-M0 CPU, with programmable analog blocks (operational amplifiers and
comparators), programmable digital blocks (PLD-based UDBs), programmable routing and
flexible GPIO (route any function to any pin), a serial communication block (for SPI,
UART, I²C), a timer/counter/PWM block and more.[3]
PSoC is used in devices as simple as Sonicare toothbrushes and Adidas sneakers, and as
complex as the TiVo set-top box. One PSoC, using CapSense, controls the touch-sensitive scroll
wheel on the Apple iPod click wheel.
In 2014, Cypress extended the PSoC 4 family by integrating a Bluetooth Low Energy radio
along with a PSoC 4 Cortex-M0-based SoC in a single, monolithic die.
In 2016, Cypress released PSoC 4 S-Series, featuring ARM Cortex-M0+ CPU.[4]
Overview
A PSoC integrated circuit is composed of a core, configurable analog and digital blocks,
and programmable routing and interconnect. The configurable blocks in a PSoC are the
biggest difference from other microcontrollers.
PSoC has three separate memory spaces: paged SRAM for data, Flash memory for
instructions and fixed data, and I/O Registers for controlling and accessing the configurable
logic blocks and functions. The device is created using SONOS technology.
PSoC resembles an ASIC: blocks can be assigned a wide range of functions and
interconnected on-chip. Unlike an ASIC, there is no special manufacturing process required
to create the custom configuration — only startup code that is created by Cypress' PSoC
Designer (for PSoC 1) or PSoC Creator (for PSoC 3 / 4 / 5) IDE.
PSoC resembles an FPGA in that at power up it must be configured, but this configuration
occurs by loading instructions from the built-in Flash memory.
PSoC most closely resembles a microcontroller combined with a PLD and programmable
analog. Code is executed to interact with the user-specified peripheral functions (called
"Components"), using automatically generated APIs and interrupt routines. PSoC
Designer or PSoC Creator generate the startup configuration code. Both integrate APIs that
initialize the user selected components upon the users needs in a Visual-Studio-like GUI.

Configurable analog and digital blocks
Using configurable analog and digital blocks, designers can create and change mixed-
signal embedded applications. The digital blocks are state machines that are configured
using the blocks registers. There are two types of digital blocks, Digital Building Blocks
(DBBxx) and Digital Communication Blocks (DCBxx). Only the communication blocks can
contain serial I/O user modules, such as SPI, UART, etc.
Each digital block is considered an 8-bit resource that designers can configure using pre-
built digital functions or user modules (UM), or, by combining blocks, turn them into 16-,
24-, or 32-bit resources. Concatenating UMs together is how 16-bit PWMs and timers are
created.
There are two types of analog blocks. The continuous time (CT) blocks are composed of an
op-amp circuit and designated as ACBxx where xx is 00-03. The other type is the switch
cap (SC) blocks, which allow complex analog signal flows and are designated by ASCxy
where x is the row and y is the column of the analog block. Designers can modify and
personalize each module to any design.

Programmable routing and interconnect
PSoC mixed-signal arrays' flexible routing allows designers to route signals to and from I/O
pins more freely than with many competing microcontrollers. Global buses allow for signal
multiplexing and for performing logic operations. Cypress suggests that this allows
designers to configure a design and make improvements more easily and faster and with
fewer PCB redesigns than a digital logic gate approach or competing microcontrollers with
more fixed function pins.
Series
There are four different families of devices, each based around a different microcontroller
core:
PSoC 1 - CY8C2xxxx series — M8C core.
PSoC 3 - CY8C3xxxx series - 8051 core.
PSoC 4 - CY8C4xxxx series - ARM Cortex-M0 core.[5]
PSoC 5/5LP - CY8C5xxxx series - ARM Cortex-M3 core.
Bluetooth Low Energy
Starting in 2014, Cypress began offering PSoC 4 BLE devices with integrated Bluetooth
Low Energy (Bluetooth Smart). This can be used to create connected products leveraging
the analog and digital blocks.[6] Users can add and configure the BLE module directly in
PSoC creator. Cypress also provides a complete Bluetooth Low Energy stack licensed
from Mindtree with both Peripheral and Central functionality.[7]
Development tools
PSoC Designer
This is the first generation software IDE to design and debug and program the PSoC 1
devices. It introduced unique features including a library of pre-characterized analog and
digital peripherals in a drag-and-drop design environment which could then be customized
to specific design needs by leveraging the dynamically generated API libraries of code.
PSoC Creator
PSoC Creator is the second generation software IDE to design debug and program the
PSoC 3 / 4 / 5 devices. The development IDE is combined with an easy to use graphical
design editor to form a powerful hardware/software co-design environment. PSoC Creator
consists of two basic building blocks. The program that allows the user to select, configure
and connect existing circuits on the chip and the components which are the equivalent of
peripherals on MCUs. What makes PSoC intriguing is the possibility to create own
application specific peripherals in hardware. Cypress publishes component packs several
times a year. PSoC users get new peripherals for their existing hardware without being
charged or having to buy new hardware. PSoC Creator also allows much freedom in
assignment of peripherals to I/O pins.

Summary
PSoC 1 PSoC 3 PSoC 4 PSoC 5/5LP
8-bit M8C core
up to 24 MHz,
4 MIPS
8-bit 8051 core (single-
cycle)
up to 67 MHz, 33 MIPS
32-bit ARM Cortex-
M0
up to
48 MHz, ? MIPS
32-bit ARM Cortex-
M3
up to 80 MHz,
84 MIPS
Flash: 4 KB to 32 KB
SRAM: 256 bytes to
2 KB
Flash: 8 KB to 64 KB
SRAM: 3 KB to 8 KB
Flash: 16 KB to
32 KB
SRAM: 2 KB to 4 KB
Flash: 32 KB to
256 KB
SRAM: 8 KB to
64 KB
I²C, SPI, UART,
FS USB 2.0
I²C, SPI, UART, LIN,
FS USB 2.0, I²S, CAN
I²C, SPI, UART
.
I²C, SPI, UART, LIN,
FS USB 2.0, I²S
16 digital PSoC
blocks
16 to 24 UDBs (Universal
Digital Blocks)
4 UDBs 20 to 24 UDBs
1 Delta-Sigma ADC
(6 to 14-bit)
131 ksps @ 8-bit;
Up to two DACs (6 to
8-bit)
1 Delta-Sigma ADC (8 to
20-bit)
192 ksps @ 12-bit;
Up to four DACs (8-bit)
1 SAR ADC (12-bit)
1 Msps @ 12-bit;
Up to two DACs (7 to
8-bit)
1 Delta-Sigma ADC
(8 to 20-bit)
192 ksps @12-bit;
2 SAR ADCs (12-bit)
1 Msps @ 12-bit;
Up to four DACs (8-
bit)
Up to 64 I/O Up to 72 I/O Up to 36 I/O Up to 72 I/O
Operation: 1.7 V to
5.25 V
Active: 2 mA,
Sleep: 3 μA
Hibernate: ?
Operation: 0.5 V to 5.5 V
Active: 1.2 mA,
Sleep: 1 μA,
Hibernate: 200 nA
Operation: 1.71 V to
5.5 V
Active: 1.6 mA,
Sleep: 1.3 μA,
Hibernate: 150 nA
Operation: 2.7 V to
5.5 V
Active: 2 mA,
Sleep: 2 μA,
Hibernate: 300 nA
Requires ICE Cube
and FlexPods
On-chip SWD, Debug
On-chip JTAG, SWD,
SWV,
Debug, Trace
CY8CKIT-001
Development Kit
CY8CKIT-001
Development Kit
CY8CKIT-030
Development Kit
CY8CKIT-040
Pioneer Kit
CY8CKIT-042
Pioneer Kit
CY8CKIT-049
Prototype Kit
CY8CKIT-001
Development Kit
CY8CKIT-050
Development Kit
CY8CKIT-059
Prototype Kit

Real Time Systems types:
Soft Real Time Systems
Hard Real Time Systems
Firm Real Time Systems
Hard real-time means you must absolutely hit every deadline. Very few systems have this
requirement. Some examples are nuclear systems, some medical applications such as
pacemakers, a large number of defense applications, avionics, etc.
Firm/soft real time systems can miss some deadlines, but eventually performance will degrade
if too many are missed. A good example is the sound system in your computer. If you miss a
few bits, no big deal, but miss too many and you're going to eventually degrade the system.
Similar would be seismic sensors. If you miss a few datapoints, no big deal, but you have to
catch most of them to make sense of the data. More importantly, nobody is going to die if they
don't work correctly.
Real Time Operating Systems (RTOS)
A real-time operating system (RTOS) is an operating system (OS) intended to
serve real-time application process data as it comes in, typically without
buffering delays. Processing time requirements (including any OS delay) are
measured in tenths of seconds or shorter.
A key characteristic of a RTOS is the level of its consistency concerning the
amount of time it takes to accept and complete an application's task; the
variability is jitter.Ahard real-time operating system has less jitter than
a soft real-time operating system. The chief design goal is not high throughput,
but rather a guarantee of a soft or hardperformance category. A RTOS that can
usually or generally meet a deadline is a soft real-time OS, but if it can meet a
deadline deterministically it is a hard real-time OS.
A common example of an RTOS application is an HDTV receiver and display. It
needs to read a digital signal, decode it and display it as the data comes in.
Any delay would be noticeable as jerky or pixelated video and/or garbled audio.
ARINC Specification 653 defines the RTOS interface standard used in aviation
embedded system designs. The RTOS is developed and supplied by multiple
suppliers in an open market.
A RTOS has an advanced algorithm for scheduling. Scheduler flexibility enables a
wider, computer-system orchestration of process priorities, but a real-time OS
is more frequently dedicated to a narrow set of applications. Key factors in a
real-time OS are minimal interrupt latency and minimal thread switching latency; a real-
time OS is valued more for how quickly or how predictably it can respond than
for the amount of work it can perform in a given period of time

According to a 2014 Embedded Market Study,the following RTOSes are among the top 10
operating systems used in the embedded systems market:
Green Hills Software INTEGRITY
Wind River VxWorks
QNX Neutrino
FreeRTOS
Micrium µC/OS-II, III
Windows CE
TI-RTOS Kernel (previously called DSP/BIOS)
RTEMS open source RTOS designed for embedded systems, mainly used for missile and
space probes control
Design Philosophy
FreeRTOS is designed to be:
Simple
Portable
Concise
Real Time Task Priorities
Low priority numbers denote low priority tasks, with the default idle priority defined by
tskIDLE_PRIORITY as
being zero.
The number of available priorities is defined by tskMAX_PRIORITIES within FreeRTOSConfig.h .
This should
be set to suit your application.
Any number of real time tasks can share the same priority - facilitating application design. User
tasks can also
share a priority of zero with the idle task.
Priority numbers should be chosen to be as close and as low as possible. For example, if your
application has
3 user tasks that must all be at different priorities then use priorities 3 (highest), 2 and 1 (lowest -
the idle task
uses priority 0).

How RTOS work :
RTOS Supported architectures :
Altera Nios II
ARM architecture
Atmel
Cortus
Cypress
Energy Micro
Fujitsu
Freescale
PIC – AVR – 8051 – PowerPC – x86

Related projects
SafeRTOS
SafeRTOS was constructed as a complementary offering to FreeRTOS, with common
functionality but with a uniquely designed safety-critical implementation. When the
FreeRTOS functional model was subjected to a full HAZOP, weakness with respect to user
misuse and hardware failure within the functional model and API were identified and
resolved. The resulting requirements set was put through a full IEC 61508 SIL 3
development life cycle, the highest possible for a software-only component.
SafeRTOS was developed by WITTENSTEIN high integrity systems, in partnership with Real
Time Engineers Ltd, primary developer of the FreeRTOS project.Both SafeRTOS and
FreeRTOS share the same scheduling algorithm, have similar APIs, and are otherwise very
similar, but they were developed with differing objectives.SafeRTOS was developed solely
in the C language to meet requirements for certification to IEC61508.
SafeRTOS is known for its ability, unique among Operating Systems, to reside solely in the
on-chip read only memory of a microcontroller, thus enabling the pre-certification of complete
Hardware and Software systems to IEC61508 or other safety or reliability operating
standards.When implemented in hardware memory, SafeRTOS code can only be utilized in
its original configuration, so certification testing of systems using this OS need not re-test
this portion of their designs during the functional safety certification process.
SafeRTOS is included in the ROM of some Stellaris Microcontrollers[11] from Texas
Instruments. This allows SafeRTOS to be used in commercial applications without having to
purchase its source code. In this usage scenario, a simple C header file is used to map
SafeRTOS API functions to their location in read-only memory. The use of read-only
memory is ideal because the code it contains cannot be changed - eliminating the
possibility of user error, and ensuring the code that was originally tested remains
absolutely identical throughout the project lifetime. It will not need re-testing as the
application code grows and evolves around it. The burden of complex kernel testing is
removed as the already certified and approved certification evidence, including the test
plan, code and results, can be purchased "off the shelf".
OpenRTOS
Another project related to FreeRTOS, one with identical code but different licensing &
pricing, is OpenRTOS from the commercial firm WITTENSTEIN Aerospace and Simulation
Ltd. The commercial licensing terms for OpenRTOS remove all references to the GNU
General Public License (GPL). For example: one of the conditions of using FreeRTOS in a
commercial product is that the user is made aware of the use of FreeRTOS and the source
code of FreeRTOS, but not the commercial product's application code, must be provided
upon request. OpenRTOS is a commercial product only available via purchase and doesn't
have this licensing requirement. OpenRTOS license purchasers also have access to full
technical support
FREERTOS
FreeRTOS is a popular[1] real-time operating system kernel for embedded devices, that has been
ported to 35microcontrollers. It is distributed under the GPL with an additional restriction and
optional exception. The restriction forbids benchmarking while the exception permits
users' proprietary code to remain closed source while maintaining the kernel itself as open
source, thereby facilitating the use of FreeRTOS in proprietary applications

Implementation
FreeRTOS is designed to be small and simple. The kernel itself consists of only three or four
C files. To make the code readable, easy to port, and maintainable, it is written mostly in C,
but there are a few assembly functions included where needed (mostly in architecture-
specific scheduler routines).
FreeRTOS provides methods for multiple threads or tasks, mutexes, semaphores and software timers.
A tick-less mode is provided for low power applications. Thread priorities are supported. In
addition there are four schemes of memory allocation provided:
allocate only;
allocate and free with a very simple, fast, algorithm;
a more complex but fast allocate and free algorithm with memory coalescence;
and C library allocate and free with some mutual exclusion protection.
There are none of the more advanced features typically found in operating
systems like Linux or Microsoft Windows, such as device drivers, advanced memory management, user
accounts, and networking. The emphasis is on compactness and speed of execution.
FreeRTOS can be thought of as a 'thread library' rather than an 'operating system',
although command line interface and POSIX-like I/O abstraction add-ons are available.
FreeRTOS implements multiple threads by having the host program call a thread tick
method at regular short intervals. The thread tick method switches tasks depending on
priority and a round-robin scheduling scheme. The usual interval is 1/1000 of a second to 1/100
of a second, via an interrupt from a hardware timer, but this interval is often changed to
suit a particular application.
Key features
Very small memory footprint, low overhead, and very fast execution.
Tick-less option for low power applications.
Equally good for hobbyists who are new to OSes, and professional developers working on
commercial products.
Scheduler can be configured for both preemptive or cooperative operation.
Coroutine support (Coroutine in FreeRTOS is a very simple and lightweight task that has very
limited use of stack)
Trace support through generic trace macros. Tools such as Tracealyzer (a.k.a. FreeRTOS+Trace,
provided by the FreeRTOS partner Percepio) can thereby record and visualize the runtime
behavior of FreeRTOS-based systems. This includes task scheduling and kernel calls for
semaphore and queue operations. Tracealyzer is a commercial tool, but also available in a
feature-limited free version. The full version is priced at US$1,200.

IDE
ATmel studio
CodeBlocks
Coding with FREERTOS
Lab1
/*
* BinarySemaphore.c
*
* Created: 18/07/2016 01:08:44 ‫م‬
* Author: Lab232
*/
/* OS Header Files */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "event_groups.h"
/* Tasks Proto. */
void T_Button(void *pvParam);
void T_Led(void *pvParam);
void port_init(void);
/* OS Serv. Decl. */
xSemaphoreHandle sBtnPressedEvent;

int main(void)
{
port_init();
vSemaphoreCreateBinary(sBtnPressedEvent,0);
xTaskCreate(T_Button,NULL,100,NULL,1,NULL);
xTaskCreate(T_Led,NULL,100,NULL,2,NULL);
vTaskStartScheduler();
}
void T_Button(void *pvParam)
{
while(1)
{
if ( (PIND & (1<<PD3)) )
{ vTaskDelay(10);
while((PIND & (1<<PD3)));
xSemaphoreGive(sBtnPressedEvent);
}
}
}
void T_Led(void *pvParam)
{
while(1)
{
if(xSemaphoreTake(sBtnPressedEvent,0xffff))
{
PORTD^= (1<<PD7);
vTaskDelay(1000);
PORTD^= (1<<PD7);
vTaskDelay(1000);

}
}
}
void port_init(void)
{
/* Btn D3 */
DDRD &= ~(1<<PD3);
PORTD &= ~(1<<PD3);
/* Led D7 */
DDRD |= (1<<PD7);
PORTD &= ~(1<<PD7);
}
lab 2 counting
/*
* BinarySemaphore.c
*
* Created: 18/07/2016 01:08:44 ‫م‬
* Author: Lab232
*/
#include "task.h"
#include "queue.h"
#include "semphr.h"

/* Tasks Proto. */
void T_Button(void *pvParam);
void T_Led(void *pvParam);
void port_init(void);
xSemaphoreHandle sBtnPressedEvent;
int main(void)
{
port_init();
sBtnPressedEvent = xSemaphoreCreateCounting(5,0);
//vSemaphoreCreateBinary(sBtnPressedEvent,0);
xTaskCreate(T_Button,NULL,100,NULL,1,NULL);
xTaskCreate(T_Led,NULL,100,NULL,2,NULL);
}
void T_Button(void *pvParam)
{
while(1)
{
if ( (PIND & (1<<PD3)) )
{
vTaskDelay(10);

while((PIND & (1<<PD3)));
xSemaphoreGive(sBtnPressedEvent);
}
}
}
void T_Led(void *pvParam)
{
while(1)
{
if(xSemaphoreTake(sBtnPressedEvent,0xffff))
{
PORTD^= (1<<PD7);
vTaskDelay(1000);
PORTD^= (1<<PD7);
vTaskDelay(1000);
}
}
}
void port_init(void)
{
/* Btn D3 */
DDRD &= ~(1<<PD3);
PORTD &= ~(1<<PD3);
/* Led D7 */

DDRD |= (1<<PD7);
PORTD &= ~(1<<PD7);
}
lab 3 uart
/*
* BinarySemaphore.c
*
* Created: 18/07/2016 01:08:44 ‫م‬
* Author: Lab232
*/
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "usart_driver.h"
/* Tasks Proto. */
void T_Send(void *pvParam);
void T_Receive(void *pvParam);

xQueueHandlemqTerm;
int main(void)
{
usart_init(9600);
mqTerm = xQueueCreate(100,1);
xTaskCreate(T_Send,NULL,100,NULL,1,NULL);
xTaskCreate(T_Receive,NULL,100,NULL,2,NULL);
}
void T_Send(void *pvParam)
{
unsigned char qsend = 0;
while(1)
{
qsend = usart_getc();
xQueueSend(mqTerm,&qsend,0XFFFF);
}
}
void T_Receive(void *pvParam)
{
unsigned char qreceive = 0;
while(1)
{
xQueueReceive(mqTerm,&qreceive,0XFFFF);
usart_putc(qreceive);
}
}

CH3
Integrated circuit design
integrated circuit design, or IC design, is a subset of electronics engineering,
encompassing the particular logic and circuit design techniques required to design integrated
circuits, or ICs. ICs consist of miniaturized electronic components built into an electrical network on
a monolithic semiconductorsubstrate by photolithography.
IC design can be divided into the broad categories of digital and analog IC design. Digital IC
design is to produce components such as microprocessors, FPGAs, memories (RAM, ROM,
and flash) and digital ASICs. Digital design focuses on logical correctness, maximizing circuit
density, and placing circuits so that clock and timing signals are routed efficiently. Analog
IC design also has specializations in power IC design and RF IC design. Analog IC design is
used in the design of op-amps, linear regulators, phase locked loops, oscillators and active filters.
Analog design is more concerned with the physics of the semiconductor devices such as
gain, matching, power dissipation, and resistance. Fidelity of analog signal amplification
and filtering is usually critical and as a result, analog ICs use larger area active devices
than digital designs and are usually less dense in circuitry.
Modern ICs are enormously complicated. An average desktop computer chip, as of 2015,
has over 1 billion transistors. The rules for what can and cannot be manufactured are also
extremely complex. Common IC processes of 2015 have more than 500 rules.
Furthermore, since the manufacturing process itself is not completely predictable,
designers must account for its statistical nature. The complexity of modern IC design, as well
as market pressure to produce designs rapidly, has led to the extensive use of automated
design tools in the IC design process. In short, the design of an IC using EDA software is the
design, test, and verification of the instructions that the IC is to carry out.

Layout view of a simple CMOS Operational Amplifier (inputs are to the left and the compensation capacitor
is to the right). The metal layer is coloured blue, green and brown are N- and P-doped Si, the polysilicon is
red and vias are crosses.
Fundamentals
Integrated circuit design involves the creation of electronic components, such
as transistors, resistors, capacitors and the metallic interconnect of these components onto a piece
of semiconductor, typically silicon. A method to isolate the individual components formed in
the substrate is necessary since the substrate silicon is conductive and often forms an active
region of the individual components. The two common methods are p-n junction
isolation and dielectric isolation. Attention must be given to power dissipation of transistors and
interconnect resistances and current density of the interconnect, contacts and vias since ICs
contain very tiny devices compared to discrete components, where such concerns are less
of an issue. Electromigration in metallic interconnect and ESD damage to the tiny components
are also of concern. Finally, the physical layout of certain circuit subblocks is typically
critical, in order to achieve the desired speed of operation, to segregate noisy portions of
an IC from quiet portions, to balance the effects of heat generation across the IC, or to
facilitate the placement of connections to circuitry outside the IC.

Design steps
A typical IC design cycle involves several steps:
Feasibility study and die size estimate
Function analysis
System Level Design
Analogue Design, Simulation & Layout
Digital Design, Simulation & Synthesis
System Simulation & Verification
Design For Test and Automatic test pattern generation
Design for manufacturability (IC)
Tape-in
Mask data preparation
Tape-out
Wafer fabrication
Die test
Packaging
Post silicon validation and integration
Device characterization
Tweak (if necessary)
Datasheet generation Portable Document Format
Ramp up
Production
Yield Analysis / Warranty Analysis Reliability (semiconductor)
Failure analysis on any returns
Plan for next generation chip using production information if possible
Roughly saying, digital IC design can be divided into three parts.
Electronic system-level design: This step creates the user functional specification. The user
may use a variety of languages and tools to create this description. Examples include
a C/C++ model, SystemC, SystemVerilog Transaction Level Models, Simulink and MATLAB.
RTL design: This step converts the user specification (what the user wants the chip to do)
into a register transfer level (RTL) description. The RTL describes the exact behavior of the
digital circuits on the chip, as well as the interconnections to inputs and outputs.
Physical design: This step takes the RTL, and a library of available logic gates, and creates
a chip design. This involves figuring out which gates to use, defining places for them,
and wiring them together.
Note that the second step, RTL design, is responsible for the chip doing the right thing. The
third step, physical design, does not affect the functionality at all (if done correctly) but
determines how fast the chip operates and how much it costs.

Design Process
Microarchitecture and System-level Design
The initial chip design process begins with system-level design and microarchitecture
planning. Within IC design companies, management and often analytics will draft a
proposal for a design team to start the design of a new chip to fit into an industry
segment. Upper-level designers will meet at this stage to decide how the chip will operate
functionally. This step is where an IC's functionality and design are decided. IC designers
will map out the functional requirements, verification testbenches, and testing
methodologies for the whole project, and will then turn the preliminary design into a
system-level specification that can be simulated with simple models using languages like
C++ and MATLAB and emulation tools. For pure and new designs, the system design stage
is where an Instruction set and operation is planned out, and in most chips existing instruction
sets are modified for newer functionality. Design at this stage is often statements such
as encodes in the MP3 format or implements IEEE floating-point arithmetic. At later stages in
the design process, each of these innocent looking statements expands to hundreds of
pages of textual documentation.
RTL design
Upon agreement of a system design, RTL designers then implement the functional models
in a hardware description language like Verilog, SystemVerilog, or VHDL. Using digital design
components like adders, shifters, and state machines as well as computer architecture
concepts like pipelining, superscalar execution, and branch prediction, RTL designers will
break a functional description into hardware models of components on the chip working
together. Each of the simple statements described in the system design can easily turn
into thousands of lines of RTL code, which is why it is extremely difficult to verify that the
RTL will do the right thing in all the possible cases that the user may throw at it.
To reduce the number of functionality bugs, a separate hardware verification group will
take the RTL and design testbenches and systems to check that the RTL actually is
performing the same steps under many different conditions, classified as the domain
of functional verification. Many techniques are used, none of them perfect but all of them
useful – extensive logic simulation, formal methods, hardware emulation, lint-like code checking, code
coverage, and so on.
A tiny error here can make the whole chip useless, or worse. The famous Pentium FDIV
bug caused the results of a division to be wrong by at most 61 parts per million, in cases
that occurred very infrequently. No one even noticed it until the chip had been in
production for months. Yet Intel was forced to offer to replace, for free, every chip sold until
they could fix the bug, at a cost of $475 million (US).

Physical design
RTL is only a behavioral model of the actual functionality of what the chip is supposed to
operate under. It has no link to a physical aspect of how the chip would operate in real life
at the materials, physics, and electrical engineering side. For this reason, the next step in
the IC design process, physical design stage, is to map the RTL into actual geometric
representations of all electronics devices, such as capacitors, resistors, logic gates, and
transistors that will go on the chip.
The main steps of physical design are listed below. In practice there is not a
straightforward progression - considerable iteration is required to ensure all objectives are
met simultaneously. This is a difficult problem in its own right, called design closure.
Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the
chip.
Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O)
pins are assigned and large objects (arrays, cores, etc.) are placed.
Placement: The gates in the netlist are assigned to nonoverlapping locations on the die
area.
Logic/placement refinement: Iterative logical and placement transformations to close
performance and power constraints.
Clock insertion: Clock signal wiring is (commonly, clock trees) introduced into the design.
Routing: The wires that connect the gates in the netlist are added.
Postwiring optimization: Performance (timing closure), noise (signal integrity), and yield (Design
for manufacturability) violations are removed.
Design for manufacturability: The design is modified, where possible, to make it as easy and
efficient as possible to produce. This is achieved by adding extra vias or adding dummy
metal/diffusion/poly layers wherever possible while complying to the design rules set by
the foundry.
Final checking: Since errors are expensive, time consuming and hard to spot, extensive
error checking is the rule, making sure the mapping to logic was done correctly, and checking that the
manufacturing rules were followed faithfully.
Tapeout and mask generation: the design data is turned into photomasks in mask data
preparation.
Analog design
Before the advent of the microprocessor and software based design tools, analog ICs were
designed using hand calculations and process kit parts. These ICs were low complexity
circuits, for example, op-amps, usually involving no more than ten transistors and few
connections. An iterative trial-and-error process and "overengineering" of device size was
often necessary to achieve a manufacturable IC. Reuse of proven designs allowed
progressively more complicated ICs to be built upon prior knowledge. When inexpensive
computer processing became available in the 1970s, computer programs were written to

simulate circuit designs with greater accuracy than practical by hand calculation. The first
circuit simulator for analog ICs was called SPICE (Simulation Program with Integrated
Circuits Emphasis). Computerized circuit simulation tools enable greater IC design
complexity than hand calculations can achieve, making the design of
analog ASICs practical. The computerized circuit simulators also enable mistakes to be
found early in the design cycle before a physical device is fabricated. Additionally, a
computerized circuit simulator can implement more sophisticated device models and
circuit analysis too tedious for hand calculations, permitting Monte Carlo analysis and process
sensitivity analysis to be practical. The effects of parameters such as temperature
variation, doping concentration variation and statistical process variations can be
simulated easily to determine if an IC design is manufacturable. Overall, computerized circuit
simulation enables a higher degree of confidence that the circuit will work as expected
upon manufacture.
Coping with variability
A challenge most critical to analog IC design involves the variability of the individual
devices built on the semiconductor chip. Unlike board-level circuit design which permits
the designer to select devices that have each been tested and binned according to value,
the device values on an IC can vary widely which are uncontrollable by the designer. For
example, some IC resistors can vary ±20% and β of an integrated BJT can vary from 20 to
100. In the latest CMOS processes, β of vertical PNP transistors can even go below 1. To
add to the design challenge, device properties often vary between each processed
semiconductor wafer. Device properties can even vary significantly across each individual
IC due to doping gradients. The underlying cause of this variability is that many
semiconductor devices are highly sensitive to uncontrollable random variances in the
process. Slight changes to the amount of diffusion time, uneven doping levels, etc. can
have large effects on device properties.
Some design techniques used to reduce the effects of the device variation are:
Using the ratios of resistors, which do match closely, rather than absolute resistor value.
Using devices with matched geometrical shapes so they have matched variations.
Making devices large so that statistical variations becomes an insignificant fraction of the
overall device property.
Segmenting large devices, such as resistors, into parts and interweaving them to cancel
variations.
Using common centroid device layout to cancel variations in devices which must match
closely (such as the transistor differential pair of an op amp).

Vendors
The three largest companies[citation needed] selling electronic design automation tools
are Synopsys, Cadence, and Mentor Graphics.
We worked on cadence
Cadence Flow
1. Create Library A. Tools >>> Library Manager
B. File >>> New >>> Library
C. Give a name and attach it to a technology library

2. Schematic
A. Create a cell view

B. Draw a schematic i. Add instances – pmos You can modify Width of transistors. Don’t modify
length unless you have a special purpose. You should select a NCSU_Analog_Parts library.

ii. Add instances – nmos, vdd, and gnd

iii. Add wires: Create >> Wire

iv. Add pins: Create >> Pin

We have for different types of direction. For schematics, we only use two types, input and output.
InputOutput type is for supply changes, and it is necessary only for layout. We will discuss about
this later.

Now, we completed a schematic design. Let’s move on the next phase.

simulation
3. Run Spectre simulation We will run spectre simulation. This section is for both schematics and
layouts. I will show an example for a schematic. You can do the same thing for a layout. A. Launch
ADE (Analog Design Environment) L Launch >>ADE L
B. Basic setup Check if your simulator is spectre. You can modify project directory.

C. Model Libraries You can download a library file at the DEN blackboard.

D. Simuli Define input signals include supply nets

E. Choose a type of analysis - transient You can choose ‘dc’ if you want to do dc analysis

A. Choose tran B. Give Stop time which means how long you want to simulate C. Select moderate
as accuracy defaults D. Do not check Transient Noise E. Check Enabled

F. Select signals to plot Outputs Æ To Be Plotted Æ Select On Schematic Click a signal (Pin) on a
schematic/extracted.
G. Run simulation Simulation Æ Run

Layout
4. Layout
It’s time to draw layout. Schematics are for verifying your design very roughly. They don’t consider
physical features like parasitic capacitances. After determining your design variables by schematics,
you need to draw layouts. Design flow of layouts is very similar to one of schematics, but it has
additional step which is LVS check. It is for check if your layout is identical to the schematic or not.
Hence, this step is very important. If your logic doesn’t pass this step, you may lose significant
points for that.

A. Create a layout

B. Add an instance - nmos

C. Add more instances – pmos, ptap, ntap, and m1_ploy

You can select alternate view of a layout. Try ‘Shift + f’ and ‘Ctrl + f’.

D. Draw metal1 There are few ways for drawing metal, but I recommend you use ‘path’. It’s quite
convenience than others. Create Æ Shape Æ Path First of all, you should select metal1 on LSW
window. Default width for metal1 is 0.3, which means 300nm (3 λ). You can draw metal layer
simply by clicking

E. Run DRC This step checks if your layout follows design rules. Verify Æ DRC

We have five errors. It is because a gnd metal layer is too close to an nmos transistor. After
modifying layout, run DRC again.

F. Add pins We had two pins on a schematic, which are ‘in’ and ‘out’. Pins are for assigning signals
to physical device, so we assign voltage level of gnd and vdd by using pins. Hence, we have 4 pins
for the layout, which are ‘in’, ‘out’, ‘gnd!’, and ‘vdd!’. Create Æ Pin

Check ‘Display Terminal Name’ if you want to
see pin name on the layout.
Click ‘Display Terminal Option

G. Extract A layout is just a picture. If you need to run simulation using the layout, you should
convert it to the other format. It is done by extracting. It’s something like compiling a code.

Select ‘Extract_parastic_cap’ as a switch name,
otherwise your extracted design won’t have parasitic
capacitances.

H. Run LVS As I mentioned before, this step is very important for your grading. More complicated
design, more time will be required for debugging LVS. Verify Æ LVS Keep in mind. You SHOULD
compare your schematic with EXTRACTED.

Run Spectre simulation It is same as schematics. Go to step ‘4. Run Spectre simulation’.

CH4 PCB Design with ( OrCAD )
OrCAD is a proprietary software tool suite used primarily for electronic design automation (EDA).
The software is used mainly by electronic design engineers and electronic technicians to
create electronic schematics and electronic prints for manufacturing printed circuit boards.
The name OrCAD is a portmanteau, reflecting the company and its software's
origins: Oregon + CAD.
Original author(s)
Cadence Design Systems
Developer(s) Cadence Design Systems
Stable release 16.6
Written in C/C++
Operating system Microsoft Windows
Type Electronic design automation
OrCAD PCB Designer
OrCAD PCB Designer is a printed circuit board designer application, and part of the OrCAD
circuit design suite. PCB Designer includes various automation features for PCB design,
board-level analysis and design rule checks (DRC).
The PCB design may be accomplished by manually tracing PCB tracks, or using the Auto-
Router provided. Such designs may include curved PCB tracks, geometric shapes, and
ground planes.
PCB Designer integrates with OrCAD Capture, using the component information system
(CIS) to store information about a certain circuit symbol and its matching PCB footprint
Introduction
Orcad is a suite of tools from Cadence for the design and layout of printed circuit boards (PCBs).
We are currently using version 9.2 of the Orcad suite. This document will give you a crash course in
designing an entire circuit board from start to finish. This will be a very small and simple circuit,
but it will demonstrate the major concepts and introduce the tools behind completing a PCB design.
After you have completed this tutorial, you will know all the steps needed to make PCBs using
Orcad. The circuit you will design is shown in the figure below. It is a dual polarity adjustable
power supply. A center tapped transformer, some diodes, 2 IC’s and few resistors and capacitors are

included in the circuit.
OrCAD Flow
Starting a New Schematic Project
To create a new project, first start Orcad Capture CIS then click File ÆNew ÆProject. You will see
the following dialog box. Browse to the PowerSupplyschematic directory that you created and
name the project psu (short for Power Supply Unit). The project name is more important than the
name of your project folder. It is used as the name of all the files in your project. So give the project
a meaningful and short name. Select the PC Board Wizard radio button and click OK. In the next
dialog box uncheck Enable project simulation. Click Next and then remove all libraries from RHS
then click Finish. You should see an empty schematic page and a project window like the following.

About Libraries and Parts
Orcad allows you to have libraries of part symbols for use in schematic entry. These libraries are
kept in separate files that are included in the project workspace. This allows you to reuse libraries in
other designs. Enormous parts are already in existing Orcad libraries. You can use these parts
directly from these libraries. Open your schematic page from the Project window if it is not open.
Your schematic is located in psu.dsnÆSCHEMATIC1ÆPAGE1 in the project window. Now click
on the Place Part tool from the right toolbar. The following dialog box appears.

2- Creating a Schematic Parts Library
Orcad allows you to create your own libraries of part symbols. You can create symbols for those
parts, which you are unable to find in Orcad libraries, or you want to draw a part symbol according
to your own standard and convenience. We will now create symbols for some of the parts in our
design and use the rest from the Orcad built-in libraries. For this we have to add a new library to our
design. To do this, highlight the psu.dsn in the project window and click File ÆNew ÆLibrary.
Right-click the library1.olb file in the project window and select Save As... Name the file
psu_symbols and place it in the libraries directory that you created earlier. Your project window will
now look like the figure below. You are now ready to add parts to your library

3- Creating Schematic Symbols
To add a new part to your library, right-click the library file and select New Part. This will bring up
a dialog box for New Part Properties. Make the entries in the dialog box so that it looks like the
following.

4- Schematic Entry
You are now ready to start placing the electrical components for your design. The circuit that we
will be drawing is shown in the beginning of this tutorial in the hand drawn form. We will need all
the parts that are included in that circuit diagram. Open up the schematic page and click the Place
Part tool on the toolbar on the right side of the screen. Here you will have to add those libraries,
which contain your desired parts. As a novice designer, you might experience difficulties in finding
a particular part because there are so many libraries and thousands of parts in each of them. But you
can always do away with this difficulty if you carefully read the library name. The Part Search
feature will certainly be very helpful in these circumstances.

5- Preparing for Layout
The transference phase (transferring the design from Capture to Layout) is the second phase of your
project and is very crucial. Annotating your design is the first step of this phase

References:
FPGA
Circuit design with VHDL, by Volnei A. Pedroni
VHDL:Programming by Example, by Douglas L. Perry,Fourth Edition
Spartan 3E Starter Board, by Digilant
VHDL Analysis and Modeling of Digital Systems, Zainalabedin Navabi, 1993
Basic VHDL Course, Dr. Ayman Wahba
The Designer’s Guide to VHDL, Peter J. Ashenden, 1996
Language Reference Manual, IEEE, 1999
VHDL Programming by Example, Douglas L. Perry, 2002
HDL Chip Design, Douglas J. Smith, 1996
PSOC & RTOS
Using the FreeRTOS Real Time Kernel - A Practical Guide_opened
FreeRTOS_manual
Real-Time.MicroC_OS_RTOS_CMP
Simply AVR Book
Cypress Hits Half-Billion Mark in Shipments of PSoC Programmable System-on-
Chip Devices
IC Design
Electronic Design Automation For Integrated Circuits Handbook, by Lavagno, Martin, and
Scheffer
Cadence Tutorial
for Cadence version 6.1 Inkwon Hwang
Feb, 2010
PCB Design
Orcad Tutorial
OrCAD Flow Tutorial

Final report NTI FPGA&RTOS&Cadeance ICFB&

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