This document proposes and evaluates a modular lifting method to improve the cycle properties of quasi-cyclic low-density parity-check (QC-LDPC) codes. The method involves lifting the parity check matrix of a base graph by shifting the circulant submatrices by powers of a modular value. This approach is shown to reduce the number of harmful trapping sets compared to existing lifting methods, resulting in up to 0.3 dB gain in decoding performance based on simulations of 5G standards codes. The modular lifting allows for more flexible shifts of the variable and check node rings compared to previous approaches while still maintaining the quasi-cyclic structure of the codes.
Tsp 2018 presentation Simulated Annealing Method for Construction of High-Gi...Usatyuk Vasiliy
Presentation which present a simulated annealing method that
construct high-girth quasi-cyclic low-density parity check (QC-LDPC) codes. The proposed method is applicable to both
regular and irregular protograph codes. The method show
improvement in term of minimal circulant size compare with
previous described methods: Hill-Climbing and improved PEG.
Simulated results are presented to demonstrate performance gain of proposed construction method in error-floor region under base graph 2 (BG2) using 5G eMBB standard length adaption method.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware...奈良先端大 情報科学研究科
Outsourcing of IC fabrication components has initiated the
potential threat of design tempering using hardware Trojans and also has drawn the attention of government agencies and the semiconductor industry. The added functionality, known as hardware Trojan, poses major detection and isolation challenges. This paper presents a hardware Trojan detection technique that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified LOC test pattern application method is proposed so as to maximize dynamic power consumption of any target segment. The proposed architecture allows activating any target segment of scan chain and keeping others freeze which reduces total circuit switching activity. This helps magnify the Trojan’s contribution to selected segment by increasing dynamic power
consumption. Experimental results for ISCAS89 benchmark circuit demonstrate its effectiveness in side-channel analysis.
Tsp 2018 presentation Simulated Annealing Method for Construction of High-Gi...Usatyuk Vasiliy
Presentation which present a simulated annealing method that
construct high-girth quasi-cyclic low-density parity check (QC-LDPC) codes. The proposed method is applicable to both
regular and irregular protograph codes. The method show
improvement in term of minimal circulant size compare with
previous described methods: Hill-Climbing and improved PEG.
Simulated results are presented to demonstrate performance gain of proposed construction method in error-floor region under base graph 2 (BG2) using 5G eMBB standard length adaption method.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware...奈良先端大 情報科学研究科
Outsourcing of IC fabrication components has initiated the
potential threat of design tempering using hardware Trojans and also has drawn the attention of government agencies and the semiconductor industry. The added functionality, known as hardware Trojan, poses major detection and isolation challenges. This paper presents a hardware Trojan detection technique that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified LOC test pattern application method is proposed so as to maximize dynamic power consumption of any target segment. The proposed architecture allows activating any target segment of scan chain and keeping others freeze which reduces total circuit switching activity. This helps magnify the Trojan’s contribution to selected segment by increasing dynamic power
consumption. Experimental results for ISCAS89 benchmark circuit demonstrate its effectiveness in side-channel analysis.
First-Order Open Loop VCO-Based ADC with XOR Gates as differentiator IJMTST Journal
In this paper, detail analysis for an open loop Voltage-Controlled Oscillator (VCO)-based ADC is discussed.
The ADC includes a ring oscillator with several inverters to extract the phases. The circuit uses the VCO as an
integrator in time domain and it uses the inverters in the VCO to perform multi-bit quantization. XOR gates
are used to operate as differentiators and all the circuit is done through CMOS transistors. Mathematical
analysis has been included to p
Demonstrating Quantum Speed-Up with a Two-Transmon Quantum Processor Ph.D. d...Andreas Dewes
The accompanying slides of my PhD defense presentation on experimental quantum computing, held at the CEA Saclay in November 2012.
Please not that some slides appear "broken" due to the animation sequences they contain, to get a correct view of the presentation, just download the PPTX.
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
Cycle’s topological optimizations and the iterative decoding problem on gener...Usatyuk Vasiliy
We consider several problem related to graph model related to error-correcting codes. From base problem of cycle broken, trapping set elliminating and bypass to fundamental problem of graph model. Thanks to the hard work of Michail Chertkov, Michail Stepanov and Andrea Montanari which inspirit me...
Slides presented at Applied Mathematics Day, Steklov Mathematical Institute of the Russian Academy of Sciences September 22, 2017 http://www.mathnet.ru/conf1249
A REVIEW OF LOW POWERAND AREA EFFICIENT FSM BASED LFSR FOR LOGIC BISTjedt_journal
Built in Self Test circuits enable an integrated circuit to test itself. Built in Self Test reduces test and maintenance costs for an integrated circuit by eliminating the need for expensive test equipment. Built in Self Test also allows an integrated circuit to test at its normal operating speed which is very important for detecting timing faults. Despite all of these advantages Built in Self Test has seen limited use in industry because of area and performance overhead and increased design time. This paper presents automated techniques for implementing BIST in a way that minimizes area and performance overhead. This approach allows applying at-speed test patterns and eliminates the need for an external tester. Proper design of the test pattern generator contributes to reduction in the power consumption of the CUT and the overall power consumption of the BIST circuitry. We have proposed FSM based LFSR which generate maximum correlation among the patterns and targeted on c432, c1908 and c3540 benchmark circuits to validate test power, achieved significant improved in power up to 15% compared to conventional test generator and also achieved optimal area overhead,designed using Verilog HDL and implemented using Xilinx 14.3 and Cadence tool.
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCEcscpconf
In recent years, various chaos based modulation schemes were evolved, of which the CS-DCSK
modulation technique provides better BER performance and bandwidth efficiency, due to its
code domain approach. The QCSK modulation technique provides double benefit: higher data
rate with similar BER performance and same bandwidth occupation as DCSK. By combining
the advantage of code shifted differential chaos shift keying (CS-DCSK) and Quadrature chaos
shift keying (QCSK) scheme, a novel CS-QCSK modulation scheme called code shifted
Quadrature chaos shift keying is proposed. The noise performance of CS-QCSK is better to
most conventional modulation schemes and also provides an increased data transmission rates
with greatly improved robustness. Analytical expressions for the bit-error rates are derived for
both AWGN channel and Rayleigh multipath fading channel. The simulation result shows that
the proposed method outperforms classical chaotic modulation schemes in terms of bit error rate (BER).
Computing the code distance of linear binary and ternary block codes using p...Usatyuk Vasiliy
We introduce a probabilistic algorithm for minimum distance of linear codes. Algorithm use Kannan embeding techniques to construct lattice from binary and ternary block code. Using permutation of code basis and QR-transformation we optimize Exp and Var for area of search under probabalistical shortest vector problem
In this short survey we consider example of most promising practical approach to improve coding gain under Factor graph in high performance regime (when we have enougth iteration budget [complexity and power comsumption for asic] to waiting recovery of variable nodes) Multi-Edge Type LDPC codes.
First-Order Open Loop VCO-Based ADC with XOR Gates as differentiator IJMTST Journal
In this paper, detail analysis for an open loop Voltage-Controlled Oscillator (VCO)-based ADC is discussed.
The ADC includes a ring oscillator with several inverters to extract the phases. The circuit uses the VCO as an
integrator in time domain and it uses the inverters in the VCO to perform multi-bit quantization. XOR gates
are used to operate as differentiators and all the circuit is done through CMOS transistors. Mathematical
analysis has been included to p
Demonstrating Quantum Speed-Up with a Two-Transmon Quantum Processor Ph.D. d...Andreas Dewes
The accompanying slides of my PhD defense presentation on experimental quantum computing, held at the CEA Saclay in November 2012.
Please not that some slides appear "broken" due to the animation sequences they contain, to get a correct view of the presentation, just download the PPTX.
Optimal and Power Aware BIST for Delay Testing of System-On-ChipIDES Editor
Test engineering for fault tolerant VLSI systems is
encumbered with optimization requisites for hardware
overhead, test power and test time. The high level quality of
these complex high-speed VLSI circuits can be assured only
through delay testing, which involves checking for accurate
temporal behavior. In the present paper, a data-path based
built-in test pattern generator (TPG) that generates iterative
pseudo-exhaustive two-patterns (IPET) for parallel delay
testing of modules with different input cone capacities is
implemented. Further, in the present study a CMOS
implementation of low power architecture (LPA) for scan based
built-in self test (BIST) for delay testing and combinational
testing is carried out. This reduces test power dissipation in
the circuit under test (CUT). Experimental results and
comparisons with pre-existing methods prove the reduction
in hardware overhead and test-time.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
Cycle’s topological optimizations and the iterative decoding problem on gener...Usatyuk Vasiliy
We consider several problem related to graph model related to error-correcting codes. From base problem of cycle broken, trapping set elliminating and bypass to fundamental problem of graph model. Thanks to the hard work of Michail Chertkov, Michail Stepanov and Andrea Montanari which inspirit me...
Slides presented at Applied Mathematics Day, Steklov Mathematical Institute of the Russian Academy of Sciences September 22, 2017 http://www.mathnet.ru/conf1249
A REVIEW OF LOW POWERAND AREA EFFICIENT FSM BASED LFSR FOR LOGIC BISTjedt_journal
Built in Self Test circuits enable an integrated circuit to test itself. Built in Self Test reduces test and maintenance costs for an integrated circuit by eliminating the need for expensive test equipment. Built in Self Test also allows an integrated circuit to test at its normal operating speed which is very important for detecting timing faults. Despite all of these advantages Built in Self Test has seen limited use in industry because of area and performance overhead and increased design time. This paper presents automated techniques for implementing BIST in a way that minimizes area and performance overhead. This approach allows applying at-speed test patterns and eliminates the need for an external tester. Proper design of the test pattern generator contributes to reduction in the power consumption of the CUT and the overall power consumption of the BIST circuitry. We have proposed FSM based LFSR which generate maximum correlation among the patterns and targeted on c432, c1908 and c3540 benchmark circuits to validate test power, achieved significant improved in power up to 15% compared to conventional test generator and also achieved optimal area overhead,designed using Verilog HDL and implemented using Xilinx 14.3 and Cadence tool.
A NOVEL CHAOS BASED MODULATION SCHEME (CS-QCSK) WITH IMPROVED BER PERFORMANCEcscpconf
In recent years, various chaos based modulation schemes were evolved, of which the CS-DCSK
modulation technique provides better BER performance and bandwidth efficiency, due to its
code domain approach. The QCSK modulation technique provides double benefit: higher data
rate with similar BER performance and same bandwidth occupation as DCSK. By combining
the advantage of code shifted differential chaos shift keying (CS-DCSK) and Quadrature chaos
shift keying (QCSK) scheme, a novel CS-QCSK modulation scheme called code shifted
Quadrature chaos shift keying is proposed. The noise performance of CS-QCSK is better to
most conventional modulation schemes and also provides an increased data transmission rates
with greatly improved robustness. Analytical expressions for the bit-error rates are derived for
both AWGN channel and Rayleigh multipath fading channel. The simulation result shows that
the proposed method outperforms classical chaotic modulation schemes in terms of bit error rate (BER).
Computing the code distance of linear binary and ternary block codes using p...Usatyuk Vasiliy
We introduce a probabilistic algorithm for minimum distance of linear codes. Algorithm use Kannan embeding techniques to construct lattice from binary and ternary block code. Using permutation of code basis and QR-transformation we optimize Exp and Var for area of search under probabalistical shortest vector problem
In this short survey we consider example of most promising practical approach to improve coding gain under Factor graph in high performance regime (when we have enougth iteration budget [complexity and power comsumption for asic] to waiting recovery of variable nodes) Multi-Edge Type LDPC codes.
Solving channel coding simulation and optimization problems using GPUUsatyuk Vasiliy
Based on several important examples we show great potencial of GPU in codes on the graph optimization (probabalistical graphical model). We consider error-floor estimation weighed of Trapping Sets, Matrix multiplication operation (which important for fast sieving of LDPC using spectral graph analisys Tanner bound and cycle enumerating using lollipop cycles count in LDPC) and Monte-Carlo simulation of LDPC and Turbo Codes.
In this presentation we consider several main methods for contruction regular QC-LDPC codes using algebraic approach. Consider existance of non broken by circulant permutation matrix cycles (short balanced cycles). Using Vontobel approach illustrate way to estimate girth bound and it influence on error-floor properties of QC-LDPC codes
Enumerating cycles in bipartite graph using matrix approachUsatyuk Vasiliy
Describe method to enumerate shortest cyclesin bipartite graph. Consider example and provide implementation of this method (https://yadi.sk/d/nMza892Y3PVR3U). Show way to improve under structured graphs
Cancer cell metabolism: special Reference to Lactate PathwayAADYARAJPANDEY1
Normal Cell Metabolism:
Cellular respiration describes the series of steps that cells use to break down sugar and other chemicals to get the energy we need to function.
Energy is stored in the bonds of glucose and when glucose is broken down, much of that energy is released.
Cell utilize energy in the form of ATP.
The first step of respiration is called glycolysis. In a series of steps, glycolysis breaks glucose into two smaller molecules - a chemical called pyruvate. A small amount of ATP is formed during this process.
Most healthy cells continue the breakdown in a second process, called the Kreb's cycle. The Kreb's cycle allows cells to “burn” the pyruvates made in glycolysis to get more ATP.
The last step in the breakdown of glucose is called oxidative phosphorylation (Ox-Phos).
It takes place in specialized cell structures called mitochondria. This process produces a large amount of ATP. Importantly, cells need oxygen to complete oxidative phosphorylation.
If a cell completes only glycolysis, only 2 molecules of ATP are made per glucose. However, if the cell completes the entire respiration process (glycolysis - Kreb's - oxidative phosphorylation), about 36 molecules of ATP are created, giving it much more energy to use.
IN CANCER CELL:
Unlike healthy cells that "burn" the entire molecule of sugar to capture a large amount of energy as ATP, cancer cells are wasteful.
Cancer cells only partially break down sugar molecules. They overuse the first step of respiration, glycolysis. They frequently do not complete the second step, oxidative phosphorylation.
This results in only 2 molecules of ATP per each glucose molecule instead of the 36 or so ATPs healthy cells gain. As a result, cancer cells need to use a lot more sugar molecules to get enough energy to survive.
Unlike healthy cells that "burn" the entire molecule of sugar to capture a large amount of energy as ATP, cancer cells are wasteful.
Cancer cells only partially break down sugar molecules. They overuse the first step of respiration, glycolysis. They frequently do not complete the second step, oxidative phosphorylation.
This results in only 2 molecules of ATP per each glucose molecule instead of the 36 or so ATPs healthy cells gain. As a result, cancer cells need to use a lot more sugar molecules to get enough energy to survive.
introduction to WARBERG PHENOMENA:
WARBURG EFFECT Usually, cancer cells are highly glycolytic (glucose addiction) and take up more glucose than do normal cells from outside.
Otto Heinrich Warburg (; 8 October 1883 – 1 August 1970) In 1931 was awarded the Nobel Prize in Physiology for his "discovery of the nature and mode of action of the respiratory enzyme.
WARNBURG EFFECT : cancer cells under aerobic (well-oxygenated) conditions to metabolize glucose to lactate (aerobic glycolysis) is known as the Warburg effect. Warburg made the observation that tumor slices consume glucose and secrete lactate at a higher rate than normal tissues.
Professional air quality monitoring systems provide immediate, on-site data for analysis, compliance, and decision-making.
Monitor common gases, weather parameters, particulates.
This presentation explores a brief idea about the structural and functional attributes of nucleotides, the structure and function of genetic materials along with the impact of UV rays and pH upon them.
Richard's aventures in two entangled wonderlandsRichard Gill
Since the loophole-free Bell experiments of 2020 and the Nobel prizes in physics of 2022, critics of Bell's work have retreated to the fortress of super-determinism. Now, super-determinism is a derogatory word - it just means "determinism". Palmer, Hance and Hossenfelder argue that quantum mechanics and determinism are not incompatible, using a sophisticated mathematical construction based on a subtle thinning of allowed states and measurements in quantum mechanics, such that what is left appears to make Bell's argument fail, without altering the empirical predictions of quantum mechanics. I think however that it is a smoke screen, and the slogan "lost in math" comes to my mind. I will discuss some other recent disproofs of Bell's theorem using the language of causality based on causal graphs. Causal thinking is also central to law and justice. I will mention surprising connections to my work on serial killer nurse cases, in particular the Dutch case of Lucia de Berk and the current UK case of Lucy Letby.
Introduction:
RNA interference (RNAi) or Post-Transcriptional Gene Silencing (PTGS) is an important biological process for modulating eukaryotic gene expression.
It is highly conserved process of posttranscriptional gene silencing by which double stranded RNA (dsRNA) causes sequence-specific degradation of mRNA sequences.
dsRNA-induced gene silencing (RNAi) is reported in a wide range of eukaryotes ranging from worms, insects, mammals and plants.
This process mediates resistance to both endogenous parasitic and exogenous pathogenic nucleic acids, and regulates the expression of protein-coding genes.
What are small ncRNAs?
micro RNA (miRNA)
short interfering RNA (siRNA)
Properties of small non-coding RNA:
Involved in silencing mRNA transcripts.
Called “small” because they are usually only about 21-24 nucleotides long.
Synthesized by first cutting up longer precursor sequences (like the 61nt one that Lee discovered).
Silence an mRNA by base pairing with some sequence on the mRNA.
Discovery of siRNA?
The first small RNA:
In 1993 Rosalind Lee (Victor Ambros lab) was studying a non- coding gene in C. elegans, lin-4, that was involved in silencing of another gene, lin-14, at the appropriate time in the
development of the worm C. elegans.
Two small transcripts of lin-4 (22nt and 61nt) were found to be complementary to a sequence in the 3' UTR of lin-14.
Because lin-4 encoded no protein, she deduced that it must be these transcripts that are causing the silencing by RNA-RNA interactions.
Types of RNAi ( non coding RNA)
MiRNA
Length (23-25 nt)
Trans acting
Binds with target MRNA in mismatch
Translation inhibition
Si RNA
Length 21 nt.
Cis acting
Bind with target Mrna in perfect complementary sequence
Piwi-RNA
Length ; 25 to 36 nt.
Expressed in Germ Cells
Regulates trnasposomes activity
MECHANISM OF RNAI:
First the double-stranded RNA teams up with a protein complex named Dicer, which cuts the long RNA into short pieces.
Then another protein complex called RISC (RNA-induced silencing complex) discards one of the two RNA strands.
The RISC-docked, single-stranded RNA then pairs with the homologous mRNA and destroys it.
THE RISC COMPLEX:
RISC is large(>500kD) RNA multi- protein Binding complex which triggers MRNA degradation in response to MRNA
Unwinding of double stranded Si RNA by ATP independent Helicase
Active component of RISC is Ago proteins( ENDONUCLEASE) which cleave target MRNA.
DICER: endonuclease (RNase Family III)
Argonaute: Central Component of the RNA-Induced Silencing Complex (RISC)
One strand of the dsRNA produced by Dicer is retained in the RISC complex in association with Argonaute
ARGONAUTE PROTEIN :
1.PAZ(PIWI/Argonaute/ Zwille)- Recognition of target MRNA
2.PIWI (p-element induced wimpy Testis)- breaks Phosphodiester bond of mRNA.)RNAse H activity.
MiRNA:
The Double-stranded RNAs are naturally produced in eukaryotic cells during development, and they have a key role in regulating gene expression .
1. Generalization of Floor Lifting for QC-LDPC Codes:
Theoretical Properties and Applications
Vasiliy Usatyuk, Sergey Egorov
South-West State University,
Kursk, L@Lcrypto.com
Ilya Vorobyev, Nikita Polyanskii
Institute for Information Transmission Problems,
Moscow, vorobyev.i.v@yandex.ru
Kazan, Russia
September 14 - 17, 2018
German Svistunov
Omsk State Technical University, Omsk, Russia
G.V.Svistunov@gmail
2. 1
100111
101001
010011
H
1v 2v 3v 4v 5v 6v
1c
2c
3c
Low density parity-check codes (LDPC-codes), – block
linear code of dimension k and code words 𝑥 size n, defined
by parity-check matrix H with size (n-k)·n, which contain low
density-parity check.
Parity-check matrix of size (n-k)·n contain about n checks.
1 2 5
1 4 6
1 2 3 6
0
0
0
x x x
x x x
x x x x
Every row of parity-check matrix H define equation:
Low Density Parity-Check Codes
Gallager R.G., “Low-density parity-check codes”, IRE Trans. Inform. Theory, vol. IT-8, pp. 21-28,
Jan. 1962.
0T
Hx (2)GF
3. 2
Tanner Graph– equivalent bipartite graph for the parity check matrix H
1v 3v2v 4v 5v 6v
1c 3c2cChecks (row)
VN (columns)
Tanner Graph. Cycles and Girth
Tanner R.M., “A recursive approach to low complexity codes”, IEEE Trans. Inform. Theory, IT-27,
pp. 533-547, September 1981.
100111
101001
010011
H
1v 2v 3v 4v 5v 6v
1c
2c
3c
4. 3
Tanner Graph– equivalent bipartite graph for the parity check matrix H
1v 3v2v 4v 5v 6v
1c 3c2c
Cycle - closed simple way in Tanner-graph.
Example of cycle 4:c2 → v1 → c3 → v6 → c2
Girth – shortest cycles in Tanner-graph.
Checks (row)
VN (columns)
Tanner Graph. Cycles and Girth
Tanner R.M., “A recursive approach to low complexity codes”, IEEE Trans. Inform. Theory, IT-27,
pp. 533-547, September 1981.
5. 4
Quasi-Cyclic LDPC(QC-LDPC codes)- LDPC-codes which parity-
check matrix defined by structured block submatrix –
Circulant Permutation matrix.
Applied QC-LDPC codes allow to simplify analysis of code and
graph properties, increase throughput (parallelism inside
circulant), decrease complexity of hardware implementation
based on barrel shifter.
100010
010001
010110
101001
H
1v 2v 3v 4v 5v 6v
1c
2c
3c
0 1 1
0 1 0
0 1 1
0 1 0
QC
I I I
H
I I I
4c
Quasi-Cyclic LDPC codes
( ) 2 2:Circulant PermutationMatrix CPM of size 0 1 11 0 0 1 0 0
, ,
0 1 1 0 0 0
I I I
R. M. Tanner, D. Sridhara, T. Fuja, ”A class of group structured LDPC codes”, Proc. ICSTA 2001,
Ambleside, England, 2001
6. 5
1
1
,
0
( ) 0 mod ( )k k
i
j j k
k
l Z
QC-LDPC codes contain cycle of size if (circulant permutation matrix) shifts satisfy equationi2
Cycles at QC-LDPC Codes
Fossorier M.P.C., “Quasi-cyclic low-density parity-check codes from circulant permutation
matrices”, IEEE Trans. Inf. Theory, vol. 50, no. 8, pp. 1788–1793, 2004.
For example for cycle 4, 𝑥 𝑖𝑠 𝑎 𝑐𝑖𝑟𝑐𝑢𝑙𝑎𝑛𝑡 𝑠ℎ𝑖𝑓𝑡 𝑖𝑛 𝑚𝑎𝑡𝑟𝑖𝑥:
0 0 1
0 0 1
, 2 2QC
I I I
H where I CPM of size
I I I
1 0 1 0 0 1
0 1 0 1 1 0
1 0 1 0 0 1
0 1 0 1 1 0
H
(H )QCAuth size I
If you found cycles multiplied it to Authomorphism of Tanner graph, in our case Auth=2
7. 6
1
1
,
0
( ) 0 mod ( )k k
i
j j k
k
l Z
QC-LDPC codes contain cycle of size if (circulant permutation matrix) shifts satisfy equationi2
Cycles at QC-LDPC Codes
Fossorier M.P.C., “Quasi-cyclic low-density parity-check codes from circulant permutation
matrices”, IEEE Trans. Inf. Theory, vol. 50, no. 8, pp. 1788–1793, 2004.
For example for cycle 4:
11. 10
Proposed
Floor Scale Modular Lifting – Flow Chart
upperupper
upper
current
current zrHE
z
z
HE mod*
It further step to get flexible in broking VN
and CN ring-generalization of floor lifting.
Only ‘r’ (scale) optimization procedure is necessary for particular code
15. 14
Code A is the QC-LDPC with base graph 2 (BG2) from 5G EMBB standard R1-1711982 Nokia
WF on LDPC parity check matrices 3GPP RAN1-NR2 Qingdao, China, 27th – 30th June 2017
Code B is BG2 lifted using proposed floor scale modular lifting
16. Summary
1. Proved probabilistic statement concerning a theoretical
improvement of proposed lifting method with respect to the
number of small cycles.
2. This approach improve cycle properties of QC-LDPC codes,
decrease number of harmful Trapping sets and show from 0.1
to 0.3 dB gain compare to EMBB lifting.
15
19. 96,48,24:
22
*
2496
*
circulant
ZZZZ
Floor lifting (heuristics approach nobody know why it work)
Floor incomprehensible operation under multiplicative group
upper
upper
current
current HE
z
z
HE
96,92,...,34,32,28,24:circulant
We broke rings of CN and VN at some place and it work
Seho Myung; Kyeongcheol Yang; Youngkyun Kim, "Lifting methods for quasi-cyclic LDPC codes," in Communications Letters, IEEE , vol.10,
no.6, pp.489-491
Aamod Khandekar, Thomas Richardson Qualcomm patent, US 8,578,249 B2
Floor lifting
22. Lifted protograph minimum distance
upper bound estimation
Code family upper bound bigger or equal lifted
protograph upper bound
Performance of codes derived with
the same protograph
Lifting is critical for code
performance
