This document summarizes the author's PhD work on analyzing the reliability of nano-scale circuits. It discusses how threshold voltage variations, process variations, and negative bias temperature instability aging affect circuit reliability. Analytical and simulation-based techniques are used to model these effects and compute failure probabilities. The author's future work will apply these techniques to evaluate reliability for logic paths in combinational and memory circuits fabricated with emerging technologies like FinFETs.

1. Reliability of Nano-scale Circuits: A Partial Journey of my PhD
Usman Khalid
Richard Newton Young Fellow
Email: khalidu@diet.uniroma1.it Sapienza University of Rome, Italy
Abstract
Joint Impact of NBTI Aging with Process Variations
Related Work and Background Definitions
Influence of Threshold Variations on Reliability
Future Work
In future PhD work, the above schemes will be applied in order to compute the Reliability for a generic logic path for combinational
and memory elements. As well as the work will be extended from CMOS to emerging technologies such as FinFETs and Fully
Depleted (FD)-SOI technologies.
Threshold variations and process variations in conjunction to voltage noise can be responsible of logic
errors in digital circuits. The variations in process-induced parameters affect the probability of noise-
induced faulty operation of digital logic cells. Furthermore, process variation together with NBTI aging
have a huge impact on noise margins of memory elements such as flip-flops. This poster demonstrates the
novel techniques to model threshold variations, process variations as well as NBTI aging phenomenon
with verification Monte Carlo simulations scheme in terms of failure probability or reliability
computation.
Fig. 1. Left: Two inverter cells Right: Logic threshold voltages.
Grey area denotes undefined VoutA logic value.
Table : Failure probability for selected cases using Safe Operation
Region approach for 𝑽 𝑰𝑵 high
Table : Failure Probability Comparison b/w Safe Operation Region Vs
Spice MC Simulations for both 𝑽 𝑰𝑵 high and low for σVin=0.30
INV A INV B
Vout A Vout B
VIL VIH Vout A
Vout B
Fig. 3: Left: Variation between VTHP vs. Vin;
Right: High VIN; Bottom: Low VIN
σ Tox σ Ndep σ Leff σ Weff
σ
Vin=0.15
σ
Vin=0.20
σ
Vin=0.25
σ
Vin=0.30
15·10-12 20·1016 15·10-10 25·10-10 1.170·10-2 9.950·10-2 3.107·10-2 6.032·10-2
15·10-12 20·1016 25·10-10 30·10-10 1.170·10-2 9.960·10-2 3.101·10-2 6.033·10-2
20·10-12 25·1016 20·10-10 15·10-10 1.470·10-2 1.102·10-2 3.148·10-2 6.125·10-2
20·10-12 30·1016 30·10-10 25·10-10 1.460·10-2 1.100·10-2 3.146·10-2 6.121·10-2
25·10-12 15·1016 25·10-10 30·10-10 1.630·10-2 1.165·10-2 3.307·10-2 6.224·10-2
25·10-12 25·1016 25·10-10 25·10-10 1.640·10-2 1.165·10-2 3.308·10-2 6.221·10-2
30·10-12 25·1016 20·10-10 15·10-10 2.010·10-2 1.269·10-2 3.378·10-2 6.246·102
30·10-12 30·1016 30·10-10 30·10-10 2.000·10-2 1.267·10-2 3.375·10-2 6.241·102
Process Parameters Safe Operation
Region
Approach
SPICE Monte
Carlo
Simulations
HighVin
σ Tox σ Ndep σ Leff σ Weff
σVin=0.30 σ Vin=0.30
15·10-12 15·1016 20·10-10 15·10-10 0.060300 0.066700
20·10-12 15·1016 20·10-10 20·10-10 0.061270 0.068260
30·10-12 20·1016 20·10-10 20·10-10 0.062500 0.073530
25·10-12 25·1016 25·10-10 25·10-10 0.062210 0.074480
LowVin
15·10-12 15·1017 20·10-10 15·10-10 0.061790 0.062390
20·10-12 15·1017 20·10-10 20·10-10 0.062000 0.064003
30·10-12 20·1017 20·10-10 20·10-10 0.063920 0.064161
25·10-12 25·1017 25·10-10 25·10-10 0.063440 0.066714
We introduce NBTI degradation and process parameters variations, both
VIL and VIH will be actually functions of such effects. We can formally
express the dependence of VIL and VIH on oxide thickness (Tox), channel
width (W) and length (L) as a pair of functions 𝑉𝐼𝐿 = 𝑉𝐼𝐿(𝑡 𝑜𝑥, 𝐿, 𝑊, 𝑌),
𝑉𝐼𝐻 = 𝑉𝐼𝐻(𝑡 𝑜𝑥, 𝐿, 𝑊, 𝑌).
0
0,2
0,4
0,6
0,8
1
0 3E-11 6E-11 9E-11
Vout
Time (ps)
Input HL
0
0,2
0,4
0,6
0,8
1
0 4E-11 8E-11 1,2E-10
Vout
Time (ps)
Input LH
Vin
Vtp
Vtn
Vout
Vdd
Fig. : First: Simulated
circuit; Middle: Output
voltages for different VTHP
variations when Input HL.
Last: Output voltages for
different VTHP variations
when Input LH
Threshold Variations
Reliability of Nano-scale
Circuits
Digital-Logic Level
Bayesian
Netwroks
(BN)
Probablistic
Transfer
Matrix (PTM)
Probabilistic
Gate Model
(PGM)
Booelan
Difference
Error
Calculator
Transistor-Level
Stochastic
Estimation
Scheme
Gate Reliability
EDA Tool
(GREDA)
This Work
Analytical, Semi-Analytical, Monte Carlo Sim.
Failure Probaility Techniques
VIN, VTHN, VTHP VIN, Tox, NDEP, Leff, Weff
This Work
Techniques of Estimation Reliability
Process Variations NBTI Aging
NBTI Aging, VIN, Tox, NDEP, Leff,
Weff
This Work This Work
 ANALYTICAL Approach
Mathematically, the probability of incorrect output is the probability that the three random variables 𝑉𝐼𝑁, 𝑉𝑇𝑁, 𝑉𝑇𝑃 fall outside the
safe operation region, and can be computed analytically as a 3-D integral of the associated probability density function
𝑓𝑣 𝐼𝑁,𝑣 𝑇𝑁,𝑣 𝑇𝑃
∙ .
We discretize the integral computation by defining 𝑉𝐼𝑁 = 𝑖 ∙ 𝛿𝑣𝑖𝑛, 𝑉𝑇𝑁 = 𝑗 ∙ 𝛿𝑡𝑛, 𝑉𝑇𝑃 = 𝑘 ∙ 𝛿𝑣𝑡𝑝 so that we obtain
𝑃𝑒𝑟𝑟𝑜𝑟 =
𝑖=−∞
+∞
𝑝 𝑣𝑖𝑛 𝑖
𝑗=−∞
+∞
𝑝 𝑣𝑡𝑛 𝑗
𝑘=𝐻 𝑖,𝑗
+∞
𝑝 𝑣𝑡𝑝 𝑘
where 𝑝 𝑣𝑖𝑛 = 𝑖∙𝛿𝑣𝑖𝑛
𝑖+1 ∙𝛿𝑣𝑖𝑛
𝑓𝑣 𝐼𝑁
𝑉𝐼𝑁 𝑑𝑉𝐼𝑁 and similarly for 𝑝𝑗, 𝑝 𝑘, and 𝐻 𝑖, 𝑗 = 𝐺 𝑖 ∙ 𝛿𝑣𝑖𝑛 , 𝑗 ∙ 𝛿𝑡𝑛 / 𝛿𝑣𝑡𝑝.
In our analysis, we assume normal distributions and independence of VTN and VTP
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0,16
SPICE MC analytical Results shows that in all cases the
relative difference of the
analytical calculation with
respect to SPICE MC is below
5%. The SPICE MC run time
was >100 hours per each case.
Semi-Analytical “Safe Operation Region”
1E-50
1E-45
1E-40
1E-35
1E-30
1E-25
1E-20
1E-15
1E-10
1E-05
1
0 5 10 15 20 25 30 35 40 45 50
0.02
0.03
0.04
0.05
Fig: Error probability results. Omitted values are below 10-50
Technology: 45 nm 32 nm 22 nm 16 nm
σVTN 0.0237 0.0341 0.0516 0.0715
σVTP 0.0167 0.0220 0.0346 0.0478
Table – Technology data
We performed the analysis of the error probability
𝜹 = (𝒕 𝒐𝒙 𝑵 𝑨)/ 𝑾 𝒆𝒇𝒇 𝑳 𝒆𝒇𝒇
Technology 45 nm 32 nm 22 nm 16 nm
VDD 1.0 0.9 0.8 0.7
VIH 0.60 0.57 0.54 0.48
VIL 0.38 0.33 0.28 0.22
Table – Logic thresholds values
-0.1
0.1
0.3
0.5
-0.5
0
0.5
1
1.5
-1
0
1
Vthn
Vin
(Low Value)
Vthp
Safe Operation
Region
0.5
0.7
0.9
1.11.1
-0.5
0
0.5
1
1.5
-2
-1
0
1
2
Vthn
Vin
(High Value)
Vthp
Safe Operation
Region
0.00E+00
5.00E-04
1.00E-03
1.50E-03
2.00E-03
2.50E-03
3.00E-03
s Tox
P{failure}
(a) (b) (c)
Fig: (a) Probability of Failure versus Vin standard deviation for different standard deviation of Tox. (b): Detail of the dependency of
Probability of failure from Tox for σ Vin=0.25 (c) Trendline of Tox behavior with extended Standard deviations
𝑃𝑒𝑟𝑟𝑜𝑟 =
−∞
+∞
−∞
+∞
𝐺 𝑉 𝐼𝑁,𝑉 𝑇𝑁
+∞
𝑓𝑣 𝐼𝑁,𝑣 𝑇𝑁,𝑣 𝑇𝑃
𝑉𝐼𝑁, 𝑉𝑇𝑁, 𝑉𝑇𝑃 𝑑𝑉𝑇𝑃 𝑑𝑉𝐼𝑁 𝑑𝑉𝑇𝑁.
Fig: 2D and 3D diagram of Safe operation region for VTN, VTP and VIN variation for High and Low VIN
D
CKN
CK CKN
CK
Q
Inv 1
Inv 2
TG 1 TG 2
Inv 3
Inv 5_load
Inv 4
Fig. Transmission Gate based static flip-flop
Inv 1CK
CKN
CKN
CK
Inv 3CKN
CK
CK
CKN
Inv 5_load
Q
D
VDD
VDD
VDD
VDD
CKN
CK
VDD
CK
CKN
VDD
CK
CKN
TG 1
CKN
CK
TG 2
Inv 4Inv 2
Fig. Bootstrap C2MOS based pseudo-static flip-flop
0 years 10 years
Q edge tCKtoQ tSetup MIN tCKtoQ tSetup MIN
flip flop 1
0-to-1 11.57 ps 09 ps 13.51 ps 10 ps
1-to-0 16.59 ps 11 ps 20.26 ps 16 ps
flip flop 2
0-to-1 04.20 ps 12 ps 05.78 ps 16 ps
1-to-0 06.35 ps 15 ps 07.40 ps 19 ps
Table – Characterized propagation delay and minimum setup
time for different types of flip flops at different aging times
VDD
100 p 100 p + trf
0 V
V
VIL
Time (s)
clkQVD
VDD
100 p 100 p + trf
0 V
V
Time (s)
clkQ
VD
VDD
100 p 100 p + trf
0 V
V
Time (s)
clk
Q
VD
(a)
(b)
(c)
Fig. 8. Timing scheme for the selection of: Left: VIL value, Right: VIH value
VDD
100 p 100 p + trf
0 V
V
VIH
Time (s)
clkQVD
VDD
100 p 100 p + trf
0 V
V
Time (s)
clkQ
VD
VDD
100 p 100 p + trf
0 V
V
Time (s)
clk
Q
VD
(a)
(b)
(c)
Setup
time
margin
Years Nominal MC Mean MC Sigma
long
VIL
0 0.398 0.402 0.01366
2 0.347 0.350 0.01102
5 0.336 0.338 0.01051
7 0.331 0.333 0.01033
10 0.326 0.328 0.01014
VIH
0 0.679 0.677 0.01947
2 0.746 0.743 0.02030
5 0.761 0.757 0.02024
8 0.767 0.763 0.02011
10 0.774 0.770 0.02001
short
VIL
0 0.148 0.151 0.02503
2 0.060 0.063 0.02661
5 0.038 0.042 0.02675
7 0.029 0.032 0.02672
10 0.018 0.022 0.02658
VIH
0 0.868 0.866 0.02873
2 0.958 0.955 0.03163
5 0.980 0.977 0.03227
8 0.989 0.987 0.03258
10 1.000 0.998 0.03296
Table . Noise Margin Results for flip flop 1.
Nominal Approach vs SPICE Monte Carlo
0,310
0,320
0,330
0,340
0,350
0,360
0,370
0 5 10 15
NoiseMargins
Years
VIL (MC Mean)
VIL (Nominal)
Poly. (VIL (MC Mean))
Poly. (VIL (Nominal))
0,72
0,73
0,74
0,75
0,76
0,77
0,78
0,79
0,8
0 5 10 15
NoiseMargins
Years
VIH (Nominal)
VIH (MC Mean)
Poly. (VIH (Nominal))
Poly. (VIH (MC Mean))
Fig: Error probability results. Omitted values are below 10-50
Logic
gate
Logic
gate
Logic
gate
Logic
gate FF
The probability that the register samples a wrong value
due to the voltage drop/rise is equal to the probability
that the voltage noise margins of the flip-flops in the
register is smaller than the voltage drop/rise 𝑣, i.e.
formally:
Pr 𝑉𝐼𝐿 < 𝑣 = −∞
𝑣
𝒩 𝑥, 𝜇 𝑉𝐼𝐿, 𝜎 𝑉𝐼𝐿 𝑑𝑥,
for logic ‘0’ at register input, with positive voltage rise
v;
Pr 𝑉𝐼𝐻 > 𝑉 𝐷𝐷 + 𝑣 = 𝑉𝐷𝐷+𝑣
+∞
𝒩 𝑥, 𝜇 𝑉𝐼𝐻, 𝜎 𝑉𝐼𝐻 𝑑𝑥,
for logic ‘1’ at register input, with negative voltage
drop 𝑣;
where 𝒩 𝑥, 𝜇, 𝜎 is the normal probability density
function.
Fig: A generic path in digital architecture design.
0 years 10 years
drop/rie
[V]
+0.05 +0.1 -0.05 -0.1 +0.05 +0.1 -0.05 -0.1
FF A 4.4e-05 2.7e-02 1.7e-03 1.2e-01 8.9e-01 9.9e-01 9.4e-01 9.9e-01
FF B 4.9e-05 1.7e-02 8.8e-05 2.4e-02 7.7e-01 9.9e-01 8.4e-01 9.9e-01
FF C 2.3e-04 5.7e-02 4.9e-05 1.7e-02 8.8e-01 9.9e-01 7.3e-01 9.8e-01
FF D 3.2e-15 1.2e-10 6.3e-15 5.4e-10 1.4e-01 3.6e-01 5.6e-01 8.0e-01
FF E 1.0e-02 2.9e-01 1.1e-16 6.4e-11 1.7e-02 3.3e-01 4.6e-01 8.7e-01
FF F 4.6e-07 9.0e-05 2.2e-13 1.7e-08 6.5e-01 8.3e-01 7.1e-01 9.4e-01
FF G 5.1e-07 4.0e-05 8.2e-12 2.1e-08 7.0e-01 8.9e-01 2.3e-01 4.7e-01
Table – Failure probability of registers for different types of flip flops
at different aging times (short setup time design case)