This document describes a patent application for an epitaxial group-III-nitride buffer layer structure on a heterosubstrate. The buffer layer structure includes at least one stress-management layer sequence with an interlayer structure between a first and second group-III-nitride layer. The interlayer structure has a larger bandgap than the adjacent layers. A p-type dopant concentration profile drops by at least a factor of two from the interlayer structure, with a starting concentration of at least 1x1018 cm-3, to the first and second group-III-nitride layers. This concentration profile helps manage stress in the buffer layer and avoids parasitic conductive channels, providing an improved buffer layer structure.
Boridign kinetics fe2 b layers formed on aisi 1045 steeluaeh
Boriding is a thermochemical treatment in which boron atoms are diffused into the surface of a workpiece and form borides with the base metal. Apart from constructional materials, which meet these high demands, processes have been developed which have a positive effect on the tribological applications including abrasive, adhesive, fatigue and corrosion wear of the component surface.
Growth kinetics and mechanical properties of fe2 b layers formed on aisi d2 s...uaeh
Boriding is our favourite method to harden steels. That is also why we have developed a special boriding treatment that works even better than regular boriding, called BoroCoat®.
Boriding is a thermochemical heat treatment that diffuses boron into the surface of a workpiece. The boride layer that is formed on top is extremely wear resistant and protects the workpiece from chemical attacks as well as abrasive wear and cold welding.
Boron can be applied as a powder, as a paste and as granules, making possible the treatment of almost any type of workpiece, no matter their design. Boriding is extremely effective when it comes to corrosion resistance and can be applied to workpieces in mechanical engineering, for valves and for power tools.
Boridign kinetics fe2 b layers formed on aisi 1045 steeluaeh
Boriding is a thermochemical treatment in which boron atoms are diffused into the surface of a workpiece and form borides with the base metal. Apart from constructional materials, which meet these high demands, processes have been developed which have a positive effect on the tribological applications including abrasive, adhesive, fatigue and corrosion wear of the component surface.
Growth kinetics and mechanical properties of fe2 b layers formed on aisi d2 s...uaeh
Boriding is our favourite method to harden steels. That is also why we have developed a special boriding treatment that works even better than regular boriding, called BoroCoat®.
Boriding is a thermochemical heat treatment that diffuses boron into the surface of a workpiece. The boride layer that is formed on top is extremely wear resistant and protects the workpiece from chemical attacks as well as abrasive wear and cold welding.
Boron can be applied as a powder, as a paste and as granules, making possible the treatment of almost any type of workpiece, no matter their design. Boriding is extremely effective when it comes to corrosion resistance and can be applied to workpieces in mechanical engineering, for valves and for power tools.
The Humidity Dependence of Pentacene Organic Metal- Oxide-Semiconductor Field...TELKOMNIKA JOURNAL
Metal-oxide-semiconductor field-effect transistors (MOSFET) were fabricated using organic
semiconductor pentacene. The humidity dependence of drain current gate voltage (ID-VG) characteristic
and drain current drain voltage characteristic (ID-VD) will be explained. Firstly, the thermal oxidation method
was used to grow SiO2 gate insulator with thickness of 11 nm. Secondly, the thermal evaporation method
was used to form Au source and drain electrodes with thickness of 28 nm. The channel width and length of
the transistors were 500 and 200 respectively. By the same method, organic semiconductor
material pentacene was deposited with thickness of 50 nm at vacuum of 7.8x10-6 Torr. The hole mobility
decreased from 0.035 cm2/(Vs) to 0.006 cm2/(Vs), while the threshold voltage increased from 0.5 V to 2.5
V and gate leakage current also increased from 5.8x10-10 A to 3.3x10-9 A when the relative humidity
increased from 20% to 70%.
Modeling of Dirac voltage for highly p-doped graphene field-effect transistor...journalBEEI
In this paper, the modeling approach of Dirac voltage extraction of highly p-doped graphene field-effect transistor (GFET) measured at atmospheric pressure is presented. The difference of measurement results between atmospheric and vacuum pressures was analyzed. This work was started with actual wafer-scale fabrication of GFET with the purposes of getting functional device and good contact of metal/graphene interface. The output and transfer characteristic curves were measured accordingly to support on GFET functionality and suitability of presented wafer fabrication flow. The Dirac voltage was derived based on the measured output characteristic curve using ambipolar virtual source model parameter extraction methodology. The circuit-level simulation using frequency doubler circuit shows the importance of accurate Dirac voltage value to the device practicality towards design integration.
A Study On Double Gate Field Effect Transistor For Area And Cost Efficiencypaperpublications3
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal. Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used to successfully manufacture the new FET structure.
The Humidity Dependence of Pentacene Organic Metal- Oxide-Semiconductor Field...TELKOMNIKA JOURNAL
Metal-oxide-semiconductor field-effect transistors (MOSFET) were fabricated using organic
semiconductor pentacene. The humidity dependence of drain current gate voltage (ID-VG) characteristic
and drain current drain voltage characteristic (ID-VD) will be explained. Firstly, the thermal oxidation method
was used to grow SiO2 gate insulator with thickness of 11 nm. Secondly, the thermal evaporation method
was used to form Au source and drain electrodes with thickness of 28 nm. The channel width and length of
the transistors were 500 and 200 respectively. By the same method, organic semiconductor
material pentacene was deposited with thickness of 50 nm at vacuum of 7.8x10-6 Torr. The hole mobility
decreased from 0.035 cm2/(Vs) to 0.006 cm2/(Vs), while the threshold voltage increased from 0.5 V to 2.5
V and gate leakage current also increased from 5.8x10-10 A to 3.3x10-9 A when the relative humidity
increased from 20% to 70%.
Modeling of Dirac voltage for highly p-doped graphene field-effect transistor...journalBEEI
In this paper, the modeling approach of Dirac voltage extraction of highly p-doped graphene field-effect transistor (GFET) measured at atmospheric pressure is presented. The difference of measurement results between atmospheric and vacuum pressures was analyzed. This work was started with actual wafer-scale fabrication of GFET with the purposes of getting functional device and good contact of metal/graphene interface. The output and transfer characteristic curves were measured accordingly to support on GFET functionality and suitability of presented wafer fabrication flow. The Dirac voltage was derived based on the measured output characteristic curve using ambipolar virtual source model parameter extraction methodology. The circuit-level simulation using frequency doubler circuit shows the importance of accurate Dirac voltage value to the device practicality towards design integration.
A Study On Double Gate Field Effect Transistor For Area And Cost Efficiencypaperpublications3
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal. Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used to successfully manufacture the new FET structure.
Analysis Of 3C-Sic Double Implanted MOSFET With Gaussian Profile Doping In Th...IJRES Journal
The present work aims at the design of 3C-SiC Double Implanted Metal Oxide Semiconductor Field Effect Transistor (DIMOSFET) with Gaussian doping profile in drift region for high breakdown voltages. By varying the device height ‘h’, function constant m and peak concentration 𝑁0, analysis has been done for an optimum profile for high breakdown voltage. With Gaussian profile peak concentration 𝑁0 = 1016 𝑐𝑚−3 at drain end and m as 1.496 ×10−2cm, highest breakdown voltage of 6.84kV has been estimated with device height of 200μm.
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However,
as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However,
as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
Multiple gate field effect transistors foreSAT Journals
Abstract
This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of Multigate FETs; and their advantages/disadvantages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspective on the future of the FinFET technology is presented. Keywords: CMOS scaling, Double gate MOSFET, FinFET, Multiple gate FET, Multigate FET
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Similar to Buffer doping in GaN to reduce parasitic channels (20)
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
TOP 10 B TECH COLLEGES IN JAIPUR 2024.pptxnikitacareer3
Looking for the best engineering colleges in Jaipur for 2024?
Check out our list of the top 10 B.Tech colleges to help you make the right choice for your future career!
1) MNIT
2) MANIPAL UNIV
3) LNMIIT
4) NIMS UNIV
5) JECRC
6) VIVEKANANDA GLOBAL UNIV
7) BIT JAIPUR
8) APEX UNIV
9) AMITY UNIV.
10) JNU
TO KNOW MORE ABOUT COLLEGES, FEES AND PLACEMENT, WATCH THE FULL VIDEO GIVEN BELOW ON "TOP 10 B TECH COLLEGES IN JAIPUR"
https://www.youtube.com/watch?v=vSNje0MBh7g
VISIT CAREER MANTRA PORTAL TO KNOW MORE ABOUT COLLEGES/UNIVERSITITES in Jaipur:
https://careermantra.net/colleges/3378/Jaipur/b-tech
Get all the information you need to plan your next steps in your medical career with Career Mantra!
https://careermantra.net/
Online aptitude test management system project report.pdfKamal Acharya
The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
Every time when lecturers/professors need to conduct examinations they have to sit down think about the questions and then create a whole new set of questions for each and every exam. In some cases the professor may want to give an open book online exam that is the student can take the exam any time anywhere, but the student might have to answer the questions in a limited time period. The professor may want to change the sequence of questions for every student. The problem that a student has is whenever a date for the exam is declared the student has to take it and there is no way he can take it at some other time. This project will create an interface for the examiner to create and store questions in a repository. It will also create an interface for the student to take examinations at his convenience and the questions and/or exams may be timed. Thereby creating an application which can be used by examiners and examinee’s simultaneously.
Examination System is very useful for Teachers/Professors. As in the teaching profession, you are responsible for writing question papers. In the conventional method, you write the question paper on paper, keep question papers separate from answers and all this information you have to keep in a locker to avoid unauthorized access. Using the Examination System you can create a question paper and everything will be written to a single exam file in encrypted format. You can set the General and Administrator password to avoid unauthorized access to your question paper. Every time you start the examination, the program shuffles all the questions and selects them randomly from the database, which reduces the chances of memorizing the questions.
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NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
1. Printed by Jouve, 75001 PARIS (FR)
(19)
EP 2 767 620 A1
TEPZZ 7676 ZA_T
(11) EP 2 767 620 A1
(12) EUROPEAN PATENT APPLICATION
(43) Date of publication:
20.08.2014 Bulletin 2014/34
(21) Application number: 13155540.1
(22) Date of filing: 15.02.2013
(51) Int Cl.:
C30B 25/18 (2006.01) C30B 29/40 (2006.01)
H01L 29/267 (2006.01) H01L 21/02 (2006.01)
(84) Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB
GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO
PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME
(71) Applicant: Azzurro Semiconductors AG
01237 Dresden (DE)
(72) Inventors:
• Lutgen, Stephan
01309 Dresden (DE)
• Murad, Saad
01705 Freital (DE)
• Chitnis, Ashay
01309 Dresden (DE)
(74) Representative: Eisenführ Speiser
Patentanwälte Rechtsanwälte PartGmbB
Anna-Louisa-Karsch-Strasse 2
10178 Berlin (DE)
(54) P-doping of group-III-nitride buffer layer structure on a heterosubstrate
(57) The invention relates to an epitaxial group-III-nitride
buffer-layer structure (100) on a heterosubstrate,
wherein the buffer-layer structure (100) comprises at
least one stress-management layer sequence S includ-ing
an interlayer structure (530) arranged between and
adjacent to a first and a second group-III-nitride layer
(120, 140), wherein the interlayer structure (130) com-prises
a group-III-nitride interlayer material having a larg-er
band gap than the materials of the first and second
group-III-nitride layers (120, 140), and wherein a p-type-dopant-
concentration profile drops, starting from at least
1x1018 cm-3, by at least a factor of two in transition from
the interlayer structure (130) to the first and second
group-III-nitride layers (120, 140).
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Description
[0001] The present invention relates to an epitaxial
group-III-nitride buffer layer structure on a heterosub-strate.
It also relates to a device structure, in particular
to a layer structure of a transistor, a field-effect transistor
(FET), a high-electron-mobility transistor (HEMT), in par-ticular
a normally-on or normally-off HEMT or a metal-insulator-
semiconductor (MIS)HEMT, a Schottky diode,
or a P-I-N structure.
[0002] Most group-III-nitride based device structures,
in particular transistor structures used nowadays for radio
frequency (RF) or high-voltage (HV) power-conversion
devices, are fabricated on a heterosubstrate, this means
on a substrate of a material other than a group-III-nitride
material, such as a Si, SiC, or Al2O3 (Sapphire) substrate.
The ability to use Si as a heterosubstrate is particularly
advantageous because it allows using relatively cheap
wafers having large industry-standard diameters, and
because it forms the basis for monolithically integrating
group-III-nitride devices into silicon-based integrated cir-cuits
made by a CMOS or related technology.
[0003] Such epitaxial group-III-nitride layer structures
grown on a heterosubstrate, however, require a sophis-ticated
buffer layer structure between the substrate and
the active layer(s) in order to manage stress and defects
within the crystalline structure.
[0004] In order to control the resistive properties of the
buffer layer structure in a group-III-nitride layer structure,
Fe doping has been widely used. However, the use of
Fe has some disadvantages. More specifically, Fe dop-ing
results in an undesired tilt and twist of the crystallite
structure, as can be revealed by x-ray diffractometry
(XRD). Furthermore, the inventors found that Fe, when
provided as a dopant during the growth of the epitaxial
layer structure, segregates towards a channel layer,
which in operation carries a two-dimensional electron
gas, hereinafter also referred to in short as 2DEG. The
presence of Fe in the channel layer is detrimental for
achieving a desired high electron concentration in the
2DEG. Finally, Fe doping causes an undesired Fe con-tamination
of the reactor used for deposition of the group-
III-nitride layer structure. This causes an undesired Fe
background doping, typically in concentrations up to
about 1017cm-3 in nominally undoped upper HEMT-de-vice
layers and on the wafer surface. Since the presence
of Fe induces traps for charge carriers, an unintentional
Fe doping reduces a dynamical behavior of the on-re-sistance
Ron of group-III-nitride based HEMT devices.
Due to the contamination risk, Fe doping is not consid-ered
compatible with wafer processing in CMOS proc-esses.
This forms an obstacle for an integration of the
fabrication of group-III-nitride devices into existing, well-established
CMOS process lines on silicon wafers.
[0005] The document US 7,884,393 discloses the use
of a homosubstrate in the form of a GaN substrate to
achieve an extremely low dislocation density in an epi-taxial
group-III-nitride layer structure grown on the ho-mosubstrate.
The low dislocation density achievable by
growth on a homosubstrate makes a carbon concentra-tion
in the different layers of the layer structure variable
to some degree. By growing on a homosubstrate and
controlling a carbon concentration, according to US
7,884,393, the quality of a buffer layer and a channel
layer of group-III-nitride field-effect transistors and
HEMTs is improved. As an application, US 7,884,393
describes a HEMT structure grown on a GaN substrate,
which has single high-resistance buffer layer deposited
immediately on the GaN substrate, a single GaN channel
layer immediately on the buffer layer, and a single barrier
layer immediately on the channel layer.. The buffer layer
is in different embodiments made of GaN or AlGaN and
has a carbon concentration of 4x1017cm-3 or higher. The
highest carbon concentration disclosed for the buffer lay-er
in US 7,884,393 is 2x1018cm-3. The adjacent channel
layer does not form a part of the buffer layer, but forms
an active layer of the HEMT. It is made of either GaN or
InGAN and has a carbon concentration of not more than
4x1016cm-3. A lower concentration of carbon in the chan-nel
layer is described in US 7,884,393 as desirable for
obtaining a high purity and thus a high electron mobility.
Group-III-nitride buffer layer structures grown on heter-osubstrates,
however, and in particular silicon, have a
much higher dislocation density compared to those
grown on a homosubtrate. This high dislocation density
can currently not be avoided. Typical dislocation densi-ties
achieved in state-of-the-art buffer layer structures on
heterosubstrates are in the range of 5x107-5x109cm-2.
[0006] A first aspect of the invention disclosed in the
present specification is an epitaxial group-III-nitride buff-er
layer structure on a heterosubstrate. The buffer layer
structure comprises at least one stress-management lay-er
sequence including an interlayer structure arranged
between and adjacent to a first and a second group-III-nitride
layer, wherein the interlayer structure comprises
a group-III-nitride interlayer material having a larger band
gap than the materials of the first and second group-III-nitride
layers, and wherein a p-type-dopant-concentra-tion
profile drops, starting from at least 1x1018 cm-3, by
at least a factor of two in transition from the interlayer
structure to the first and second group-III-nitride layers.
[0007] The p-type-dopant concentration profile match-es
the hole concentration profile if no compensation ef-fects
occur. If compensation effects have to be consid-ered,
the p-type-dopant concentration is higher than the
desired hole concentration. For instance, the p-type-do-pant
concentration may be higher by a factor of 5, 10,
20, 50 or 100 than the hole concentration achieved. Thus,
in different embodiments, the p-type-dopant concentra-tion
profile considering compensation effects drops,
starting for instance from at least 1x1019 cm-3 (factor 10),
or from 1x1020 cm-3 (factor 100), by at least a factor of
two in transition from the interlayer structure to the first
and second group-III-nitride layers.
[0008] Suitable p-type dopants are for instance carbon
and magnesium.
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[0009] The buffer layer structure of the invention is
based on the recognition, that group-III nitrides grown on
a heterosubstrate are subjected to substantial stress dur-ing
the manufacturing process. In comparison with a dep-osition
on a homosubstrate, this requires a special stress
management in the buffer-layer structure. One stress
management measure is including in the buffer layer
structure a stress-management layer sequence of an in-terlayer
structure that is arranged between and adjacent
to a first group-III-nitride layer and a second group-III-nitride
layer, which have a smaller band gap than a group-
III-nitride interlayer material. However, the provision of
this stress-management layer sequence implies the risk
of a formation of undesired parasitic conductive channels
in the buffer layer structure. The invention is based on
the further recognition that an incorporation of carbon or
magnesium as p-type dopant in the stress-management
layer sequence with a suitable concentration profile
across the stress-management layer sequence is effec-tive
in avoiding the formation of such parasitic conductive
channels in the buffer layer structure. This way, it be-comes
even possible in some embodiments to avoid any
intentional incorporation of iron atoms, which, as de-scribed,
have been used in the prior art to achieve a highly
resistive buffer layer structure.
[0010] The p-type concentration profile of the present
invention has a concentration contrast between the in-terlayer
structure on one hand and the first and second
group-III-nitride layers on the other hand. Namely, the p-type-
dopant-concentration profile drops, starting from at
least 1x1018 cm-3, by at least a factor of two in transition
from the interlayer structure to the first and second group-
III-nitride layers. Herein the drop in the p-type-dopant
concentration can either be sudden or continous. The
inventors have recognized in their experiments that a
lower contrast or lower concentration values will not be
efficient in avoiding parasitic conductive channels in the
stress-management layer sequence. The inventors are
the first to manufacture a group-III-nitride based buffer
layer structure with a stress management layer structure
that achieves the mentioned high p-type concentration
contrast between the interlayer structure and the first and
second layers even at dislocation densities in the range
of 5x107-5x109cm-2, which are for instance observed
when using a silicon substrate as the heterosubstrate.
Thus, it is only the combination of the mentioned p-type
dopant concentrations and their minimum difference as
defined above, which can provide a highly-resistive buffer
layer structure for group-III-nitrides on heterosubstrates
without having to use transition metal atoms such as iron,
which have negative side effects described earlier.
[0011] The high resistivity of the buffer layer structure
enables a subsequent manufacture of highly efficient
electronic group-III-nitride semiconductor devices based
on the buffer stress-management layer sequence, such
as group-III-nitride-based high-electron mobility transis-tors
or Schottky diodes. Consequently the buffer layer
structure according to the first aspect of the invention
allows providing a strain-managed buffer layer structure
on a heterosubstrate, which due to its high resistivity is
particularly suited as a base for highly efficient electronic
devices requiring a high resistance of the buffer layer
structure. With the buffer layer structures according to
the invention high resistivities, which means high break-down
electric field strength of more than 1 MV/cm or even
2 or 3 MV/cm can be reached. By increasing an Al content
in the interlayer structure the breakdown electric field
strength can be additionally increased.
[0012] In the following, embodiments of the buffer layer
structure of the first aspect of the invention will be de-scribed.
[0013] In a preferred embodiment of the stress-man-agement
layer sequence the interlayer structure has a
p-type-dopant concentration profile which drops in tran-sition
from the interlayer structure to the first and second
group-III-nitride layer by at least one order of magnitude
or even by at least two orders of magnitude. The building
of a 2DEG in the buffer stress-management layer se-quence
can be suppressed with higher effectivity the
higher the drop in p-type-dopant concentration is.
[0014] Preferably the p-type-dopant concentration is
constant throughout the interlayer structure.
[0015] In a preferable embodiment the first or the sec-ond,
or the first and the second group-III-nitride layer are
only unintentionally doped, this means a measured p-type
dopant concentration of not more than 1x1017 /cm3.
Higher ranges of p-type-dopant concentration of the first
or the second, or the first and the second group-III-nitride
layer in the preferable range of 1x1018 /cm3 or even
1x1019 /cm3 can be tolerated with corresponding higher
p-type-dopant concentration in the interlayer structure.
[0016] In one embodiment of the invention the inter-layer
structure is a single layer and the group-III-nitride
interlayer material is of homogeneous composition,
which has a larger band gap than the first and second
group-III-nitride layers. The concentration of the p-type
dopant in the interlayer structure is at least 6x1018 cm-3,
a p-type dopant concentration of at least 1x1020cm-3 is
preferred. P-type-dopant concentrations of at least
6x1018 cm-3 in a single interlayer have the additional ben-efit
of being able to compensate undesired parasitic ox-ygen
concentrations in the layer. Thus, higher oxygen
content in the layer is tolerable, which reduces the fab-rication
costs of the buffer-layer structure, because com-plex
and expensive measures to reduce or avoid an un-wanted
oxygen incorporation into the layers during
growth can be omitted. But even values of the p-type-dopant
concentration of the single interlayer of up to
1x1021 cm-3 are beneficial in this regard.
[0017] In another preferred embodiment the interlayer
structure comprises a first group-III-nitride interlayer that
is arranged between and adjacent to a second group-III-nitride
interlayer and a third group-III-nitride interlayer.
The first, second and third group-III-nitride interlayer
have a respective homogeneous composition. A band
gap of the first group-III-nitride interlayer is larger than
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band gaps of the second group-III-nitride interlayer and
of the third group-III-nitride interlayer. The p-type-dopant
concentration throughout the interlayer structure is at
least 5x1018cm-3. Such an interlayer structure allows the
use of a p-type-dopant concentration at a level between
5x1018cm-3and 1x1019cm-3. The doping level that can
be electrically activated is limited. Moderate p-type do-pant
concentrations in the interlayer structure which are
able to eliminate the parasitic 2DEG channels are pre-ferred
because a higher p-type doping level can cause
undesired process fluctuations. Nevertheless if process
fluctuations can be compensated in another way, also
higher p-type dopant concentrations are preferred.
[0018] In a variation of this embodiment the material
of the first and second group-III-nitride layer is the same
as the material of second and third group-III-nitride inter-layers
and the group-III-nitride interlayer material having
a larger band gap than the materials of the first and sec-ond
group-III-nitride layers is the material of the first
group-III-nitride interlayer.
[0019] In another preferred embodiment the interlayer
structure comprises a first group-III-nitride interlayer that
is arranged between and adjacent to a second group-III-nitride
interlayer and a third group-III-nitride interlayer
and the first group-III-nitride interlayer is compositionally
graded. In this embodiment a p-type doping concentra-tion
of 1x1018 cm-3 throughout the interlayer structure is
already sufficient to avoid the building of a parasitic 2
DEG channel.
[0020] By using the described three-layer structure of
the interlayer structure and especially a compositionally
graded first group-III-nitride interlayer, p-type doping
concentrations of 5x1018 cm-3, respectively 1x1018 cm-3
in the first group-III-nitride interlayer are sufficient to com-pensate
undesired parasitic oxygen concentrations in the
respective layer.
[0021] In another embodiment, the group-III-nitride in-terlayer
material having a larger band gap additionally
has a larger oxygen concentration than either the first or
the second group-III-nitride layer, or than both the first
and the second group-III-nitride layer.
[0022] The first group-III-nitride interlayer is preferably
made of AlGaN having an Al mole fraction that increases
with increasing distance from the substrate. Such an in-crease
of the Al mole fraction with increasing distance
improves the stress management of the buffer layer
structure as well as it allows the use of lower p-type-dopant
concentrations in the interlayer structure.
[0023] A compositional grading of the second group-
III-nitride interlayer or the third group-III-nitride interlayer
or the second and the third group-III-nitride interlayer is
part of another embodiment of the invention. The grading
of these layers is especially advantageous in regard of
avoiding additional stress due to lattice mismatches be-tween
the first group-III-nitride interlayer on one side and
the first and second group-III-nitride layer on the other
side.
[0024] In another embodiment of the invention the con-centration
of the p-type dopant is higher in the second
and third group-III-nitride interlayers than in the first
group-III-nitride interlayer.
[0025] As p-type dopant carbon or magnesium, or a
combination of carbon and magnesium are preferred.
[0026] In preferred embodiments, there is no intention-al
Fe doping throughout the buffer layer structure. This
is for instance expressed in an Fe concentration of less
than 4x1016cm-3. However, in some embodiments it may
still be useful to also include iron in the buffer layer struc-ture.
Due to the presence of p-type dopant according to
the present invention, iron can be incorporated in the
buffer-layer structure in much lower concentrations, com-pared
to prior-art buffer-layer structures.
[0027] In a favorable embodiment of the invention the
buffer layer structure comprises at least two stress-man-agement
layer sequences, wherein a second stress-management
layer sequence is arranged at a larger dis-tance
from the substrate than a first stress-management
layer sequence and has a second interlayer structure .
With additional interlayer structures the stress manage-ment
of the buffer layer structure on the heterosubstrate
and the quality of subsequent active layers can be im-proved.
[0028] This can be further improved by the use of a
second interlayer structure, which differs from the first
interlayer structure in at least one of the following: a layer
thickness of at least one of the interlayers of the interlayer
structure, a p-type-dopant-concentration in at least one
of the interlayers of the interlayer structure, a material
composition of at least one of the interlayers of the inter-layer
structure, and a number of interlayers in the inter-layer
structure.
[0029] Another preferable embodiment comprises an
additional group-III-nitride layer which is deposited on
top of the buffer layer structure and wherein the additional
layer has a graded p-type-dopant concentration, wherein
the p-type dopant concentration is higher in a first section
of the additional layer adjacent to the buffer layer than in
a second section of the additional layer further away from
the buffer layer. Favorably the buffer layer structure is
grown on a heterosubstrate such as a silicon, a silicon-on-
insulator, a silicon carbide substrate, a Diamond or a
Ga2O3-substrate.
[0030] In preferred embodiments, the stress-manage-ment
layer sequence is configured to introduce a com-pressive
stress in buffer layer structure during growth,
which fully or at least partially compensates a tensile
stress developing after growth during a cooling down of
the buffer layer structure from growth temperature to
room temperature.
[0031] Preferably, the group-III-nitride interlayer mate-rial
having a larger band gap than the materials of the
first and second group-III-nitride layers is a binary, ter-nary
or quaternary first group-III-nitride material that has
higher aluminum content than a second group-III-nitride
material forming the first and second group-III-nitride lay-er.
AlN, AlGaN, AlInGaN or AlInN are favorable materials
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forming the group-III-nitride interlayer material. In some
embodiments, the layer made of the group-III-nitride in-terlayer
material is a low-temperature layer, that is, it is
grown at a lower temperature than the adjacent first and
second group-III-nitride layers. Also the use of similar
growth temperatures in the interlayer structure and the
first and second group-III-nitride layers can be useful in
certain embodiments.
[0032] In order to further improve the stress manage-ment
and the resistivity, an embodiment of the invention
further comprises a buffer stack deposited between the
heterosubstrate and the stress-management layer se-quence,
the buffer stack comprising
a) either a compositionally graded AlGaN buffer layer
having a Ga fraction increasing with increasing dis-tance
from the heterosubstrate,
b) or a superlattice formed by a stack of alternating
group-III-nitride layers of two kinds,
wherein the buffer stack has a p-type-dopant concentra-tion
of at least 1x1018 cm-3.
[0033] In regard of a further improved stress-manage-ment
in combination with high resistivity in the whole buff-er
layer structure an embodiment of the invention is pre-ferred,
which comprises a nucleation layer between the
buffer stack and the substrate, wherein the nucleation
layer has a p-type dopant concentration of at least 1x1018
cm-3.
[0034] In a further embodiment, the invention relates
to a group-III-nitride device on a heterosubstrate, in par-ticular
a transistor, FET, a normally-on or a normally-off
(MIS)-HEMT, Schottky diode, PIN structure, comprising
the epitaxial group-III-nitride buffer layer structures ac-cording
to the first aspect of the invention or one of its
embodiments. The buffer layer structures according to
the invention are also advantageous for the use in opto-electronic
devices such as LEDs or laser diodes. The
device performance is substantially improved by includ-ing
the buffer layer structure of the present invention.
[0035] Preferably the group-III-nitride device compris-es
an only unintentionally doped channel active group-
III-nitride layer, which means a p-type-dopant concentra-tion
of not more than 1x1017cm-3, preferably lower than
4x1016cm-3. Such a low p-type-dopant concentration in
the active layer enables highly efficient performance of
the group-III-nitride device, where high conductivity is re-quired
in the active group-III-nitride layer.
[0036] In another embodiment the group-III-nitride de-vice
is a HEMT. Here, the active layer forms a channel
layer. The HEMT further comprises a barrier layer on the
active layer. A 2DEG can thus form at an interface be-tween
the channel layer and the barrier layer. Thin inter-mediate
layers between the channel layer and the active
layers may be used, as is known as such in the prior art.
Preferably, the HEMT further comprises a cap layer on
the barrier layer. The cap layer may comprise one or
more p-type dopants. Carbon or magnesium may be
used as the p-dopant or as one of the p-type dopants
herein as well.
[0037] In a second aspect, the invention relates to a
method for fabricating a p-type-doped group-III-nitride
buffer layer structure on a heterosubstrate, the method
comprising
- fabricating an epitaxial group-III-nitride buffer layer
structure on a heterosubstrate, wherein the buffer
layer structure is fabricated as comprising a stress-management
layer sequence including an interlayer
structure arranged between and adjacent to a first
and a second group-III-nitride layer, wherein the in-terlayer
structure comprises a group-III-nitride inter-layer
material having a larger band gap than the ma-terials
of the first and second group-III-nitride layers,
and wherein the stress management layer sequence
is fabricated to have a p-type-dopant-concentration
profile, which drops, starting from at least 1x1018
cm-3, by at least a factor of two in transition from the
interlayer structure to the first and second group-III-nitride
layers.
[0038] Favorably, metal-organic vapor epitaxy
(MOVPE) or metal-organic chemical vapor deposition
(MOCVD) is used as a deposition method.
[0039] In a preferred embodiment of the method the
layer made of the group-III-nitride interlayer material hav-ing
a larger band gap than the materials of the first and
second group-III-nitride layers is deposited at a temper-ature
lower than the temperature at which the first group-
III-nitride layer and the second group-III-nitride layer are
grown. With this temperature management, growth rate
and V/III-ratio a high difference between the p-type do-pant
concentration in the group-III-nitride interlayer ma-terial
and in the first or second group-III-nitride layer can
be achieved. At the same time, this is advantageous for
the stress-management function of the layer sequence.
[0040] In a preferred embodiment of the method before
the deposition of the stress-management layer sequence
a AlN nucleation layer is deposited on the substrate by
a vapor phase deposition technique using a hydrogen-free
carrier gas, preferably N2, at a temperature between
800 and 1030 °C, followed by a deposition of a buffer
stack before depositing the stress-management layer se-quence
by using Tetraethylgallium and Trimethylalumi-num
as precursors at a temperature between 800 and
1030 °C, wherein the buffer stack comprises
a) either a compositionally graded AlGaN buffer layer
having a Ga fraction increasing with increasing dis-tance
from the heterosubstrate,
b) or a superlattice formed by a stack of alternating
group-III-nitride layers of two kinds. The low temper-atures
during the growth of the AlN nucleation layer
and the buffer stack are advantageous for the incor-
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poration of carbon concentrations of more than
1x1017 cm-3 and lead to a better crystal quality.
[0041] In order to control the p-type dopant concentra-tion
in the different layers of the buffer layer structure
several growth parameters other than the growth tem-perature
can be controlled and adjusted. Under other-wise
constant growth conditions, increasing a flow rate
of a nitrogen source used in the preparation of a layer
leads to a decreased p-type dopant concentration in the
layer. An opposite effect is achieved by a higher flow rate
of a gallium precursor. A higher V/III ratio during the
growth of a layer also leads to a lower p-type dopant
concentration in the layer. A similar effect is achieved by
a higher ambient pressure in the reactor and by a lower-ing
the growth rate of a layer. An additional means to
control and adjust the p-type dopant concentration is the
use of special C-precursors like for example CBr4, CCI4.
[0042] Further embodiments of the invention will be
described hereinafter with reference to the drawings, in
which:
Fig. 1 shows an embodiment of a buffer layer struc-ture
according to the first aspect of the invention;
Fig. 2 shows another embodiment of a buffer layer
structure according to the first aspect of the inven-tion;
Fig. 3 shows an embodiment of a group-III-nitride
device according to the invention,
Fig. 4 a) shows a concentration diagram for parts of
a transistor based on a buffer layer structure accord-ing
to the invention,
Fig. 4 b) shows a current-voltage characteristic of
the transistor of Fig. 4 a),
Fig. 5 shows another embodiment of a buffer layer
structure according to the first aspect of the inven-tion,
Fig. 6 shows an aluminum content profile (a)), a hole
concentration profile (b)) and band gap profiles at 0
V (c)) of variation 1 of the structure of Fig. 5.
Fig. 7 shows an aluminum content profile (a)), a hole
concentration profile (b)) and band gap profiles at 0
V (c)) of variation 2 of the structure of Fig. 5.
Fig. 8 shows an aluminum content profile (a)), a hole
concentration profile (b)) and band gap profiles at
300 V (c)) of variation 3 of the structure of Fig. 5.
[0043] Fig. 1 shows an embodiment of a buffer layer
structure 100 according to the first aspect of the invention.
On a substrate 110, which in the present embodiment is
made of silicon or silicon carbide, an intermediate layer
may be grown. This intermediate layer is not shown in
detail in Fig. 1, but only indicated by a space above the
substrate 110. Such intermediate layer, which may con-tain
a sub-layer structure, serves for achieving nucleation
and initial lattice adaptation. In some embodiments, how-ever,
the intermediate layer may be omitted, and the buff-er
layer structure grown directly on the substrate. Exam-ples
of an intermediate layer in the form of a buffer stack
will be described further below.
[0044] The buffer layer structure 100 comprises a
stress-management layer sequence S. The stress-man-agement
layer sequence is formed of three group-III-ni-tride
layers 120 to 140, of which an single interlayer 130
is sandwiched between a first group-III-nitride layer 120
and a second group-III-nitride layer 140.
[0045] In this stress-management layer sequence S,
the first group-III-nitride layer 120 is deposited first. It is
made of GaN. In other embodiments, it is made of AlGaN.
The thickness of the first group-III-nitride layer 120 is typ-ically
between 300 and 2000 nm, for instance 590 nm.
[0046] Directly on the first group-III-nitride layer 120,
the single interlayer 130 is deposited. In the present ex-ample,
it is made of AlGaN. Alternative embodiments use
AlN, or AlInN, or AlInGaN.
[0047] The thickness of the single interlayer is typically
between 10 and 50 nm. In the present example it is 30 nm.
[0048] Directly on the single interlayer 130, the second
group-III-nitride layer 140 is grown. In the present exam-ple,
it is made of the same material as the first group-III-nitride
layer, that is GaN. In other embodiments, it is made
of AlGaN. Its thickness is typically between 300 nm and
1.5 mm. In the present example it is 1 mm thick.
[0049] The single interlayer 130 has a carbon concen-tration
of 1x1019cm-3. In contrast, the first group-III-nitride
layer and the second group-III-nitride layer have a lower
carbon concentration of not more than 1x1018cm-3. In
the present example, their carbon concentration is
1x1017cm-3. Due to the different composition of the Al-
GaN of the single interlayer 130 in comparison with the
GaN of the first and second group-III-nitride layers 120
and 140, a difference in lattice constants is achieved,
which correlates with a difference in band gap. The dif-ference
in lattice constants introduces a stress compo-nent
that at least partially compensates stress created
by the growth on the heterosubstrate. The stress-man-agement
layer sequence S made of GaN-AlGaN-GaN is
thus able to reduce a stress which occurs in the buffer
layer structure and any layers grown on top of it. On the
other hand, the stress-management layer sequence also
introduces a band structure profile that tends to allow the
formation of parasitic conductive channels, which may
even comprise a 2DEG near the interfaces between the
GaN and AlGaN materials. By introducing carbon at the
given concentration levels the building of a 2DEG at the
interfaces of single interlayer 130 and first and second
group-III-nitride layers 120 and 140 is suppressed. Due
to its higher carbon concentration, especially the single
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interlayer layer 130 exhibits also a high resistivity which
is needed for the subsequent building of high efficient
electronic devices based on such a buffer layer structure.
[0050] Fig. 2 shows another embodiment of a buffer
layer structure 200 according to the first aspect of the
invention. Compared with the buffer layer structure 100
of Fig. 1, the buffer layer structure 200 comprises a nu-cleation
layer 255 and a superlattice 250 between a sec-ond
group-III-nitride layer 220 and the substrate 210. The
superlattice 250 and the nucleation layer form an exam-ple
of an intermediate layer. The nucleation layer 255 is
an AlN layer. The superlattice 250 in this embodiment is
a high temperature AlGaN / low temperature AlGaN su-perlattice
with a thickness of 100 nm. The nominal com-position
of the high- and low-temperature AlGaN layers
is identical. The nucleation layer 255 and the superlattice
250 further improve the stress management of the buffer
layer structure 200. The nucleation layer 255 and the
superlattice 250 have a carbon concentration of 5x1018
cm-3 in this example, which improves the resistivity of the
buffer layer structure. Other favorable embodiments of
the superlattice are AlGaN/GaN or AlN/GaN superlattic-es.
[0051] The use of several first group-III-nitride interlay-ers
within the buffer layer structure further improves the
stress management, in particular in the case of a silicon
substrate, where the lattice mismatch to group-III-nitride
materials is particularly high. Therefore, on the stress-management
layer sequence S comprising the first
group-III-nitride layer 220, the single interlayer 230 and
the second group-III-nitride layer 240, two repetitions of
the stress management layer sequence are deposited.
A first repetition contains a further single interlayer 231
and a further group-III-nitride layer 241, the group-III-ni-tride
layer 240 is the first group-III-nitride layer in regard
of the second single interlayer 231 and at the same time
the second group-III-nitride layer in regard of the first sin-gle
interlayer 230. A second repetition contains a further
single interlayer 232 and a further group-III-nitride layer
242. Here the group-III-nitride layer 241 is the first group-
III-nitride layer in regard of the third single interlayer 232
and the second group-III-nitride layer in regard of the
second single interlayer 231. The first single interlayer
230 and its repetitions 231, 232 are thus all arranged
between and adjacent to group-III-nitride layers, which
in comparison have a lower band gap.
[0052] In a further embodiment also properties other
than the thickness of the single interlayers can vary, pref-erably
the Al content can decrease in the direction point-ing
away from the substrate. In another embodiment (not
shown) more than one layer with lower band gap may
follow the first group-III-nitride layer (or any of its repeti-tions).
[0053] The single interlayer 231 in this embodiment
has identical properties (composition, thickness, growth
temperature) as single interlayer layer 230. The group-
III-nitride layer 241 corresponds to the third group-III-ni-tride
layer 240. However, in the present example, it is
somewhat thicker than the third group-III-nitride layer
240, namely 2 mm thick. It is thus possible, but not a
requirement to have the layers of the second stress man-agement
layer sequence S1 identical to corresponding
layers of the original stress management layer sequence
S. It is also possible to vary layer thicknesses between
different repetitions of the second stress management
layer sequence S2. However, the thickness of the first
group-III-nitride layer 230 and its corresponding repeti-tions
in the layers 231 and 232 is preferably the same.
[0054] Fig. 3 shows a transistor 300 as an application
case of the group-III-nitride buffer layer structure accord-ing
to the invention. In this embodiment, an AlGaN buffer
layer 350 having a Ga fraction increasing with increasing
distance from a silicon substrate 310 is grown on the
silicon substrate 310.
[0055] On the AlGaN buffer layer 350, a stress-man-agement
layer sequence S is formed of three group-III-nitride
layers 320 to 340, of which a single interlayer 330
is sandwiched between a first group-III-nitride layer 320
and a second group-III-nitride layer 340. For the detailed
characteristics of these layers, we refer to the above de-scription
of the layers 120 to 140 of the embodiment of
Fig. 1.
[0056] The stress-management layer sequence S is
followed by a back barrier layer 360. The back barrier
layer 360 is made of AlGaN and has a graded carbon
concentration starting with a carbon concentration of
1x1018cm-3 at an interface between back barrier layer
360 and third group-III-nitride layer 340, and ending with
a carbon concentration of less than 4x1016 cm-3 at an
interface between back barrier layer 360 and a following
active layer 370.
[0057] The active layer 370, which forms a channel
layer that contains a 2DEG charge carrier channel active
in operation of the transistor, is made of GaN and has a
carbon concentration of 4x1016 cm-3. In the present ex-ample,
it is 40 nm thick. A transistor based on the de-scribed
structure shows the following properties: a
charge carrier densitiy of around 1x1013cm-2, a high elec-tron
mobility of 1000-2500 cm2/(V·s) and a low sheet re-sistance
clearly below 400 Ω/sq.
[0058] On the active layer 370, a barrier layer 380 is
grown. The barrier layer is an AlGaN (AlGaInN) layer in
the present example. In other embodiments, other com-positions
may be used that are suitable to form a potential
barrier for charge carriers that are in the channel layer.
The barrier layer has a thickness of 25 nm in the present
example. A cap layer 390 is grown on the barrier layer
380 and forms a uppermost layer of the transistor struc-ture
(disregarding contacts). In the present case for d
mode HEMT devices, the cap layer 390 is a p-doped
GaN layer with a thickness of 4nm. In the cap layer 390
carbon is used a dopant at a concentration level of 1017
cm-3 in this example.
[0059] The buffer layer structure of this embodiment
leads to a favorable stress management of the whole
structure and at the same time achieves a high resistance
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below the active layers. The graded back barrier layer
360 additionally prevents carriers from entering the un-derlying
layers of the buffer layer structure and the sub-strate,
which improves the electrical performance of the
device. The active layer 370 (GaN or InGaN) grown on
the buffer layer structure exhibits a high crystal quality
and a low resistance due to its low carbon concentration.
With the GaN cap layer 390 a good electrical contact to
contact structures and external devices is achieved. To
reduce the series resistance of the HEMT device addi-tional
recess etching of GaN-cap and part of the AlGaN-layer
in lateral sections for ohmic contact formation is
favorable.
[0060] Fig. 4 a) shows a concentration diagram for
parts of a transistor based on a buffer layer structure
according to the invention as obtained from a secondary
ion mass spectroscop (SIMS) measurement. Fig. 4b
shows a current-voltage characteristic of the transistor
of Fig. 4 a).
[0061] Fig. 4 a) shows traces of an aluminum concen-tration
4000, a carbon concentration 4100 and an oxygen
concentration 4200 on a logarithmic scale as a function
of depth for a portion of the transistor including a buffer
layer structure. Maxima 430, 431, 432 and 433 of the
aluminium concentration 4000 are detected at the posi-tions
of the single interlayers. This is indicative of an Al
contribution to AlGaN stoichiometry of the single inter-layers
[0062] A maximum 480 in the aluminum trace 4000
represents an AlGaN barrier layer. As can be seen from
the diagram of Fig. 4 a), also the carbon concentration
4100 and the oxygen concentration exhibit respective
maxima at the positions of the first group-III-nitride layers,
i.e., at the Al peaks. The carbon concentration in the sin-gle
interlayers is 2x1020cm-3, while the carbon concen-tration
in the GaN layers between the single interlayers
is slightly below 1x1017cm-3. Thus the carbon concen-tration
in the single interlayers is 3 orders of magnitude
higher than in the GaN layers therebetween. The forma-tion
of a 2DEG in the buffer layer structure is thereby
suppressed. As shown in the diagram of Fig. 4 b) the
transistor based on the described buffer layer structure
with high carbon content (4300) exhibit high breakdown
voltage and low leakage current. The characteristic curve
of a transistor according to the invention is herein com-pared
with the characteristic curve (4301) of a transistor
based on a buffer layer structure which differs from the
claimed structure in the fact that a low p-type concentra-tion
of less than 1x1018cm-3 is used in the interlayer struc-tures.
[0063] Fig. 5 shows another embodiment of a buffer
layer structure 500 according to the first aspect of the
invention. Compared with the buffer layer structures of
the Fig. 1 to 4, the buffer layer structure 500 comprises
an interlayer structure 530 comprising three different lay-ers
instead of a single layer. After the growing of the first
group-III-nitride layer 520, in this example made of unin-tentionally
doped GaN, a second group-III-nitride inter-layer
536 is grown also consisting of GaN. The second
group-III-nitride interlayer is followed by a first group-III-nitride
interlayer 535 and a third group-III-nitride interlay-er
537, whereby the third group-III-nitride interlayer 536
also consist of GaN and is followed by a second group-
III-nitride layer 540. The second and third group-III-nitride
interlayers 535 and 537 have thicknesses of 50 nm in
this embodiment. Thicknesses between 20 and 200 nm
are favorable for these layers. The first group-III-nitride
interlayer 535 comprises a group-III-nitride interlayer ma-terial
having a larger band gap than the materials of the
first and second group-III-nitride layers 520, 540, in this
case AlGaN, and has a thickness of 30 nm. In the follow-ing
variations of the buffer layer structure including dif-ferent
modifications of the Al content of the first group-
III-nitride interlayer 535 and of the p-dopant concentra-tion
will be presented and their effects on the prevention
of the 2DEG building.
Variation 1
[0064] Variation 1 of the layer structure shown in Fig.
5 includes the use of a first group-III-nitride interlayer 535
with constant aluminum content. The aluminum content
profile for the structure is shown in Fig. 6 a) in principle.
As stated before in this embodiment the second and third
group-III-nitride interlayers 536 and 537 are made of GaN
as well as the first and second group-III-nitride layers 520
and 540. The first group-III-nitride interlayer 535 consist
of AlGaN. Fig. 6 b) shows the hole concentration profile
for the structure, the hole concentration is 5x1018 cm-3
within the whole interlayer structure, thus in all three
group-III-nitride interlayers 535, 536 and 537. The first
and second group-III-nitride layers 520 and 540 are un-intentionally
doped. The hole concentration in the inter-layer
structure is achieved by intentionally doping the in-terlayers
with magnesium or carbon. The shown hole
concentration profile for this layer structure leads to the
energy profiles of the layer structure shown in Fig. 6 c),
whereby 601 represents the conduction band energy pro-file
and 602 represents the valence band profile. As can
be seen in Fig. 6 c) the building of a 2DEG at the interfaces
between AlGaN and GaN, thus between the first group-
III-nitride interlayer 535 and the second and third group-
III-nitride interlayers 536 and 537 is effectively sup-pressed.
Variation 2
[0065] Variation 2 of the layer structure shown in Fig.
5 includes the use of a first group-III-nitride interlayer 535
with a gradient in the aluminum content. The aluminum
content profile for the structure is shown in Fig. 7 a) in
principle. In this embodiment the second and third group-
III-nitride interlayers 536 and 537 are made of GaN as
well as the first and second group-III-nitride layers 520
and 540. The aluminum content of the first group-III-ni-tride
interlayer 535 increases from 10 % at the interface
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to the second group-III-nitride interlayer 536 to 70 % at
the interface to third group-III-nitride interlayer 537. The
increase can be either continous as shown in the diagram
or stepwise.
[0066] Fig. 7 b) shows the hole concentration profile
for the structure, the hole concentration for this embod-iment
is 1x1018 cm-3 within the whole interlayer structure,
thus in all three group-III-nitride interlayers 535, 536 and
537. The first and second group-III-nitride layers 520 and
540 are unintentionally doped.
[0067] As can be seen in Fig. 7 c) the building of a
2DEG at the interfaces between AlGaN and GaN, thus
between the first group-III-nitride interlayer 535 and the
second and third group-III-nitride interlayers 536 and 537
is effectively suppressed with the relatively smaller hole
concentration respectively p-dopant-concentration if a
graded AlGaN layer is used as the first group-III-nitride
interlayer.
Variation 3
[0068] Variation 3 of the layer structure shown in Fig.
5 shows compared to Variation 2 another advantageous
hole concentration profile with which the building of par-asitic
2DEG can be effectively suppressed. The alumi-num
content profile for the structure, shown in Fig. 8 a)
is in principle the same as the one shown in Fig. 7 a).
[0069] Fig. 8 b) shows the hole concentration profile
for the structure, the hole concentration for this embod-iment
is 5x1018 cm-3 only in the second and third group-
III-nitride interlayers 536 and 537, the first group-III-ni-tride
interlayer 535 is unintentionally doped as well as
the first and second group-III-nitride layers 520 and 540.
[0070] As can be seen in Fig. 8 c) where the energy
bands fo the structure at 300V are shown, the building
of a 2DEG at the interfaces between AlGaN and GaN,
thus between the first group-III-nitride interlayer 535 and
the second and third group-III-nitride interlayers 536 and
537 can also effectively be suppressed without intention-al
doping of the first group-III-nitride interlayer 535 if the
doping level of the second and third group-III-nitride in-terlayers
536 and 537 is sufficiently high, even in oper-ation.
[0071] As described in Fig. 2 relating to single interlay-ers
also with the described interlayer structures compris-ing
three group-III-nitride interlayers repetitions of the
stress-management layer sequence are advantageous.
For example a first stress-management layer sequence
comprising a single interlayer made of AlN followed by a
three stress-management layer sequences each com-prising
a three-layer interlayer structure of GaN-AlGaN-GaN
can be advantageous.
Claims
1. An epitaxial group-III-nitride buffer-layer structure on
a heterosubstrate, wherein the buffer-layer structure
comprises at least one stress-management layer se-quence
including an interlayer structure arranged
between and adjacent to a first and a second group-
III-nitride layer, wherein the interlayer structure com-prises
a group-III-nitride interlayer material having a
larger band gap than the materials of the first and
second group-III-nitride layers, and wherein a p-type-
dopant-concentration profile drops, starting
from at least 1x1018 cm-3, by at least a factor of two
in transition from the interlayer structure to the first
and second group-III-nitride layers.
2. The buffer-layer structure according to claim 1,
wherein the p-type-dopant-concentration profile
drops in transition from the interlayer structure to the
first and second group-III-nitride layers by at least
one order of magnitude.
3. The buffer-layer structure according to claim 1,
wherein the p-type-dopant-concentration profile
drops in transition from the interlayer structure to the
first and second group-III-nitride layers by at least
two orders of magnitude.
4. The buffer-layer structure according to one of the
claims 1 to 3, wherein the p-type-dopant-concentra-tion
is constant throughout the interlayer structure.
5. The buffer-layer structure of one of the preceding
claims, wherein the interlayer structure is a single
layer and the group-III-nitride interlayer material is
of homogeneous composition, which has a larger
band gap than the first and second group-III-nitride
layers and wherein the concentration of the p-type
dopant in the interlayer structure is at least
6x1018cm-3.
6. The buffer-layer structure of one of the claims 1 to
4, wherein
- the interlayer structure comprises a first group-
III-nitride interlayer that is arranged between
and adjacent to a second group-III-nitride inter-layer
and a third group-III-nitride interlayer,
- the first, second and third group-III-nitride in-terlayer
have a respective homogeneous com-position,
- a band gap of the first group-III-nitride interlayer
is larger than band gaps of the second group-
III-nitride interlayer and the third group-III-nitride
interlayer, and wherein
- the p-type-dopant concentration throughout
the interlayer structure is at least 5x1018cm-3.
7. The buffer-layer structure of one of the claims 1 to
4, wherein the interlayer structure comprises a first
group-III-nitride interlayer that is arranged between
and adjacent to a second group-III-nitride interlayer
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and a third group-III-nitride interlayer, and wherein
the first group-III-nitride interlayer is compositionally
graded.
8. The buffer-layer structure of one of the claims 1 to
4, wherein
- the interlayer structure comprises a first group-
III-nitride interlayer that is arranged between
and adjacent to a second group-III-nitride inter-layer
and a third group-III-nitride interlayer,
- wherein the second group-III-nitride interlayer
or the third group-III-nitride interlayer or the sec-ond
and the third group-III-nitride interlayer are
compositionally graded.
9. The buffer-layer structure of claim 7, wherein the first
group-III-nitride interlayer is made of AlGaN having
an Al mole fraction that increases with increasing
distance from the substrate.
10. The buffer layer structure according to one of the
preceding claims, wherein the group-III-nitride inter-layer
material having a larger band gap additionally
has a larger oxygen concentration than either the
first or the second group-III-nitride layer, or than both
the first and the second group-III-nitride layer.
11. The buffer-layer structure of claim 7 or 9, wherein
the concentration of the p-type dopant is higher in
the second and third group-III-nitride interlayers than
in the first group-III-nitride interlayer.
12. The buffer-layer structure of one of the preceding
claims, wherein the p-type dopant is carbon or mag-nesium,
or a combination of carbon and magnesium.
13. The buffer-layer structure of one of the preceding
claims, wherein the first or the second, or the first
and the second group-III-nitride layer has a p-type-dopant
concentration between 1x1016 /cm3 and
1x1018 /cm3.
14. The buffer layer structure according to one of the
preceding claims, comprising at least two stress-management
layer sequences wherein a second
stress-management layer sequence arranged at a
larger distance from the substrate than a first stress-management
layer sequence has a second interlay-er
structure.
15. The buffer layer structure according to claim 14,
wherein the second interlayer structure differs from
the first interlayer structure in at least one of the fol-lowing:
a layer thickness of at least one of the inter-layers
of the interlayer structure, a p-type-dopant-concentration
in at least one of the interlayers of the
interlayer structure, a material composition of at least
one of the interlayers of the interlayer structure, and
a number of interlayers in the interlayer structure.
16. The buffer layer structure according to one of the
preceding claims, wherein an additional group-III-ni-tride
layer is deposited on top of the buffer layer struc-ture
and wherein the additional layer has a graded
p-type-dopant-concentration profile, wherein the p-type-
dopant concentration is higher in a first section
of the additional layer adjacent to the buffer layer
than in a second section of the additional layer further
away from the buffer layer.
17. The buffer layer structure according to one of the
preceding claims, wherein the heterosubstrate is ei-ther
a silicon substrate, a silicon-on-insulator sub-strate,
or a silicon carbide substrate.
18. The buffer layer structure according to one of the
preceding claims, further comprising a buffer stack
deposited between the heterosubstrate and the
stress-management layer sequence, the buffer
stack comprising
a) either a compositionally graded AlGaN buffer
layer having a Ga fraction increasing with in-creasing
distance from the heterosubstrate,
b) or a superlattice formed by a stack of alter-nating
group-III-nitride layers of two kinds,
wherein the buffer stack has a p-type-dopant con-centration
of at least 1x1017 cm-3.
19. A group-III-nitride device, in particular a transistor, a
FET, a normally-on or a normally-off HEMT or MIS-HEMT,
a Schottky diode, a PIN diode, a LED com-prising
an epitaxial group-III-nitride buffer layer
structure on a heterosubstrate according to one of
the preceding claims.
20. A method for fabricating a p-type-doped group-III-nitride
buffer layer structure on a heterosubstrate,
the method comprising
- fabricating an epitaxial group-III-nitride buffer
layer structure on a heterosubstrate, the buffer
layer structure comprising a stress-manage-ment
layer sequence including an interlayer
structure arranged between and adjacent to a
first and a second group-III-nitride layer, and the
interlayer structure comprising a group-III-ni-tride
interlayer material having a larger band gap
than the materials of the first and second group-
III-nitride layers, wherein
- the stress management layer sequence is fab-ricated
with a p-type-dopant-concentration pro-file,
which drops, starting from at least 1x1018
cm-3, by at least a factor of two in transition from
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the interlayer structure to the first and second
group-III-nitride layers.
21. The method according claim 20 further comprising,
before fabricating the stress-management layer se-quence,
- depositing a AlN nucleation layer on the sub-strate
at a temperature between 800 and 1030
°C by a vapor phase deposition technique using
a hydrogen-free carrier gas
- depositing a buffer stack before depositing the
stress-management layer sequence by using
Tetraethylgallium and Trimethylaluminum as
precursors at a temperature between 800 and
1030°C,
- wherein the buffer stack comprises
a) either a compositionally graded AlGaN
buffer layer having a Ga fraction increasing
with increasing distance from the hetero-substrate,
b) or a superlattice formed by a stack of al-ternating
group-III-nitride layers of two
kinds, and wherein
the nucleation layer and the buffer stack are fab-ricated
with a p-type-dopant concentration of at
least 1x1018 cm-3.
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REFERENCES CITED IN THE DESCRIPTION
This list of references cited by the applicant is for the reader’s convenience only. It does not form part of the European
patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be
excluded and the EPO disclaims all liability in this regard.
Patent documents cited in the description
• US 7884393 B [0005]