This document describes an all-solution-processed non-volatile memory device based on graphene quantum dots (GQDs) embedded in graphene oxide layers. The memory device was fabricated on a flexible PET substrate using spin-coating and spray-coating deposition of the layers. Electrical characterization showed bistable switching behavior with an ON/OFF current ratio of 105. Various conduction mechanisms were proposed to describe the charge trapping and transport processes in the GQD-based memory, including Schottky emission, Poole-Frenkel emission, and trapped charge limited current conduction. The GQDs provided nanoscale charge trapping sites to enable multilevel switching and non-volatility in the graphene oxide-based resistive memory structure

1. Vol.:(0123456789)
1 3
Journal of Materials Science: Materials in Electronics
https://doi.org/10.1007/s10854-019-02015-3
Electrical bistabilities behaviour of all‑solution‑processed non‑volatile
memories based on graphene quantum dots embedded in graphene
oxide layers
Muhammad Musoddiq Jaafar1,2
· Poh Choon Ooi1
· M. F. Mohd. Razip Wee1
·
Muhammad Aniq Shazni Mohammad Haniff3
· Mohd Ambri Mohamed1
· Edward Yi Chang2,4,5
·
Burhanuddin Yeop Majlis1
· Chang Fu Dee1
Received: 24 May 2019 / Accepted: 10 August 2019
© Springer Science+Business Media, LLC, part of Springer Nature 2019
Abstract
This study demonstrates the feasibility of all-solution-processed mean to fabricate carbon-based non-volatile memory (NVM).
The NVM devices were fabricated on polyethylene terephthalate (PET) substrate using spin-coating and spray-coating
techniques in the structure of silver nanowires (AgNWs)/graphene oxide (GO)/graphene quantum dots (GQDs)/graphene
oxide (GO)/poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS)/PET. PEDOT:PSS was used as the bot-
tom conductive layer and deposited by spin-coating method. GQDs were used as a charge trapping site in the structure and
embedded in the two GO insulator layers. The AgNW metal electrode was formed on top of GO/GQDs/GO/PEDOT:PSS by
the spray-coating method. The overall smooth surface morphology of the spray-coated films serves as good contact with the
top metal electrode. The electrical characterization of the fabricated device shows the bistable current states with the ON/
OFF ratio of ­
105
. The NVM device can be programmed and erased multiple times. Various conduction mechanisms were
proposed to describe the charge trapping process in GQD based on the obtained current–voltage measurement.
1 Introduction
Traditional Si-based information storage technology has
come to theoretical and physical limits. Thus, it has moti-
vated researchers to develop a new generation of non-vola-
tile memory (NVM) cells for the growing demand in modern
electronics devices [1]. A recent study has demonstrated that
metal nanoparticles, semiconductor quantum dots, carbon
nanotubes, core–shells semiconductor nanocrystals were
blended with polymer have been proposed as charge stor-
age materials for the development of non-volatile resistive
memory devices [2, 3]. However, it is still unsatisfactory
to meet the criteria for the data storage demand in mod-
ern electronics devices attributed to the costly manufactur-
ing processes, slower switching speed, and higher power
for switching as compared to its Si counterpart. Thus, the
development of high-performance NVM devices from the
improvement of nanomaterials as the charge storage medium
has gained increasing attention. Graphene is believed to be a
promising candidate for next-generation electronics and pho-
tonics devices applications due to its unique properties of the
planar structure, high electrical conductivity, high transpar-
ency and flexibility, large surface area, and high mechanical
* Poh Choon Ooi
pcooi@gmx.com
* M. F. Mohd. Razip Wee
m.farhanulhakim@ukm.edu.my
* Chang Fu Dee
cfdee@ukm.edu.my
1
Institute of Microengineering and Nanoelectronics,
Universiti Kebangsaan Malaysia, 43600 Bangi, Malaysia
2
International College of Semiconductor Technology, National
Chiao Tung University, University Road, Hsinchu 30010,
Taiwan, ROC
3
Advanced Devices Lab, MIMOS Berhad, Technology Park
Malaysia, 57000 Kuala Lumpur, Malaysia
4
Department of Electronics Engineering, National Chiao Tung
University, University Road, Hsinchu 30010, Taiwan, ROC
5
Department of Materials Science and Engineering, National
Chiao Tung University, University Road, Hsinchu 30010,
Taiwan, ROC

2. Journal of Materials Science: Materials in Electronics
1 3
stability [4]. Furthermore, compare with traditional NVM
devices, graphene has numerous advantages such as the
high density of states, high mobility, high work function,
and low dimensionality. Hence, graphene has been studied
extensively towards the development of NVM devices as a
charge trap medium [5].
Semiconductor quantum dots such as nanometer-sized
graphene is believed to be a promising candidate for the
next-generation electronics and photonics devices applica-
tions due to its numerous advantages such as the high den-
sity of states, high mobility, high work function, and low
dimensionality [6]. The nanometer-sized graphene, gra-
phene quantum dots (GQDs) will be used as charge trap
material in this study because it provided the advantage of
constricting the lateral charge movement as a result of the
nanocrystals are separated from each other. The separation
of nanocrystals is important to prevent stored charges leak
through the dielectric defects and hence longer data retention
time [3]. To constrain the movement of stored charges in the
trap sites, GQDs will be embedded in between the graphene
oxide (GO) insulator layers during the device fabrication.
Apart from its advantages of large surface area and trans-
parency, GO as a resistive layer has been reported to be a
good insulator barrier at maintaining high and low resistive
states for many stress cycles attributed to its flexibility and
mechanical stability [7] as compared to the typical thin insu-
lating metal oxide layer, for instance aluminum oxide [8],
titanium dioxide [9], and nickel(II) oxide [10]. These metal
oxide materials are usually being used as a resistive layer
and have some critical demerits material properties espe-
cially low mechanical flexibility and less transparent [11].
Even though the similar carbon-based NVM device struc-
ture had been reported by Ooi et al. [11], however, they had
fabricated write-once-read-many devices for very limited
applications. Therefore, we propose to further modify their
reported device design so that the device can be programmed
and erased for multiple times resemble flash memory behav-
iour. The carbon-based device will be fabricated by sim-
ple solution-processed route particularly spray-coating and
spin-coating.
2 Experimental procedure
Figure 1a shows the modified carbon-based NVM device
in the structure of silver nanowires (AgNWs)/GO/GQDs/
GO/poly(3,4-ethylenedioxythiophene) polystyrene sulfonate
(PEDOT:PSS) on top of a 2.5 cm × 3.0 cm polyethylene tere-
phthalate (PET). The PET substrate was oxygen plasma-
treated at 15 W for 1 min prior to the deposition of 45 nm
PEDOT:PSS by using spin coating technique at 2000 rpm
in 60 s. Subsequently, a 120 µl methanol was dropped on
the deposited PEDOT:PSS layer immediately after the spin
coating process and annealed at 70 °C for 20 min to improve
the conductivity performance by eliminating the hydrophilic
insulator PSS from the coated layer [12].
Next, 1 ml of both as purchased GQD and GO solutions
from ACS Nano were diluted with 4 ml of ethanol separately
in two different vials to achieve the same 0.2 mg/ml concen-
tration. Both solutions were agitated for 15 min to ensure
the homogenous distribution of the nanoparticles in ethanol
solution. Then, the spray-coating deposition was carried out
to deposit the stacking layer of GO/GQDs/GO on top of
PEDOT:PPS layer. The deposition process was conducted on
the 100 °C hot plate at 0.1 MPa with a fixed 15 cm distance
between the tip of the nozzle and the substrate. A 2 ml of
GO solution was spray-coated to form the 100 nm GO layer
adjacent to PEDOT:PSS, followed by 2 ml of GQDs solu-
tion to form the charge trap layer. Afterward, 3 ml of GO
solution was used to form 140 nm GO layer on top of the
GQDs layer. It is worth to mention that the reference device
without GQDs was also fabricated. Finally, the solution of
AgNWs that purchased from ACS Nano was spray-coated
to form 0.5 mm circular electrodes at the same pressure and
temperature on the hot plate. Figure 1b shows the scanning
electron microscope (SEM) image of the multi-stacked layer
of the fabricated device.
A field-emission scanning electron microscopy (FESEM,
SU8030, HITACHI) was used to investigate the cross-sec-
tional structure of the fabricated devices. An atomic force
Fig. 1 a Schematic diagram and b SEM cross-sectional image for the
fabricated NVM devices

3. Journal of Materials Science: Materials in Electronics
1 3
microscopy (AFM, NX-10, Park Systems) in non-contact
mode was used to evaluate the thickness of the device and
the surface morphology of GO and GQD layers. The cur-
rent–voltage (I–V) profile of the NVM devices was meas-
ured by Keithley 4200-SCS semiconductor characterization
system. All the bias voltages were applied on top of the
AgNWs electrode with respect to the PEDOT:PSS electrode
for all measurements.
3 Results and discussion
The surface morphologies for each coating layer were inves-
tigated by performing AFM. Figure 2a shows the typical
AFM image of the first-layer GO film with an estimated
thickness of 100 nm on the PEDOT:PSS/PET substrate.
The formation of non-aligned short wrinkles on GO was
observed after the first coating process as it is a common
effect as reported using Langmuir–Blodgett, CVD, and
other methods [13, 14]. Noted that it is nearly impossible
to eliminate the effect the wrinkles due to the consequence
of the physical interaction between the overlapping GO
flakes [15]. However, the effect of the wrinkles in this work
was minimized by our coating method with a root-mean-
square (rms) roughness of about ~ 0.1 nm, suggesting a
very smooth surface of GO (see Fig. 2d). After the second
coating process with GQDs on the GO film, the resultant
surface became much coarser where the GQDs were iso-
lated on the GO film in the form of clumping structures, as
shown in Fig. 2b. Here, the thick topographic of GQDs up
to ~ 500 nm was observed from its corresponding height
profile of the AFM image (see Fig. 2e), hence contributing
to higher rms roughness of about ~ 22.0 nm. The observa-
tion suggests that these structures are possibly attributed to
the agglomeration effect as the GQDs are prone to clump
together after drying at 100 °C. Figure 2c shows the GO
film with an estimated thickness of 140 nm on the surface
of GQDs/GO after the third coating process. From its cor-
responding height profile of the AFM image (see Fig. 2f),
the GO film exhibited a much smoother surface with less
particulate structures compared to the GQDs. As a conse-
quence, the rms roughness of the GO film is expected to
decrease to ~ 11.6 nm. Overall, the smooth surface of the
GO/GQDs/GO film in this work was obtained in order to
Fig. 2 AFM images of a first-layer 100 nm thick GO film on
PEDOT:PSS/PET substrate, b second-layer GQDs on GO/
PEDOT:PSS/PET substrate and c third-layer 140 nm thick GO film
on GQDs/GO/PEDOT:PSS/PET substrate by spray-coating method.
d–f Their corresponding height profile plots along the selected white
line as illustrated in a–c

4. Journal of Materials Science: Materials in Electronics
1 3
serve as good contact with the AgNWs electrode for the
NVM device characterization. We deliberately designed a
100 nm GO layer adjacent to PEDOT:PSS bottom conduc-
tive layer to ensure optimum electrons injection from the
higher work function of PEDOT:PSS as compared to the
lower work function of top electrode AgNWs. Meanwhile,
the 140 nm GO layer adjacent to AgNWs is to ensure longer
retention for trapped charges in the GQDs site.
Figure 3a shows the semi-log scale I–V plot for the fab-
ricated NVM device. Whereas, the inset in Fig. 3a shows
the electrical measurement was performed to investigate
the electrical behaviour of the NVM devices. The voltage
was applied from − 1.8 to 1.5 V and vice versa. Notice that,
in Fig. 3b, there is no significant hysteresis window that
can be observed for the devices without the presence of
GQDs when the voltage was swept. Thus, the large hys-
teresis window observed in Fig. 3a is likely attributed to
the presence of GQDs in the NVM devices [3, 16]. The
curve fitting method was conducted in the different voltage
regions I, II and III as marked in Fig. 3a. It is found that
the conduction mechanisms through the device are in good
agreement as proposed by Ooi et al. [3]. As the thickness
of the GO layer adjacent to the bottom conductive elec-
trode is approximately 100 nm, hence it is thick enough to
avoid the quantum tunneling. Therefore, at the low voltage
in the region I, the abrupt increased of current at 0.52 V
can be explained by electrons injection from PEDOT:PSS
electrode due to the thinner GO layer. The electrons are
transported to the conductive polymer–insulator interface
via the two-step process, i.e. Schottky emission (SE) fol-
lowed by Poole–Frenkel (PF) emission to reach the trapped
sites [3]. When the swept voltage reached 0.52 V, with the
measured slope value of approximately 84.0, suggesting that
the transport mechanism is switched to follow the trapped
charge-limited current (TCLC) model [17] in region II. In
this region, the GQDs trap sites start to fill up with electrons
and cause a sudden increase in current as shown in Fig. 3a.
Once all the trap sites are filled through TCLC conduction,
(a) (b)
(c)
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
II
III
Current
(A)
Voltage (V)
I
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
Current
(A)
Voltage (V)
GQDs
140
nm
PVDF
PEDOT: PSS
AgNWs
e e
e
e
e
e
e e
e e
e
100
nm
PVDF
e
e
V0
SE
PF
TCLC
Fig. 3 a Semi-log plot of I–V characterization for the NVM device.
The inset shows the fabricated device during the electrical measure-
ment. b Reference sample shows the negligible hysteresis memory
window. c Energy band diagram to illustrate the various possible con-
duction mechanisms through the NVM device

5. Journal of Materials Science: Materials in Electronics
1 3
the transport mechanism switched to obey ohmic conduc-
tion due to a unity slope of approximately 1.1 as shown in
region III. This observation could be associated with the
formation of Ag filaments. AgNWs in the top electrodes can
be oxidized and in turn driven into the graphene oxide layer,
forming conducting filaments that are responsible for subse-
quent resistive switching [17]. Figure 3c depicts the energy
band diagram to describe the charges trapping process in
the GQDs via possible conduction mechanisms through the
dielectric layers.
One of the crucial examinations to test the reliability
of NVM devices is to conduct endurance test by switch-
ing between ON- or OFF-test in the sequence of “write-
read-erase-read” as shown in Fig. 4, which describe the
switching characteristics. As can be seen in Fig. 4a, to
program the fabricated devices, an arbitrarily large posi-
tive voltage (≫ VON) is applied at the AgNWs electrode. A
+ 1.5 V pulse is applied to the AgNWs electrode to inject
electrons from the PEDOT:PSS into the GQDs and hence
programmed the device. Likewise, as shown in Fig. 4a,
to erase the device, an arbitrarily large negative pulse of
− 1.8 V is applied at the AgNWs electrode in an attempt
to attract the trapped electrons in the GQDs return to the
PEDOT:PSS. The ON and OFF state of the device is read
at + 0.15 V applied at the AgNWs electrode as shown in
Fig. 4a. The obtained switching endurance test behaviour
has been plotted in Fig. 4b for 240 ms. The switching per-
formance of the device resembles to flash memory behav-
iour because it can be programmed and erased multiple
times. Next, retention test measurements were also carried
out to examine the performance of the fabricated NVM
devices under stress at ambient conditions. A + 1.5 V bias
was applied to the top AgNWs electrode to ensure that
the device switched to the ON state. Whereas, a − 1.8 V
bias was applied to the top AgNWs electrode to switch
the device to OFF state. A read voltage at + 0.15 V was
applied to observe the stability of the device at ON and
OFF current state, respectively for 1 × 104
s. Figure 5
shows that the device is stable without any degradation
for times up to 1 × 104
s with a distinct ON/OFF ratio of
­105
. The promising high distinct ON/OFF ratio might be
associated with the high number of trapping sites formed
by edge defect states in GQDs. In addition, GQDs is a
zero band-gap semiconductor with ignorable quantum-size
effects. Therefore, its high work function and small Bohr
radius of GQD make it a favorable charge trapping mate-
rial [18].
(a)
0 50 100 150 200 250
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
Erase
Read
)
V
(
e
g
a
t
l
o
V
Time (ms)
Write
0 50 100 150 200 250
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
Read
Erase
)
A
(
t
n
e
r
r
u
C
Time (ms)
Write
Read
(b)
Fig. 4 “ON”/“OFF” endurance cycle test of the NVM device
0.0 2.0x10
3
4.0x10
3
6.0x10
3
8.0x10
3
1.0x10
4
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
Current
(A)
Time (s)
OFF
ON
ION /IOFF~105
Fig. 5 Recorded retention stability test of the fabricated NVM
devices at ambient conditions

6. Journal of Materials Science: Materials in Electronics
1 3
4 Conclusion
In conclusion, the AgNWs/GO/GQDs/GO/PEDOT:PSS
stacked layers were deposited on a PET substrate by spray-
coating and spin-coating methods. The overall smooth sur-
face morphology of the GO/GQDs/GO film serves a good
contact with the AgNWs electrode for the NVM device
characterization. The I–V characterization of the fabricated
NVM devices shows the bistable current states with a large
hysteresis window with a distinct ON/OFF ratio of ­
105
and
stable up to 1 × 104
s. Various conduction mechanisms
through the dielectric layers have been proposed. The fabri-
cated NVM device shows similar behavior as flash memory.
Therefore, the modified stacking structure could be exploited
for next-generation rewritable carbon-based flash memory
device.
Acknowledgements This study was financially supported by the
Research University Grant from Universiti Kebangsaan Malaysia
(GUP-2018-085), LRGS/NANOMITE/UKM-UKM/04/01 from
the Ministry of Education Malaysia, and “Center for the Semiconduc-
tor Technology Research” from The Featured Areas Research Center
Program within the framework of the Higher Education Sprout Project
by the Ministry of Education (MOE) in Taiwan. This work also sup-
ported in part by the Ministry of Science and Technology, Taiwan,
under Grant MOST-108-3017-F-009-003. We would also like to fur-
ther extend our gratitude to Skim Zamalah Penyelidik Tersorhor from
Pusat Pengurusan Penyelidikan dan Instrumentasi (CRIM), Universiti
Kebangsaan Malaysia.
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