ECET4730_Project_Final_Report

Heart Monitoring System
Sharif Kazwah
Veronica Nelson
Charles Lowd
Rahu Bannister
Sami Itum
Allan Waters
ARTIX-
7
BASYS 3
DIGILENT
XILINX
ECET 4730, VHDL & Field Programmable Gate Arrays
Section 01
Fall 2015
Professor, Scott Tippens
Department of Electrical and Computer Engineering Technology
Submitted
December 7, 2015

Page | 1
Table of Contents
Table of Contents.......................................................................................................................... 1
Executive Summary...................................................................................................................... 2
1. Introduction ........................................................................................................................... 3
1.1 Objective........................................................................................................................... 3
1.2 Background ...................................................................................................................... 3
2. Project Description and Goals.............................................................................................. 4
2.1 Market .............................................................................................................................. 4
2.2 Characteristics ................................................................................................................. 4
2.3 Implementation................................................................................................................. 5
3. Technical Specifications.....................................................................................................5-6
3.1 Operational ...................................................................................................................... 6
3.2 Performance..................................................................................................................... 7
3.2.1 Heart Rate..............................................................................................................7-8
3.2.2 Temperature.............................................................................................................. 9
3.2.3 LCD screen ............................................................................................................. 10
3.3 Interface ....................................................................................................................10-11
3.4 Physical.......................................................................................................................... 11
4. Design Approach and Details ............................................................................................. 12
4.1 Design Approach.......................................................................................................12-13
4.1.1 Beats Per Minute..................................................................................................... 14
4.1.2 Dallas 1-Wire.....................................................................................................15-16
4.1.3 Transmission of data to LCD screen .................................................................17-18
4.2 Codes and Standards...................................................................................................... 18
4.3 Constraints, Alternatives, and Tradeoff......................................................................... 19
5. Schedules, Tasks, and Milestones....................................................................................... 20
6. Project Demonstration ........................................................................................................ 21
7. Marketing and Cost Analysis ............................................................................................. 21
7.1 Marketing ....................................................................................................................... 21
7.2 Cost Analysis.................................................................................................................. 21
8. Summary .............................................................................................................................. 22
9. References............................................................................................................................. 22

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Appendix A (Top Level Design) ................................................................................................ 23
Appendix B.1 (Heart Monitor – State Machine_Proposed).................................................... 24
Appendix B.2 (Heart Monitor – Block Diagram_Proposed) .................................................. 25
Appendix B.3 (Heart Monitor – Sub-Block Diagram_Proposed) .......................................... 26
Appendix C (Temperature – Block Diagram_Proposed)........................................................ 27
Appendix D (LCD – Block Diagram_Proposed)...................................................................... 28
Appendix E (Heart Monitor – Block Diagram_Achieved)...................................................... 29
Appendix F (Temperature – Block Diagram_Achieved) ........................................................ 30
Appendix G (Wiring Diagram).................................................................................................. 31
Appendix H (Schematic)............................................................................................................. 32
Appendix I (Heart Monitor – VHDL Code)........................................................................33-38
Appendix J (Temperature – VHDL Code)..........................................................................39-56
Appendix K (LCD screen – VHDL Code) ...........................................................................57-60

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Executive Summary
The knowledge of one’s health in contemporary society is a fundamental part of life. With the
advent of a biomedical instrument people are able to access the essentials of their body’s health
through the touch of their finger. This system measures various parameters such as: beats per
minute from a heart pulse and body temperature. The Basys 3 FPGA collects data from the
parameters and is displayed on an LCD screen. Other than its portability, a major advantage from
this embedded system is that an individual can have the compatibility of multiple variables. These
variables can be extenuated from checking the current heart rate of an individual to a target heart
rate they wish to achieve. The temperature can range from lowest temperature possible to
maximum temperature whether in Celsius or Fahrenheit. The creation of a biomedical instrument
is to innovate what biomedical engineers are studying. It allows people minimal room for
predictions as its purpose is served to measure intensive health in advance.

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1. Introduction
1.1 Objective
The objective of this project is to design and build a heart monitor system prototype which will
allow the user to safely monitor their heart rate during physical activities. While the system
measures beats per minute for the heart, body temperature is also displayed to ensure safety for
the user.
1.2 Background
According to research a high percentage of top health problems are caused by unhealthy lifestyle
being either high stress, lack of exercise, or combination of several factors. Unfortunately, up to
this point there has been limited technology to assist individuals in measuring real time heart rate.
Thus, we have designed an apparatus to assist individuals in making a lifestyle change.
The heart rate monitor will display real time heart rate, temperature rate, and alert system. The
real time heart rate monitor displays the individuals current heart rate. In addition, it alerts the
individual if the heart rate exceeds a predefined safe zone they must change their current state to
decrease their activity. There is also a temperature sensor that measures the individuals body
temperature. If the body exceeds a predefined body temperature an alert will be sent to the display.

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2. Project Description and Goals
In general, this apparatus is used in monitoring an individual’s heart rate and body temperature.
There are two sensors which are worn by the individual and the sensors send a signal to a remote
LCD interface. There were a number of goals that were addressed prior to design of this system
which would be achieved. As discussed previously, the heart monitor’s objective is to provide the
user with a current heart rate, target heart rate and a temperature sensor to understand the
temperature of the body. This is important because it delivers feedback for the user their current
cardio health and ensures safety if physical activity were to occur. The LCD screen was included
to display the health parameters proposed in the design. However, it will be interfaced with the
design to exhibit how it should be implemented if configured appropriately.
2.1 Market
The global market for mobile health care is drastically increasing due to advancement in technology; in
addition, the rise of awareness in lifestyle choices. It is estimated the wearable fitness will exceed $1.15
billion in 2014, up 35 percent from 2013. The target market is predominantly male (60 percent) with 56
percent being under the age of thirty-four earning less than $50,000 a year. With the changes in our current
health care and the support of insurance companies the market share is expected to expand to 80% of the
population in the next five years.
2.2 Characteristics
The focus of the heart rate monitor is to measure the BPM then send an alert if the BPM is entering
a danger zone or if the BPM is not meeting expectations. The BPM measurement is obtained every
three seconds then a message is sent to the display with the results.

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2.3 Implementation
The concluding implementation was able to acquire the essential goals specified. However, some
of the technical details of the subsystem were not reached due to a number of reasons. One goal
that was not implemented in the final design is passing the heart rate and temperature sensor to the
LCD screen. This was not accomplished due to the complexity of the LCD screen interface with
the FPGA. Instead the parameters of the system were exhibited on the seven-segment display
which is embedded onto the Basys 3 board.
3. Technical Specifications
Following the project description and the goals discussed in the previous section, technical
specifications were developed to provide explicit details of the complete system. These
specifications defined the methodized parameters for the project to be cost-efficient, easy to use,
and consistent.
Shown on the next page in Table 1, the technical specifications are distributed into four main
categories: Operational, Performance, Interface and Physical. These specifications were addressed
briefly in the preliminary design as to how the system should be employed and also the objectives
it shall accomplish.

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3.1 Operational
This apparatus for monitoring an individual’s BPM and temperature includes two sensors and an
LCD display. The heart rate sensor has a wearable device which sends a wireless signal to the
receiver. The receiver is directly connected to the Basys 3. Then Basys 3 deciphers the data the
transmits the data to the LCD. The LCD displays the current BPM and the target BPM. Once, the
target BPM is reached an alert is sent to the LCD notifying the individual goal has been reached.
If the user exceeds or drops below a set BPM then a message is also sent alerting the user of BPM
status. As far as the temperature sensor, the sensor can measure the room temperature or the
individual’s temperature. The sensor has a stainless steel tube; the stainless steel allows for
measurements to be taken in wet or dry conditions. The system is also equipped with a system
reset. The system reset will erase all data so fresh measurements can be taken.
Proposed Specs Achieved Specs Description
Operational
Power Management From Basys 3 From Basys 3 Source of voltage
System Reset Push button Push button System Reset functionality
Performance
Heart Rate BPM Curr_BPM Range of BPM
Temperature andC F  Binary value Range of temperature
LCD screen SPI Transfer SPI Register Data on LCD screen
Interface
FPGA to LCD SPI 7-segment Display interface of system
Physical
Standalone Breadboard Breadboard Physical design of system
Table 1. Technical Specifications for the Heart Monitoring System

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3.2 Performance
As with any device maximum performance to be achieved is listed in Table 1. Initially each sensor
was tested individually to ensure quality and leave no room for error. However, for the goals of
this design and the end results should be viewed on the LCD and the seven-segment display but
only one feature was accomplished. The data displayed achieved the majority of the specifications
defined in the project which was suitable for final implementation.
3.2.1 Heart Rate
The performance of the heart rate sensor was not too difficult to experiment. Due to countless
issues that occurred during the testing phase, the heart rate was not successful of being displayed
on the LCD screen. Though it is unfortunate and that it did not appear on the LCD screen, it does
appear on the seven-segment displays. The heart rate design of the system can be understood by
the following state machine shown on the next page in Figure 1. The system is designed assuming
that the individual using this instrument is seeking to engage in physical activity. If this is the case,
then the user’s state would be ‘RUN’. If the user has reached a state where the current heart rate
(Curr_BPM) exceeds their target heart rate (Targ_BPM), then the user should slow down and
‘WALK’. And finally if the user attains the target heart rate as their current heart rate, the user
should ‘STOP’. If any problems or issues were to occur during this process, the user will have
accessibility reset the system to certify that no damage is done to the instrument nor the user. In
the software architecture, a state machine process was not necessary since the FPGA would only
show and update the BPM frequency every three seconds.

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RUN STOPWALK
Curr_BPM = Targ_BPM + 1 Curr_BPM = Targ_BPM
Curr_BPM < Targ_BPM
SysReset
Displayed below in Figures 2,3 and 4 are the various beats per minute which was updated every
three seconds to interpret the next beat. Before incorporating the heart rate sensor with the FPGA
this was tested using a switch from the Basys 3. Once this design was complete and the hardware
descriptions were defined, the sensor was then included and sure enough it performed precisely.
Figure 1. State Machine of Heart Rate
Figure 2. 84 BPM Figure 3. 99 BPM Figure 4. 76 BPM

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Figure 5. DS18B20 implementation with LED
3.2.2 Temperature
The temperature group used the 1-Wire digital waterproof DS18B20 temperature sensor whose
wire is further divided into a blue ground wire, yellow signal wire, and red 3.33V – 5V power
wire. The sensor provides a 9 to 12-bit (configurable) temperature reading that ranges from
55 to 122C C   . The bit commands that were sent to the sensor were able to initialize the sensor,
then write to obtain a recording, and finally read that recording and finally clear the sensor to repeat
the process again. Shown below in Figure 5 is the temperature sensor operating and updating the
signal received on the LED for a time-slot of 60us. It cannot be clearly seen the LED updating in
the figure, however, in implementation the LED updated constantly.

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3.2.3 LCD screen
The output of the FPGA drives the SPI interface with three signals. The three signals clock the
data to be stored in the SPI register. Once the latch signal has a rising edge, the asserted data is
seen on the output of the SPI module and input to the LCD. The inputs to the SPI module consist
of SCLK, DAT, and LAT. These are signals sent out by the Basys 3 to control the output to the
LCD.
The SPI Signals:
 SCLK - asserts data when SPI module receives a rising edge from this signal
 DAT - signal applied to the register when the SPI clock goes high
 LAT - latches the last 8 bits applied to the SPI register
The order in which the data is sent to the SPI module is:
1. LAT signal is set low.
2. Create a rising edge on the SCLK line.
3. Assert the value of DAT into the SPI register
4. After the 8th bit has been sent, bring the LAT signal high.
3.3 Interface
The interface of the FPGA and the LCD seemed very simple. Interface to the LCD was
implemented with an SPI (Serial Peripheral Interface). An SPI is useful because it only requires
three signal wires to control the LCD. If we were to directly connect the FPGA to drive the LCD,
we would need at least 4 data lines and 3 control lines. Using the SPI interface saves four extra
Basys 3 outputs. This would allow a total number of three I/O ports from the Basys3 board.

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The LCD itself did not have an SPI input, so an SPI backpack from www.adafruit.com was used.
Adafruit’s product has code available for controlling the backpack in C, but not in VHDL, so the
code needed to be created to interface the two. However, after encountering numerous issues and
constraints, the LCD interface was not a priority as much as finding an alternative to display
anything. The selected alternative to display data obtained was on the seven-segment display
which is already integrated with the FPGA. Presented below in Figure 6 is an overview of the
entire project.
3.4 Physical
In the planning phase of the design, it was proposed that the system should not be extravagant and
only be connected to a breadboard if necessary. Two factors prevented this from happening and
one of them was cost and the other was time. Cost was beginning to escalate after the purchase of
the sensors and the LCD screen. Time was another issue because it was too valuable for time to be
consumed on physical design rather than software design. Nonetheless, it was not required that the
system need a complete assembled physical prototype to prove the concept of how the heart
monitoring system operates.
Figure 6. Overview of Heart Monitoring System (Achieved)

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4. Design Approach and Details
The system had three main subsystems:
 Beats Per Minute
 Dallas 1-Wire
 Transmission of data to LCD screen
4.1 Design Approach
Both subsystems work mutually to permit data that is received to the FPGA is delivered to the
LCD for display. There are two methods implemented to obtain this data for each sensor. The first
method is the data determination for the temperature sensor. The DS18B20 uses the Dallas 1-Wire
protocol which consists of lower data rates and a wider range. Another important yet a little
complex method was the Data Control for the system. This block of the design comprises of the
all the data that should be received from the temperature sensor and the heart rate sensor which
then follows another protocol to transmit the data to the LCD screen. The transmission of the data
to the LCD screen corresponds with the Serial Peripheral Interface (SPI) procedure. Basically the
SPI interface has a Serial Clock, MOSI, for (“Master Out / Slave In”) and MISO, for (“Master In
/ Slave Out”). When data is transferred from the master to a slave, the data is sent to MOSI If the
slave must refer back to the master, the master will remain to produce a predetermined number of
clock cycles, and the slave will place the data onto a third data line called MISO [1]. This portion
of the experiment was the most challenging because it is the foundation of the whole system.
Problems were developing in the design phase due to lack of research. Some alternatives were
being discovered to seek solution, but not everything came together.

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In Figure 7 shown below the block diagram of the Top Level Design including all the main
components interfaced with each subsystem. This diagram is a revision of the block diagram that
was proposed in the preliminary design. The Top Level Design is the main outline of the project
because this is where the planning phase of the project initiated. The fundamentals of designing a
system in a project is essential. Without a top-level architecture, there would not be a path to follow
to begin the process of dividing the project into separate subsystems.
Temp Sensor
BMP Sensor
BMP
Temp
integer
integer
Data
Integrator
LCD
integer
Figure 7. Top Level Design (Block Diagram)

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4.1.1 Beats Per Minute
For this section of the design there were a few modifications as to how the structure of Beats Per
Minute should be accumulated. In the initial design of the preliminary phase, the Beats Per Minute
would be determined in reference to the first beat that is received. Every pulse after the first beat
will be compared with the next beat then summed with the first beat and divided by a half to
determine the target heart rate. Not only should it show target heart rate but also the current heart
rate. Shown below in Figure 8 is an example of what was proposed to be illustrated in the final
implementation.
However, this design was not executed in the implementation. Instead it will determine the number
of pulses received every three seconds (rather than every minute) and update the beat received
each time by a factor of 12. This will continue on until the user either shuts down the instrument
or interrupts the process by pushing the reset button on the FPGA. If this occurs, then system will
reset and repeat the process to wait for a signal to be received and then transmitted.
Figure 8. Determination of target heart rate

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4.1.2 Dallas 1-Wire
Since the DS18B20 is a digital sensor, communication to it proceeds by driving the signal wire
‘LOW’ or ‘HIGH’ for a specific period of time to let the system know either a ‘1’ or ‘0’ is being
sent [2]. First is the initialization process. With this the master being the Basys 3 controller sends
a low for a minimum of 480µs. When the DS18B20 detects the rising edge of the clock, it holds
for 15µs to 60µs and then transmits a presence pulse by pulling the 1-Wire bus ‘LOW’ for 60µs
to 240µs. The writing, reading, and convert commands function a little differently than the
initialization. Here there are specified write and read time slots that dictate what is sent to the
DS18B20. The total slot time is 60µs and by alternating the slot signal change from ‘LOW’ to
‘HIGH’ a ‘1’ or ‘0’ can be sent out. This was used to send the required hex commands to obtain
these readings.
The hex commands are as followed:
 44H – convert: This takes a reading.
 4EH- Write scratchpad: This writes our data to the sensor.
 BEH- Read scratchpad: This allows us to read data the sensor outputs.
Once data is read from the sensor it needs to be converted into a decimal number to display on the
seven-segment display of the controller. Shown on the next page in Figure 9 and Figure 10 is the
timing process for the DS18B20 when a signal is received and sent.

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Figure 9. Initialization Timing
Figure 10. Read/Write Time Slot Timing Diagram

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4.1.3 Transmission of data to LCD screen
The design for data control consists of several phases. To begin, you must have a power on phase
to allow the LCD display to have its voltage supply stabilized. After the voltage is stable the LCD
requires a sequence of command bytes to initialize the LCD to a 4-Bit Interface. After initialization
phase it goes into a ‘READY’ state where it now can send commands to write characters to the
LCD. Once it is in a ‘READY’ state it will now read inputs from various sensors and push those
characters out to the LCD along with positioning of those characters. Displayed in Figure 11 is the
process for the 4-Bit Interface implemented for the LCD screen.
LCD_DataControl
Power On
LCD_DataControl
Initialization
LCD_DataControl
Ready
LCD_DataControl
DataOut
Wait 50ms
When Initialization Complete
If DataEn = Begin
DataOut
Transfer = Complete
The SPI interface for the LCD module only allows for the 4-bit operation of the LCD. This is
because the SPI output is based on an 8-bit register. The 8-bit register has to include enough bits
to satisfy the LCD control signals RS, R/W, and EN. For the LCD to operate in 4-bit mode, the
SPI has to give an output for each instruction and latching command.
Figure 11. 4-Bit Interface

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Because the LCD will only receive instructions, the R/W signal will always stay LOW. The RS
signal is brought high when writing characters or commands to the LCD. It is low when the LCD
initializes with its first instructions.
4.2 Codes and Standards
Serial Peripheral Interface Bus (SPI) codes and standards are specified by IEEE 1149.1-2013 [3].
This standard is s synchronous serial communication interface used for short distance
communication, mainly embedded systems. The SPI was developed by Motorola which has
become standard. The SPI device communicates in full duplex mode using a master-slave
architecture with one master. The master device originates the frame for reading and writing. The
SPI may also be depicted as a synchronous serial interface with uses differential signaling with a
single simplex communication channel. To begin communication, the master configures the clock.
Then selects the slave device with logic level 0 on the select line. The clock cycle a full duplex
transmission occurs. The master sends one bit using a MOSI line and the slave reads it. This is
shown below in Figure 12.
Figure 12. SPI Protocol

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4.3 Constraints, Alternatives, and Tradeoffs
The major constraint during design and implementation of this project was integration. Integrating
all of the components and systems to work together. At the same time, prior to integration there
were other issues occurring throughout each component. For the heart rate module, the beats from
a heart pulse did not transmit accurately to the receiver. The pulse was either delayed or too fast
that the data became inconsistent. An alternative that was employed is if a pulse was received it
should have no interference with any other form of frequencies within its surroundings. This was
done by measuring the data in calm environments to ensure accuracy and precision. For the
temperature sensor, a substantial amount of time was lost trying to communicate with the sensor
due to the timing and specifics of the controller and the sensor itself. Multiple precise timing clocks
had to be developed for simple communication. Since the Basys 3 is a VHDL device it requires
the user to manually make and implement registers and sequences. This increases the number of
code lines substantially. Conversion also proved to be an extreme issue as well as finding the
proper information in the datasheets. For future implementation we highly recommend using a
non-VHDL controller. This allows for faster programming and integration.

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5. Schedules, Tasks, and Milestones
Referring to Table 2 is a list of tasks general tasks which are subdivided into more specific tasks.
Each task has a precise start and end date to ensure the project is completed. Unfortunately, not
everything was completed due to specific constraints stated previously.
Project Lead: Sharif Kazwah
Project Start Date: 11/2/2015 (Monday)
Display Week: Daily
WBS Task Lead
Prede
cessor Start End
Work
Days
Cal.
Days
%
Done
1 Project Planning
1.1 Spec Project
Wed
11/04/15
Wed
11/04/15 1 1 100%
1.2 Define Goals
Wed
11/04/15
Wed
11/04/15 1 1 100%
1.3 Order Parts
Wed
11/04/15
Wed
11/04/15 1 1 10%
2 Block Diagram
2.1 Design
Wed
11/04/15
Mon
11/09/15 2 6 100%
2.2 Integrate Blocks
Mon
11/09/15
Wed
11/11/15 2 3 100%
3 Programming
3.1 Temp. Sensor
Wed
11/11/15
Mon
11/16/15 2 6 90%
3.2 LCD
Wed
11/11/15
Mon
11/16/15 2 6 90%
3.3 Pulse Sensor
Wed
11/11/15
Mon
11/16/15 2 6 100%
4 Final Project
4.1 Integrate Program
Wed
11/18/15
Mon
11/30/15 5 13 0%
4.2 Write Report
Mon
11/30/15
Wed
12/02/15 3 3 100%
4.3 Update Report
Wed
12/02/15
Mon
12/07/15 2 4 100%
5 Final Demonstration
Demo
Mon
12/07/15
Mon
12/07/15 1 1 100%
Table 2. Project Schedule

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6. Project Demonstration
The final project demonstration was commenced by Professor Tippens. The implementation did
not completely succeed. The heart monitor was able to display various beats on the seven-segment
display when a pulse was obtained by someone wearing the wireless sensor. The temperature
sensor operated properly and sent a binary value to an LED. However, it did not display
temperature on the seven-segment display. Unfortunately, the LCD screen was able to initialized
and power on but did not accomplish to display any characters.
7. Marketing and Cost Analysis
7.1 Marketing
Due to the advances in technology and the want to live a healthy lifestyle our product will attract
most consumers. The device is low cost, plus, proved affected in monitoring the individuals BPM
and body temperature. The device can also be worn to check the heart rate without having to
participate in physical activities. As the apparatus progresses, other programming changes can be
made to improve the functionality of the device. So the success of the product will highly depend
on marketing which the focus should be in doctors’ offices and gyms.
7.2 Cost Analysis
Listed below in Table 3 is the total budget invested on the project. Of course cost will decrease if
the materials are ordered in a larger volume and ahead of time. Since time was a huge constraint,
the components were ordered immediately with expedited shipping.

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Materials Quantity Cost Vendor
Heart Rate Educational Starter Pack w/wireless sensors 1 $65.00 Adafruit
Waterproof Digital Sensor 1 $9.95 Adafruit
I2C/SPI Character LCD Backpack 1 $10.00 Adafruit
LCD 1 $23.95 Adafruit
Basys 3 1 $79.00 Digilent
TOTAL: $187.90
8. Summary
The final implementation of the system was unsuccessful. Though there were unfinished tasks in
the project, it was a positive and challenging experience.
9. References
[1] Learn.sparkfun.com, 'Serial Peripheral Interface (SPI) - learn.sparkfun.com', 2015. [Online]. Available:
https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi. [Accessed: 25- Nov- 2015].
[2] Maximintegrated.com, 'DS18B20 Programmable Resolution 1-Wire Digital Thermometer -
Maxim', 2015. [Online]. Available:
https://www.maximintegrated.com/en/products/analog/sensors-and-sensor-
interface/DS18B20.html. [Accessed: 04- Dec- 2015].
[3] 'IEEE Standard for Test Access Port and Boundary-Scan Architecture'., 2015 [Online].
Available: https://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6515989
Table 3. Project Budget

Temp Sensor
BMP Sensor
BMP
Temp
integer
integer
Data
Integrator
LCD
integer
Title: ECET4730_Project_Top_Level
Date: 12/7/2015 Revised: 12/7/2015
Professor: Tippens Engineer: Team Sharif
Kennesaw State University
ECET 4730 VHDL and Field Programmable Gate Arrays

RUN STOPWALK
Curr_BPM = Targ_BPM + 1 Curr_BPM = Targ_BPM
Curr_BPM < Targ_BPM
SysReset
Title: ECET4730_Project_HM_State_Machine
Date: 12/7/2015 Revised: 12/7/2015
Professor: S. Tippens
Engineer(s):
V. Nelson, S. Kazwah

SysReset
SysClock
Next_State Current_State Next_State
LCD
STATE_TRANSISTIONSTATE_RESGISTER
Title: ECET4730_Project_HM_Block_Diagram
Date: 12/7/2015 Revised: 12/7/2015
Engineer(s):
SysReset
SysReset
Curr_BPM
Targ_BPM
SysClock
Sync_Curr_BPM
Sync_Targ_BPM

SysReset
SysReset
SysReset
SysClock
SysClock
SysClock
WorkOut_Stop_BPM
WorkOut_BPM
Start_BPM
BPM
BPM
Targ_BPM (integer)
Curr_BPM (integer)
HeartMonitor
BPM
Title: ECET4730_Project_HM_Sub_Block
Date: 12/7/2015 Revised: 12/7/2015
Engineer(s):

SysReset
SysClock
CLOCK_DIVIDER
SysReset
SysClock
TEMPERATURE
Temp_Clock
Temp_Sensor
Temp_C (integer)
SysReset
SysClock
CONVERSION
Temp_F (integer)
Title: ECET4730_Project_Tempearture
Date: 12/7/2015 Revised: 12/7/2015
Engineer(s):
C. Lowd, R. Bannister

SysReset
SysClock
Data_Done Data_EN Data_Done
SPI_Data
SPI_TRANSFERDATA_CONTROL
Title: ECET4730_Project_LCD_Block_Diagram
Date: 12/7/2015 Revised: 12/7/2015
Engineer(s):
S. Itum, A. Waters
SPI_Clock
LCD_Data
SysReset
Temp
BPM

SysClock
btnD
SYSRESET_PROCESS
SysReset
pulse
SysReset
Heart_Rate
seven_seg_0
seven_seg_1
seg
an
8
8
4
8
BPM seg_select
SysClock
Heart_Rate
SysReset
BPM
100 2
BPM_PROCESS
HEART_MONITOR_PROCESS
SEVEN_SEG_CLOCK_PROCESS
SysClock
SysReset
SEG_SELECT_PROCESS
Title: ECET4730_Project_Heart_Monitor.vhd
Date: 12/7/2015 Revised: 12/7/2015
Engineer(s):

Anode_Select
P3 Anode_Selection
SevenSeg
an 4
8
P1 One_Second_Change
Phase_H
Phase_HE
Phase_HEL
Phase_HELL
Phase_ELLO
Phase_LLO
Phase_LO
Phase_O
Blank_Phase
Phase_B
Phase_BY
Phase_BYE
Phase_BYE1
Phase_YE
Phase_E
P2 7Seg Mux Clock
3
clk
2
Reset
Switch
clk
P5 Led Display
Reset
Counter
Switch
2
clk
0-11
P4 Led Display
Reset
clk
Led Output
Title: ECET4730_Project_Temp_Sub_Block
Date: 12/7/2015 Revised: 12/7/2015
Engineer(s):
C. Lowd, R. Bannister

ARTIX-7
BASYS 3
DIGILENT
XILINX
BPM
V+
GND
Signal
DS18B20
Title: ECET4730_Project_Wiring_Diagram
Date: 12/7/2015 Revision: 1.0
Professor: Tippens Engineer: S. Kazwah

1
1
2
2
3
3
4
4
D D
C C
B B
A A
1
2
3
4
5
6
7
8
9
10
11
12
Pmod 2x6
JBGND GND
VCC3V3
CA
11
CB
7
CC
4
CD
2
CE
1
CF
10
CG
5
DP
3
A1
12
A2
9
A3
8
A4
6
TOF-2481BE-N
KW4-281ASB
Q1A
2.2K
R_AN3
2.2K
R_AN2
2.2K
R_AN0
Q1B
Q2A
Q2B
2.2K
R_AN1
VCC3V3
AN3
AN2
AN1
AN0
100
R_CB
100
R_CC
100
R_CD
100
R_CE
100
R_CF
100
R_CA
100
R_CG
100
R_DP
CA
CB
CC
CD
CE
CF
CG
DP
200
R_JB3
200
R_JB4
200
R_JB2
200
R_JB1
200
R_JB8
200
R_JB9
200
R_JB10
200
R_JB7JB1
JB2
JB3
JB4
JB7
JB8
JB9
JB10
VDD
4 OUT
3
STBY
1 GND
2
SysClock
DSC1033CC1-100.0000T
VCC3V3
GND
100nF
C_CLK
SysClock
Signal
V+
GND
Polar Heart Rate Receiver
GND
VCC3V3
LD0
330
R_LEDled_pulse
pulse
VCC
Data
GND
Temperature Sensor
DS18B20
GND
VCC3V3
BTND
PTA-142
10K
R_btnD
VCC3V3
SysReset
GND
10K
R_btn
Title: ECET4730_Project_schematic.Sch.Dot
Date: Revision:
Engineer:
12/8/2015
S. Kazwah
2.0
Professor:S. Tippens

1 ----------------------------------------------------------------------------------
2 -- School: Kennesaw State University
3 -- Southern Polytechnic College of Engineering and Engineering Technology
4 -- Department: Electrical and Computer Engineering Technology
5 -- Course: ECET 4730 - VHDL and Field Programmable Gate Arrays
6 -- Professor: Scott Tippens
7 -- Engineer: Veronica Nelson & Sharif Kazwah
8 --
9 -- Create Date: 12/2/2015 03:06:47 PM
10 -- Design Name: Heart_Monitor
11 -- Module Name: Heart_Monitor.vhd
12 -- Project Name: Project B
13 -- Target Devices: Xilinx Artix-7™ FPGA (XC7A35T-1CPG236C) - Basys3
14 --
15 -- Description: Demonstrates a Heart Monitor logic design in VHDL. In this project,
16 -- the VHDL component is interfaced with a Heart Pulse Rate module
17 -- that receives a wireless signal from a Polar Wireless Sensor. The
18 -- signal that is received is sent to the FPGA, updates every 3 seconds
19 -- and displays the value of the heart rate on the 7-segment displays.
20 --
21 --
22 -- Dependencies: none
23 --
24 -- Revision: 1.1 (12/2/2015)
25 -- Additional Comments:
26 --
27 ----------------------------------------------------------------------------------
28
29
30 library IEEE ;
31 use IEEE .STD_LOGIC_1164 .ALL ;
32 use ieee .std_logic_unsigned .all ;
33 use ieee .numeric_std .ALL ;
34
35 -- Uncomment the following library declaration if using
36 -- arithmetic functions with Signed or Unsigned values
37 --use IEEE.NUMERIC_STD.ALL;
38
39 -- Uncomment the following library declaration if instantiating
40 -- any Xilinx leaf cells in this code.
41 --library UNISIM;
42 --use UNISIM.VComponents.all;
43
44 entity heart_monitor is
45 Port ( SysClock : in std_logic ; --synchronous system clock
46 btnD : in std_logic ;
47 pulse : in std_logic ; --JB1
48 JB2 : in std_logic ;
49 JB : out std_logic ;
50 led_pulse : out std_logic ;
51 an : out std_logic_vector (3 downto 0); --anodes
52 seg : out std_logic_vector (7 downto 0)); --segments
53 -- beat : out integer range 0 to 99);
54 end heart_monitor ;
55
56 architecture heart_monitor_ARCH of heart_monitor is
57
58 ----declaration of signals---------------------------------------SIGNALS
59 signal SysReset : std_logic ;
60 signal Heart_Rate : std_logic ;
61 signal seg_select : std_logic ;
62 signal seven_seg_0 : std_logic_vector (7 downto 0); --segment 0
63 signal seven_seg_1 : std_logic_vector (7 downto 0); --segment 1
64 signal BPM : integer range 0 to 99;
65
66 ----declaration of constants----------------------------------CONSTANTS
67 constant ACTIVE : std_logic := '0';
68 constant NOT_ACTIVE: std_logic := '1';
69
70 begin
71 led_pulse <= pulse ; --led blinks for every pulse received
72
73 ----------------------------------------------------------------------------------
74 --Process Name : SYSRESET_PROCESS
75 --Sensitivity List : btnD
76 --Signals Changed : SysReset
77 --Pins Used : none

78 --Description : This process assigns btnD to SysReset. The signal will be
79 -- 'ACTIVE' if button is pressed. When the button is released
80 -- the signal is 'NOT_ACTIVE'.
81 ----------------------------------------------------------------------------------
82 SYSRESET_PROCESS: process(btnD)
83 begin
84 if (btnD = '1') then
85 SysReset <= ACTIVE;
86 else
87 SysReset <= NOT_ACTIVE;
88 end if;
89 end process;
90
91 ----------------------------------------------------------------------------------
92 --Process Name : HEART_MONITOR_PROCESS
93 --Sensitivity List : SysClock, SysReset, pulse
94 --Signals Changed : Heart_Rate
96 --Description : This checks if a 'pulse' signal is received and assigns that
97 -- signal to 'Heart_Rate'. If a 'pulse' is received, the signal
98 -- for 'Heart_Rate' goes 'HIGH', otherwise the signal will stay
99 -- 'LOW'.
100 ----------------------------------------------------------------------------------
101 HEART_MONITOR_PROCESS: process(SysClock, SysReset, pulse)
102 begin
103 if (SysReset = ACTIVE) then
104 Heart_Rate <= '0';
105 elsif rising_edge(SysClock) then
106 if (pulse = '1') then
108 else
110 end if;
111 end if;
112 end process;
113
114 ----------------------------------------------------------------------------------
115 --Process Name : BPM_PROCESS
116 --Sensitivity List : SysClock, SysReset
117 --Signals Changed : BPM
119 --Description : This process includes the system clock divider and counts up
120 -- to three seconds before it changes values. It goes through a
121 -- look-up table and multiplies the pulse signal by 12 after
122 -- every three seconds the pulse updates.
123 ----------------------------------------------------------------------------------
124 BPM_PROCESS: process(SysClock, SysReset)
125 variable clk_divider : std_logic_vector(26 downto 0);
126 constant clk_divider_1Hz : std_logic_vector(26 downto 0) :=
"101111101011110000100000000"; --1Hz
127 variable seconds_range : integer range 0 to 10;
128 variable BPM_range : integer range 0 to 20;
129 variable BPM_reached : std_logic;
130 begin
132 clk_divider := (others => '0');
133 seconds_range := 0;
134 BPM_range := 0;
135 BPM_reached := NOT_ACTIVE;
136 BPM <= 0;
137 -- beat <= 0;
139 if (Heart_Rate = '1') then
140 if (BPM_reached = NOT_ACTIVE) then
141 BPM_range := BPM_range + 1;
142 BPM_reached := ACTIVE;
143 end if;
144 else
145 BPM_reached := NOT_ACTIVE;
146 end if;
147 clk_divider := clk_divider + 1;
148 if (clk_divider = clk_divider_1Hz) then
149 clk_divider := (others => '0');
150 seconds_range := seconds_range + 1;
151 if (seconds_range = 3) then
152 seconds_range := 0;
153 -- beat <= BPM_range * 12;

154 BPM <= (BPM_range + 1) * 12;
155 end if;
156 end if;
157 end if;
158 end process;
159
160 --look-up table for segment 1
161 with BPM select
162 seven_seg_1 <= "11000000" when 0, --0
163 "11000000" when 1, --1
164 "11000000" when 2, --2
165 "11000000" when 3, --3
166 "11000000" when 4, --4
167 "11000000" when 5, --5
168 "11000000" when 6, --6
169 "11000000" when 7, --7
170 "11000000" when 8, --8
171 "11000000" when 9, --9
172 "11111001" when 10, --10
173 "11111001" when 11, --11
174 "11111001" when 12, --12
175 "11111001" when 13, --13
176 "11111001" when 14, --14
177 "11111001" when 15, --15
178 "11111001" when 16, --16
179 "11111001" when 17, --17
180 "11111001" when 18, --18
181 "11111001" when 19, --19
182 "10100100" when 20, --20
183 "10100100" when 21, --21
184 "10100100" when 22, --22
185 "10100100" when 23, --23
186 "10100100" when 24, --24
187 "10100100" when 25, --25
188 "10100100" when 26, --26
189 "10100100" when 27, --27
190 "10100100" when 28, --28
191 "10100100" when 29, --29
192 "10110000" when 30, --30
193 "10110000" when 31, --31
194 "10110000" when 32, --32
195 "10110000" when 33, --33
196 "10110000" when 34, --34
197 "10110000" when 35, --35
198 "10110000" when 36, --36
199 "10110000" when 37, --37
200 "10110000" when 38, --38
201 "10110000" when 39, --39
202 "10011001" when 40, --40
203 "10011001" when 41, --41
204 "10011001" when 42, --42
205 "10011001" when 43, --43
206 "10011001" when 44, --44
207 "10011001" when 45, --45
208 "10011001" when 46, --46
209 "10011001" when 47, --47
210 "10011001" when 48, --48
211 "10011001" when 49, --49
212 "10010010" when 50, --50
213 "10010010" when 51, --51
214 "10010010" when 52, --52
215 "10010010" when 53, --53
216 "10010010" when 54, --54
217 "10010010" when 55, --55
218 "10010010" when 56, --56
219 "10010010" when 57, --57
220 "10010010" when 58, --58
221 "10010010" when 59, --59
222 "10000010" when 60, --60
223 "10000010" when 61, --61
224 "10000010" when 62, --62
225 "10000010" when 63, --63
226 "10000010" when 64, --64
227 "10000010" when 65, --65
228 "10000010" when 66, --66
229 "10000010" when 67, --67
230 "10000010" when 68, --68

231 "10000010" when 69, --69
232 "11111000" when 70, --70
233 "11111000" when 71, --71
234 "11111000" when 72, --72
235 "11111000" when 73, --73
236 "11111000" when 74, --74
237 "11111000" when 75, --75
238 "11111000" when 76, --76
239 "11111000" when 77, --77
240 "11111000" when 78, --78
241 "11111000" when 79, --79
242 "10000000" when 80, --80
243 "10000000" when 81, --81
244 "10000000" when 82, --82
245 "10000000" when 83, --83
246 "10000000" when 84, --84
247 "10000000" when 85, --85
248 "10000000" when 86, --86
249 "10000000" when 87, --87
250 "10000000" when 88, --88
251 "10000000" when 89, --89
252 "10011000" when 90, --90
253 "10011000" when 91, --91
254 "10011000" when 92, --92
255 "10011000" when 93, --93
256 "10011000" when 94, --94
257 "10011000" when 95, --95
258 "10011000" when 96, --96
259 "10011000" when 97, --97
260 "10011000" when 98, --98
261 "10011000" when others; --99
262
263 --look-up table for segment 0
264 with BPM select
265 seven_seg_0 <= "11000000" when 0, --0
266 "11111001" when 1, --1
267 "10100100" when 2, --2
268 "10110000" when 3, --3
269 "10011001" when 4, --4
270 "10010010" when 5, --5
271 "10000010" when 6, --6
272 "11111000" when 7, --7
273 "10000000" when 8, --8
274 "10011000" when 9, --9
275 "11000000" when 10, --10
276 "11111001" when 11, --11
277 "10100100" when 12, --12
278 "10110000" when 13, --13
279 "10011001" when 14, --14
280 "10010010" when 15, --15
281 "10000010" when 16, --16
282 "11111000" when 17, --17
283 "10000000" when 18, --18
284 "10011000" when 19, --19
285 "11000000" when 20, --20
286 "11111001" when 21, --21
287 "10100100" when 22, --22
288 "10110000" when 23, --23
289 "10011001" when 24, --24
290 "10010010" when 25, --25
291 "10000010" when 26, --26
292 "11111000" when 27, --27
293 "10000000" when 28, --28
294 "10011000" when 29, --29
295 "11000000" when 30, --30
296 "11111001" when 31, --31
297 "10100100" when 32, --32
298 "10110000" when 33, --33
299 "10011001" when 34, --34
300 "10010010" when 35, --35
301 "10000010" when 36, --36
302 "11111000" when 37, --37
303 "10000000" when 38, --38
304 "10011000" when 39, --39
305 "11000000" when 40, --40
306 "11111001" when 41, --41
307 "10100100" when 42, --42

308 "10110000" when 43, --43
309 "10011001" when 44, --44
310 "10010010" when 45, --45
311 "10000010" when 46, --46
312 "11111000" when 47, --47
313 "10000000" when 48, --48
314 "10011000" when 49, --49
315 "11000000" when 50, --50
316 "11111001" when 51, --51
317 "10100100" when 52, --52
318 "10110000" when 53, --53
319 "10011001" when 54, --54
320 "10010010" when 55, --55
321 "10000010" when 56, --56
322 "11111000" when 57, --57
323 "10000000" when 58, --58
324 "10011000" when 59, --59
325 "11000000" when 60, --60
326 "11111001" when 61, --61
327 "10100100" when 62, --62
328 "10110000" when 63, --63
329 "10011001" when 64, --64
330 "10010010" when 65, --65
331 "10000010" when 66, --66
332 "11111000" when 67, --67
333 "10000000" when 68, --68
334 "10011000" when 69, --69
335 "11000000" when 70, --70
336 "11111001" when 71, --71
337 "10100100" when 72, --72
338 "10110000" when 73, --73
339 "10011001" when 74, --74
340 "10010010" when 75, --75
341 "10000010" when 76, --76
342 "11111000" when 77, --77
343 "10000000" when 78, --78
344 "10011000" when 79, --79
345 "11000000" when 80, --80
346 "11111001" when 81, --81
347 "10100100" when 82, --82
348 "10110000" when 83, --83
349 "10011001" when 84, --84
350 "10010010" when 85, --85
351 "10000010" when 86, --86
352 "11111000" when 87, --87
353 "10000000" when 88, --88
354 "10011000" when 89, --89
355 "11000000" when 90, --90
356 "11111001" when 91, --91
357 "10100100" when 92, --92
358 "10110000" when 93, --93
359 "10011001" when 94, --94
360 "10010010" when 95, --95
361 "10000010" when 96, --96
362 "11111000" when 97, --97
363 "10000000" when 98, --98
364 "10011000" when others; --99
365
366 ----------------------------------------------------------------------------------
367 --Process Name : SEVEN_SEG_CLOCK_PROCESS
369 --Signals Changed : seg_select
371 --Description : This process creates the multiplexer to select which digit
372 -- will be active on the 7-segment display. The clock is divided
373 -- from 100MHz to 500Hz
374 ----------------------------------------------------------------------------------
375 SEVEN_SEG_CLOCK_PROCESS : process(SysClock, SysReset)
376 variable seg_counter : std_logic_vector (18 downto 0);
377 constant seg_prescaler : std_logic_vector (18 downto 0) :="1111010000100100000";
--500Hz
378 begin
380 seg_counter := (others => '0');
381 seg_select <= '0';
383 seg_counter := seg_counter + 1;

384 if (seg_counter = seg_prescaler) then
385 seg_select <= not(seg_select);
386 seg_counter := (others => '0');
387 end if;
388 end if;
389 end process;
390
391 ----------------------------------------------------------------------------------
392 --Process Name : SEG_SELECT_PROCESS
394 --Signals Changed : seg
396 --Description : This process is implemented to change the digits of the
397 -- 7-segment display.
398 ----------------------------------------------------------------------------------
399 SEG_SELECT_PROCESS : process (seven_seg_0, seven_seg_1)
400 begin
401 if (seg_select = '0') then
402 seg <= seven_seg_0;
403 an <= "1110";
404 elsif (seg_select = '1') then
405 seg <= seven_seg_1;
406 an <= "1101";
407 else
408 seg <= "11111111";
409 an <= "1111";
410 end if;
411 end process;
412
413
414 end heart_monitor_ARCH;
415

1 --------------------------------------------------------------------------------
2 --
3 -- Function Set
4 -- 2-line mode, display on Line 93 lcd_data <= "00111100";
5 -- 1-line mode, display on Line 94 lcd_data <= "00110100";
6 -- 1-line mode, display off Line 95 lcd_data <= "00110000";
7 -- 2-line mode, display off Line 96 lcd_data <= "00111000";
8 -- Display ON/OFF
9 -- display on, cursor off, blink off Line 104 lcd_data <= "00001100";
10 -- display on, cursor off, blink on Line 105 lcd_data <= "00001101";
11 -- display on, cursor on, blink off Line 106 lcd_data <= "00001110";
12 -- display on, cursor on, blink on Line 107 lcd_data <= "00001111";
13 -- display off, cursor off, blink off Line 108 lcd_data <= "00001000";
14 -- display off, cursor off, blink on Line 109 lcd_data <= "00001001";
15 -- display off, cursor on, blink off Line 110 lcd_data <= "00001010";
16 -- display off, cursor on, blink on Line 111 lcd_data <= "00001011";
17 -- Entry Mode Set
18 -- increment mode, entire shift off Line 127 lcd_data <= "00000110";
19 -- increment mode, entire shift on Line 128 lcd_data <= "00000111";
20 -- decrement mode, entire shift off Line 129 lcd_data <= "00000100";
21 -- decrement mode, entire shift on Line 130 lcd_data <= "00000101";
22 --
23 library IEEE;
24 use IEEE.STD_LOGIC_1164.ALL;
25 use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 entity SPI_Transfer is
27 Port (
28 -- sw : in std_logic_vector (7 downto 0); --dummy lcd_data
29 -- lcd_data : in std_logic_vector (7 downto 0);
30 clk : in std_logic;
31 btnD : in std_logic; --lcd_enable
32 JA2 : out std_logic; --LAT on SPI module
33 btnC : in std_logic; --asysnchronous RESET
34 btnU : in std_logic; --enables state machine
35 JA0 : out std_logic; --CLK
36 JA1 : out std_logic; --DAT on SPI module
37 led1 : out std_logic;
38 led3 : out std_logic; --indicates ready state
39 led5 : out std_logic; --indicates latch state
40 led7 : out std_logic --spi clock indicator
41 );
42 end SPI_Transfer;
43
44 architecture SPI_Arch of SPI_Transfer is
45
46 constant MAX : integer := 50000000; --Sets the timing interval for the state transitions
47 type spi_state is (ready,push,clk_gen,shift,done);
48 type mode is (waiting, send_h_nibble,send_l_nibble,pulse_en_1,pulse_en_2);
49 signal reset : std_logic;
--bit7--bit6--bit5--bit4--bit3--bit2--bit1--bit0
50 signal data_tx : std_logic_vector (7 downto 0);
--PWR---DB0---DB1---DB2---DB3---EN----RS----N/A
51 signal clock : std_logic;
52 signal nibble,h_nibble,l_nibble : std_logic_vector (3 downto 0); --Holds upper and
lower bits for 4-bit mode LCD.
53 signal sclk : std_logic;
54 signal latch : std_logic;
55 signal data : std_logic;
56 signal lcd_enable : std_logic; --enable signal for when to change states
57 signal lcd_data : std_logic_vector(7 downto 0);
58 signal current,next_s : spi_state;
59 signal count : integer range 0 to MAX;
60 signal lcd_state : mode;
61 signal data_buff : std_logic_vector (7 downto 0);
62 signal data_bits : std_logic_vector (3 downto 0);
63 signal clk_div : std_logic;
64
65 --Sam's signals
66 type states is (POn, Initialize, Ready, DOut);
67 signal Lcd_Control: states;
68 signal Lcd_Next: states;
69
70 begin
71 lcd_enable <= btnD;
72 --data_tx <= ('1' & nibble & enable
73 h_nibble <= lcd_data(7 downto 4);
74 l_nibble <= lcd_data(3 downto 0);

75 reset <= btnC;
76 clock <= clk;
77 JA0 <= sclk;
78 JA2 <= latch;
79 JA1 <= data;
80 led1 <= data;
81 led5 <= latch;
82 led7 <= sclk;
83
84 --Divides the Master Clock(100Mhz) based upon MAX
85 CLOCK_DIVIDER: process (clock)
86 begin
87 if rising_edge(clock) then
88 count <= count + 1;
89 if count = MAX then
90 clk_div <= not clk_div;
91 count <= 0;
92 end if;
93 end if;
94 end process;
95 --1. Send enable signal high
96 --2. Send high nibble to spi output
97 --3. Send enable signal low
98 --4. Send enable signal high
99 --5. Send low nibble to spi output
100 --6. Send enable signal low
101 SPI_Transistion: process(lcd_data,clk_div,reset)
102 begin
103 if reset = '1' then
104 lcd_state <= waiting;
105 elsif rising_edge(clk_div) then
106 case lcd_state is
107 when waiting =>
108 lcd_state <= send_h_nibble;
109 when send_h_nibble =>
110 data_tx <= ('1' & h_nibble(3 downto 0) & '1' & '0' & '1');
111 lcd_state <= pulse_en_1;
112 when pulse_en_1 =>
114 lcd_state <= send_l_nibble;
115 when send_l_nibble =>
116 data_tx <= ('1' & l_nibble(3 downto 0) & '1' & '0' & '1');
117 lcd_state <= pulse_en_2;
118 when pulse_en_2 =>
120 lcd_state <= waiting;
121 end case;
122 end if;
123 end process;
124 ---SPI Register holds the state(bit location)
125 ---and loops back to bit_0 after bit_7
126 SPI_transfer: process(clock,data_tx,reset)
127 begin
128 if reset = '1' then
129 next_s <= ready;
130 sclk <= '1';
131 latch <= '1';
132 data_bits <= "0000";
133 data <= '0';
134 data_tx <= '0';
135 elsif rising_edge(clock) then
136 case current is
137
138 when ready =>
139 led3 <= '1'; --indicate the ready state
140 sclk <= '0';
141 if lcd_enable = '1' then
142 led3 <= '0';
143 latch <= '0';
144 data_bits <= "0000"; --latch starts the sclk
145 current <= push;
146 else
147 current <= ready; --remain in ready state
148 end if;
149
150 when push =>
151 data_buff <= data_tx;

152 current <= clk_gen;
153 when clk_gen =>
154 sclk <= not sclk;
155 current <= shift;
156 when shift =>
157 data <= data_buff(7);
158 data_buff <= (data_buff(6 downto 0) & '0');
159 sclk <= not sclk;
160 if data_bits = "1000" then
161 current <= done;
162 else
163 data_bits <= data_bits + '1';
164 current <= clk_gen;
165 end if;
166 when done =>
167 latch <= '1';
168 current <= ready;
169 when others =>
170 current <= ready;
171 end case;
172 end if;
173 end process;
174
175 LCD_CONTROLLER: process(clk_div, reset)
176 variable clk_count : integer := 0; --Event Timer
177 begin
178 if (reset = '1') then
179 clk_count := 0;
180 Lcd_Control <= POn;
181 elsif(rising_edge(clk_div)) then
182 Lcd_Control <= Lcd_Next;
183 -- if (clk_count = MAX) then
184 -- clk_count := 0;
185 -- end if;
186
187 -- end process;
188
189 -- LCD_TRANSITION: process(Lcd_Control)
190 -- begin
191 case Lcd_Control is
192 when POn =>
193 if (clk_count < (MAX)) THEN
194 clk_count := clk_count + 1;
195 Lcd_Next <= POn;
196 else
197 clk_count := 0;
198 -- rs <= '0';
199 -- rw <= '0';
200 LCD_Data <= "00110000";
201 Lcd_Next <= Initialize;
202 end if;
203 when Initialize =>
205 if(clk_count < (MAX/2200)) then --function set
206 LCD_Data <= "00101100"; --2-line mode, display on
208 elsif(clk_count < (MAX/2140)) then
209 LCD_Data <= "00000000"; --display high byte
210 -- ea <= '0';
212 elsif(clk_count < (MAX/2130)) then --display on/off control
213 LCD_Data <= "00001111"; --display on, cursor on, blink on
215 elsif(clk_count < (MAX/130)) then --wait 50 us
216 LCD_Data <= "00000000";
217 -- ea <= '0';
219 elsif(clk_count < (MAX/120)) then --display clear
220 LCD_Data <= "00000001";
221 -- ea <= '1';
223 elsif(clk_count < (MAX/70)) then --wait 2 ms
224 LCD_Data <= "00000000";
225 -- ea <= '0';
227 elsif(clk_count < (MAX/60)) then --entry mode set
228 LCD_Data <= "00000110"; --increment mode, no shift

229 -- ea <= '1';
231 elsif(clk_count < (MAX/10))then --wait 60 us
232 LCD_Data <= "00000000";
233 -- ea <= '0';
235 else --initialization complete
236 clk_count := 0;
237 Lcd_Next <= Ready;
238 end if;
239
240 --wait for the enable signal and then latch in the instruction
241 when Ready =>
242 if(lcd_enable = '1') then
243 -- rs <= lcd_bus(9);
244 -- rw <= lcd_bus(8);
245 -- LCD_Data <= lcd_bus(7 DOWNTO 0);
246 LCD_Data <= "01001000"; --send 'H'
247 clk_count := 0;
248 Lcd_Next <= DOut;
249 else
250 -- busy <= '0';
251 -- rs <= '0';
252 -- rw <= '0';
253 LCD_Data <= "00000000";
254 clk_count := 0;
256 end if;
257 when DOut =>
258 if (clk_count < (MAX)) then
259 -- e <= '0';
261 Lcd_Next <= DOut;
262 else
263 clk_count := 0;
265 end if;
266 end case;
267
268 end if;
269 end process;
270
271 end SPI_Arch;
272

ECET4730_Project_Final_Report

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