Network-on-chip (NoC) is a new aspect for designing
of future System-On-Chips (SoC) where a vast number of IP
cores are connected through interconnection network. The
communication between the nodes occurred by routing packets
rather than wires. It supports high degree of scalability,
reusability and parallelism in communication. In this paper,
we present a Mesh routing architecture, which is called
Diametrical 2D Mesh of Tree, based on Mesh-of-Tree (MoT)
routing and Diametrical 2D Mesh. It has the advantage of
having small diameter as well as large bisection width and
small node degree clubbed with being the fastest network in
terms of speed. The routing algorithm ensures that the packets
will always reach from source to sink through shortest path
and is deadlock free.
This document summarizes a study that compares the performance of the MAC layer in flat and hierarchical mobile ad hoc networks (MANETs). The study uses simulation to analyze throughput and packet drops. It finds that throughput is the same for both network structures, but that hierarchical networks have fewer packet drops at the MAC layer. Specifically, packet drops only occurred at 3 nodes in the hierarchical network, whereas 14 nodes experienced drops in the flat network structure. Therefore, the hierarchical approach improves MAC layer performance by reducing packet drops.
Network-on-Chip (NoC) is a new approach for designing the communication subsystem among IP cores in a System-on-Chip (SoC). NoC applies networking theory and related methods to on-chip communication and brings out notable improvements over conventional bus and crossbar interconnections. NoC offers a great improvement over the issues like scalability, productivity, power efficiency and signal integrity challenges of complex SoC design. In an NoC, the communication among different nodes is achieved by routing packets through a pre-designed network fabric according to some routing algorithm. Therefore, architecture and related routing algorithm play an important role to the improvement of overall performance of an NoC. A Diametrical 2D Mesh routing architecture has the facility of having some additional diagonal links with simple 2D Mesh architecture. In this work, we have proposed a Modified Extended 2D routing algorithm for this architecture, which will ensure that a packet always reaches the destination through the possible shortest path, and the path is always deadlock free.
DIA-TORUS:A NOVEL TOPOLOGY FOR NETWORK ON CHIP DESIGNIJCNCJournal
The shortcomings of conventional bus architectures are in terms of scalability and the ever increasing
demand of more bandwidth. And also the feature size of sub-micron domain is decreasing making it
difficult for bus architectures to fulfill the requirements of modern System on Chip (SoC) systems. Network
on chip (NoC) architectures presents a solution to the earlier mentioned shortcomings by employing a
packet based network for inter IP communications. A pivotal feature of NoC systems is the topology in
which the system is arranged. Several parameters which are topology dependent like hop count, path
diversity, degree and other various parameters affect the system performance. We propose a novel
topology forNoC architecture which has been thoroughly compared with the existing topologies on the
basis of different network parameters.
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the
core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We
present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are
connected in recursive triplets .TriBA network topology performance analysis have been carried out from
different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks
a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture
based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a
simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by
giving them something to just plug in desired parameters and have nodes and topology set up ready for
analysis.
In a network, one-to-all broadcasting is the process of disseminating messages from a source node to all the nodes existing in the network through successive data transmissions between pairs of nodes. Broadcasting is the most primary communication process in a network. In this paper, we study on multiport wormhole-routed multicomputers where nodes are able to send multiple messages into the network at a
time. We propose efficient broadcast algorithms in multi-port wormhole-routed multicomputers which are characterized by 3D mesh topology. The proposed algorithm Three-Dimension Broadcast Layers (3-DBl) is designed such that can send messages to destinations within two start-up communication phases for each 2-D mesh. The second proposed algorithm Three-Dimension Broadcast Surfaces (3-DBS) is designed such that can send messages to destinations within six start-up communication phases. The performance study in
this paper clearly shows the advantage of the proposed algorithm.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document provides an introduction to computer networking concepts. It defines what a network is and explains that networks allow computers to share resources like files, printers, and storage. It then covers network topologies including bus, star, ring and mesh and describes the advantages and disadvantages of each. The document also discusses network hardware and software components like network interface cards, repeaters, hubs, bridges and routers. Finally, it distinguishes between intranets, which are private networks within an organization, and the public Internet.
Design and Implementation of Multistage Interconnection Networks for SoC Netw...IJCSEIT Journal
In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage
Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs,
smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved.
Each MIN can be considered as an alternative for an NoC architecture design for its simple topology and
easy scalability with low degree. This paper includes two major contributions. First, it compares the
performance of seven prominent MINs (i.e. Omega, Butterfly, Flattened Butterfly, Flattened Baseline,
Generalized Cube, Beneš and Clos networks) based on 45nm-CMOS technology and under different types
of Synthetic and Trace-driven workloads. Second, a network called Meta-Flattened Network (MFN), was
introduced that can decrease the blocking probability by means of reduction the number of hops and
increase the intermediate paths between stages. This is also led into significant decrease in power
consumption.
This document summarizes a study that compares the performance of the MAC layer in flat and hierarchical mobile ad hoc networks (MANETs). The study uses simulation to analyze throughput and packet drops. It finds that throughput is the same for both network structures, but that hierarchical networks have fewer packet drops at the MAC layer. Specifically, packet drops only occurred at 3 nodes in the hierarchical network, whereas 14 nodes experienced drops in the flat network structure. Therefore, the hierarchical approach improves MAC layer performance by reducing packet drops.
Network-on-Chip (NoC) is a new approach for designing the communication subsystem among IP cores in a System-on-Chip (SoC). NoC applies networking theory and related methods to on-chip communication and brings out notable improvements over conventional bus and crossbar interconnections. NoC offers a great improvement over the issues like scalability, productivity, power efficiency and signal integrity challenges of complex SoC design. In an NoC, the communication among different nodes is achieved by routing packets through a pre-designed network fabric according to some routing algorithm. Therefore, architecture and related routing algorithm play an important role to the improvement of overall performance of an NoC. A Diametrical 2D Mesh routing architecture has the facility of having some additional diagonal links with simple 2D Mesh architecture. In this work, we have proposed a Modified Extended 2D routing algorithm for this architecture, which will ensure that a packet always reaches the destination through the possible shortest path, and the path is always deadlock free.
DIA-TORUS:A NOVEL TOPOLOGY FOR NETWORK ON CHIP DESIGNIJCNCJournal
The shortcomings of conventional bus architectures are in terms of scalability and the ever increasing
demand of more bandwidth. And also the feature size of sub-micron domain is decreasing making it
difficult for bus architectures to fulfill the requirements of modern System on Chip (SoC) systems. Network
on chip (NoC) architectures presents a solution to the earlier mentioned shortcomings by employing a
packet based network for inter IP communications. A pivotal feature of NoC systems is the topology in
which the system is arranged. Several parameters which are topology dependent like hop count, path
diversity, degree and other various parameters affect the system performance. We propose a novel
topology forNoC architecture which has been thoroughly compared with the existing topologies on the
basis of different network parameters.
TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the
core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We
present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are
connected in recursive triplets .TriBA network topology performance analysis have been carried out from
different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks
a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture
based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a
simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by
giving them something to just plug in desired parameters and have nodes and topology set up ready for
analysis.
In a network, one-to-all broadcasting is the process of disseminating messages from a source node to all the nodes existing in the network through successive data transmissions between pairs of nodes. Broadcasting is the most primary communication process in a network. In this paper, we study on multiport wormhole-routed multicomputers where nodes are able to send multiple messages into the network at a
time. We propose efficient broadcast algorithms in multi-port wormhole-routed multicomputers which are characterized by 3D mesh topology. The proposed algorithm Three-Dimension Broadcast Layers (3-DBl) is designed such that can send messages to destinations within two start-up communication phases for each 2-D mesh. The second proposed algorithm Three-Dimension Broadcast Surfaces (3-DBS) is designed such that can send messages to destinations within six start-up communication phases. The performance study in
this paper clearly shows the advantage of the proposed algorithm.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document provides an introduction to computer networking concepts. It defines what a network is and explains that networks allow computers to share resources like files, printers, and storage. It then covers network topologies including bus, star, ring and mesh and describes the advantages and disadvantages of each. The document also discusses network hardware and software components like network interface cards, repeaters, hubs, bridges and routers. Finally, it distinguishes between intranets, which are private networks within an organization, and the public Internet.
Design and Implementation of Multistage Interconnection Networks for SoC Netw...IJCSEIT Journal
In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage
Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs,
smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved.
Each MIN can be considered as an alternative for an NoC architecture design for its simple topology and
easy scalability with low degree. This paper includes two major contributions. First, it compares the
performance of seven prominent MINs (i.e. Omega, Butterfly, Flattened Butterfly, Flattened Baseline,
Generalized Cube, Beneš and Clos networks) based on 45nm-CMOS technology and under different types
of Synthetic and Trace-driven workloads. Second, a network called Meta-Flattened Network (MFN), was
introduced that can decrease the blocking probability by means of reduction the number of hops and
increase the intermediate paths between stages. This is also led into significant decrease in power
consumption.
This document provides an overview of various multistage interconnection networks (MINs) including cube, shuffle exchange, omega, phi, double tree, and fault-tolerant networks. It reviews the construction and performance of these networks, describing their structure and routing functions. Examples of specific MINs are given, such as the extra stage cube, shuffle exchange with extra stages, and augmented shuffle exchange networks.
This document summarizes a study evaluating the performance of the Ad Hoc On-Demand Distance Vector (AODV) routing protocol in mobile ad hoc networks with varying network sizes using NS-2 simulation. The study investigates key performance metrics such as packet delivery fraction, average end-to-end delay, normalized routing load, and throughput for network sizes ranging from 5 to 50 nodes. The results show that AODV exhibits high packet delivery fractions above 99% with relatively uniform average end-to-end delays. Normalized routing load increases with network size due to increased route requests during route discovery. Throughput initially increases but becomes stable at larger network sizes, indicating AODV's ability to deliver packets degrades as network size
Interconnection Network
in this presentation there are some explain to Interconnection Network , and espically in computer architecture and parallel processing.
The document discusses different types of system interconnect architectures used for internal connections between processors, memory modules, and I/O devices or for distributed networking of multicomputer nodes. It describes static networks like linear arrays, rings, meshes, and tori that use direct point-to-point connections and dynamic networks like buses and multistage networks that use switched channels to dynamically configure connections based on communication demands. It also covers properties, routing functions, throughput, and factors that affect performance of different network topologies.
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIPVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
This document is a study material for Class 12 Informatics Practices published by the Kendriya Vidyalaya Sangathan. It contains an index and four units on topics like networking, programming, relational database management systems, and IT applications. The networking unit discusses computer networks, communication media, network devices, topologies, protocols, and security concepts. It also covers open source concepts. The programming unit reviews concepts from Class 11 and discusses programming fundamentals. The database unit reviews RDBMS concepts and SQL commands. The IT applications unit discusses developing front-end interfaces, backend databases, and demonstrating applications in domains like e-governance, e-business and e-learning. Sample question papers are also included.
This document summarizes several static network topologies:
- Mesh networks connect each adjacent pair of nodes in rows and columns, with interior node degree depending on the network size. The Illiac mesh reduced the diameter by allowing wraparound connections.
- Torus networks add ring connections in each dimension, making them symmetric.
- Systolic arrays specially arrange processing elements and links to match specific algorithms' computation and communication needs, potentially improving performance but at higher cost and programming complexity.
- Hypercubes connect nodes along multiple dimensions, but have poor scalability and difficult packaging for higher dimensions.
Broadcast is one of the most important approach in distributed memory parallel computers that is used to
find a routing approach from a one source to all nodes in the mesh. Broadcasting is a data communication task in which corresponds to one-to-all communication. Routing schema is the approach that used to determine the road that is used to send a message from a source node to destination nodes. In this paper, we propose an efficient two algorithms for broadcasting on an all-port wormhole-routed 3D mesh with arbitrary size. In wormhole routing large network packets are broken into small pieces called FLITs (flow control digits). The destination address is kept in the first flit which is called the header flit and sets up the
routing behavior for all subsequent flits associated with the packet. If the packets of the message can’t deliver to their destination and there is a cyclic dependence over the channels in the network, then the deadlock even is occurred. In this paper we introduce an efficient two algorithms, Three-Dimension Hamiltonian Broadcast (3-DHB) and Three-Dimension Six Ports Hamiltonian Broadcast (3-DSPHB) which used broadcast communication facility with deadlock-free wormhole routing in general threedimensional networks. In this paper the behaviors of these algorithms were compared using simulation. The results presented in this paper indicate that the advantage of the proposed algorithms.
This document introduces computer networking concepts. It defines a network as connecting two or more computers to share resources like files, printers, and storage. Network topologies include bus, star, ring and mesh configurations for connecting devices either physically or logically. The document also discusses client-server models, peer-to-peer networking, intranets vs the Internet, and network hardware and software components.
This document provides an introduction to computer networking concepts. It defines what a network is and explains that networks allow computers to share resources like files, printers, and storage. It then covers network topologies including bus, star, ring and mesh; common network devices like switches, routers and hubs; and different types of networks including local area networks (LANs), wide area networks (WANs) and metropolitan area networks (MANs). It also discusses client-server models and peer-to-peer networks.
Iterative network channel decoding with cooperative space-time transmissionijasuc
This document summarizes an iterative network-channel decoding scheme for cooperative space-time transmission with network coding. The scheme uses convolutional codes as network codes at the relay node and Reed-Solomon codes as channel codes at the user nodes. An iterative joint network-channel decoder exchanges soft information between convolutional code-based network decoder and Reed-Solomon code-based channel decoders. Extrinsic information transfer analysis is performed to investigate the convergence properties of the proposed iterative decoder.
Design of an Efficient Communication Protocol for 3d Interconnection NetworkIJMTST Journal
Three-dimensional integrated circuits (3D ICs) provide better device integration, reduced signal delay and reduced interconnect power. They additionally give better layout flexibility by permitting heterogeneous integration, by taking the advantage of intrinsic capability of reducing the wire length in 3D ICs, 3D NOC Bus Hybrid mesh layout was suggested. This layout provides an apparently significant stage to implement economical multicast routings for 3D networks-on-chip. A unique multicast partitioning and routing strategy for the 3D NOC-Bus Hybrid mesh architectures to improve the system performance and to decrease the power consumption is being proposed. The planned design exploits the useful attribute of a single-hop (bus-based) interlayer communication of the 3D stacked mesh design to supply superior hardware multicast support. Finally customized partitioning approach and an effective routing method is given to decrease the average hop count and network latency. Compared to the recently designed 3D NOC architectures being capable of supporting hardware multicasting, huge simulations with traffic profiles reveals design exploitation, which is the planned multicast routing strategy will facilitate significant performance enhancements.
Optimization of ipv6 packet’s headers over ethernetIAEME Publication
This document discusses optimizing IPv6 packet headers over Ethernet frames. It proposes:
1. Creating "master packets" that contain all header fields but no data, and "slave packets" that contain only fixed header fields, an ID, tag, and data. This reduces repeated header information.
2. Processing starts with the master packet headers, then slave packets require less processing as they only contain fixed header fields and data.
3. This optimization aims to reduce processing time by decreasing repeated header contents, allowing more space for data in each packet and faster transmission speeds.
An Efficient Wireless Backhaul Utilizing MIMO Transmission and IPT ForwardingCSCJournals
Wireless backhaul has been received much attention as an enabler of future broadband mobile communication systems because it can reduce deployment cost of pico-cells, an essential part of high capacity system. A high performance network, high throughput, low average delay and low packet loss rate, is highly appreciated to sustain the increasing proliferation in multimedia transmissions. The critical issue reducing the performance of wireless backhaul is the interference occurred in the network due to simultaneous nodes transmissions. In this research, we propose a high performance wireless backhaul using the low interference sensitivity MIMO based nodes. MIMO transmission has a better BER performance over SISO one even with the same transmission rate and bandwidth, which means that MIMO can operate at lower SINR values than SISO and give the same performance. This MIMO robust performance against interference gives us a greater benefit when adopted as a wireless interface in wireless backhaul than SISO. These facts motivated us to use the IEEE 802.11n the current MIMO standard to design a MIMO based wireless backhaul. In addition and to justify our assumptions, we investigate the effect of MIMO channels correlation, a major drawback in MIMO transmission, upon the system performance, and prove the robustness of the scheme under different MIMO channels correlation values. After proving the effectiveness of MIMO as a wireless interface for wireless backhaul, we further improve the performance of this MIMO-backhaul using the high efficient Intermittent Periodic Transmit (IPT) forwarding protocol. IPT is a reduced interference packet forwarding protocol with a more efficient relay performance than conventional method in which packets are transmitted continuously form the source nodes. By using these two techniques (IEEE 802.11n (MIMO) + IPT), wireless backhaul nodes can meet more demanding communication requirements such as higher throughput, lower average delay, and lower packet dropping rate than those achieved by simply applying IEEE 802.11n to conventionally relayed backhaul. The proposed wireless backhaul will accelerate introduction of picocell based mobile communication systems.
The document discusses the Transparent Interconnection of Lots of Links (TRILL) protocol. It begins by describing some problems with the existing Spanning Tree Protocol (STP), such as inefficient paths, underutilized bandwidth, lack of multipath forwarding, and slow convergence. It then introduces TRILL as a solution, which uses routing bridges and IS-IS routing to calculate optimal layer 2 paths. Key benefits of TRILL include shortest path forwarding, multipath forwarding for better bandwidth utilization, reduced forwarding table sizes, loop mitigation, and VLAN support. TRILL headers are also described.
The document introduces computer networking concepts including definitions, advantages, disadvantages, classifications and topologies. It defines a network as connecting computers to share resources. Local area networks connect computers in a small area like a building, while wide area networks connect LANs across cities/countries. Key networking hardware includes network interface cards, repeaters, hubs, bridges, routers and switches.
The document discusses communication protocols and the OSI model. It provides details on each of the 7 layers of the OSI model and their functions. It also summarizes IBM's Systems Network Architecture (SNA) model, which maps to the 7 layers of OSI. SNA defines physical, data link, path, transmission, data flow, presentation and transaction layers that perform similar functions to their OSI counterparts.
This document summarizes a study comparing the performance of the AODV and MAODV routing protocols in a mobile ad hoc network (MANET) using the Network Simulator 2 (NS-2). The study introduces a malicious node to simulate a hacker attack and analyzes the impact on packet delivery ratio, end-to-end delay, and throughput under different node densities and pause times. The results show that MAODV has lower performance than AODV, and the difference increases as the number of nodes increases due to the greater impact of the malicious node. Future work could extend the study to include more malicious nodes and design a new protocol to detect and mitigate malicious nodes.
Neural network based energy efficient clustering and routingambitlick
This document summarizes a paper that proposes a neural network based approach for energy efficient clustering and routing in wireless sensor networks. The key points are:
1. It proposes a neural network based clustering algorithm to select cluster heads in a way that balances energy consumption.
2. It defines a routing metric based on transmission and reception energy and uses it to formulate the routing problem as a linear program to optimize energy efficiency.
3. It presents algorithms for cluster head selection using the neural network, and for multi-path routing and data transmission based on the routing metric and linear program formulation.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
This document provides an overview of various multistage interconnection networks (MINs) including cube, shuffle exchange, omega, phi, double tree, and fault-tolerant networks. It reviews the construction and performance of these networks, describing their structure and routing functions. Examples of specific MINs are given, such as the extra stage cube, shuffle exchange with extra stages, and augmented shuffle exchange networks.
This document summarizes a study evaluating the performance of the Ad Hoc On-Demand Distance Vector (AODV) routing protocol in mobile ad hoc networks with varying network sizes using NS-2 simulation. The study investigates key performance metrics such as packet delivery fraction, average end-to-end delay, normalized routing load, and throughput for network sizes ranging from 5 to 50 nodes. The results show that AODV exhibits high packet delivery fractions above 99% with relatively uniform average end-to-end delays. Normalized routing load increases with network size due to increased route requests during route discovery. Throughput initially increases but becomes stable at larger network sizes, indicating AODV's ability to deliver packets degrades as network size
Interconnection Network
in this presentation there are some explain to Interconnection Network , and espically in computer architecture and parallel processing.
The document discusses different types of system interconnect architectures used for internal connections between processors, memory modules, and I/O devices or for distributed networking of multicomputer nodes. It describes static networks like linear arrays, rings, meshes, and tori that use direct point-to-point connections and dynamic networks like buses and multistage networks that use switched channels to dynamically configure connections based on communication demands. It also covers properties, routing functions, throughput, and factors that affect performance of different network topologies.
AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIPVLSICS Design
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
This document is a study material for Class 12 Informatics Practices published by the Kendriya Vidyalaya Sangathan. It contains an index and four units on topics like networking, programming, relational database management systems, and IT applications. The networking unit discusses computer networks, communication media, network devices, topologies, protocols, and security concepts. It also covers open source concepts. The programming unit reviews concepts from Class 11 and discusses programming fundamentals. The database unit reviews RDBMS concepts and SQL commands. The IT applications unit discusses developing front-end interfaces, backend databases, and demonstrating applications in domains like e-governance, e-business and e-learning. Sample question papers are also included.
This document summarizes several static network topologies:
- Mesh networks connect each adjacent pair of nodes in rows and columns, with interior node degree depending on the network size. The Illiac mesh reduced the diameter by allowing wraparound connections.
- Torus networks add ring connections in each dimension, making them symmetric.
- Systolic arrays specially arrange processing elements and links to match specific algorithms' computation and communication needs, potentially improving performance but at higher cost and programming complexity.
- Hypercubes connect nodes along multiple dimensions, but have poor scalability and difficult packaging for higher dimensions.
Broadcast is one of the most important approach in distributed memory parallel computers that is used to
find a routing approach from a one source to all nodes in the mesh. Broadcasting is a data communication task in which corresponds to one-to-all communication. Routing schema is the approach that used to determine the road that is used to send a message from a source node to destination nodes. In this paper, we propose an efficient two algorithms for broadcasting on an all-port wormhole-routed 3D mesh with arbitrary size. In wormhole routing large network packets are broken into small pieces called FLITs (flow control digits). The destination address is kept in the first flit which is called the header flit and sets up the
routing behavior for all subsequent flits associated with the packet. If the packets of the message can’t deliver to their destination and there is a cyclic dependence over the channels in the network, then the deadlock even is occurred. In this paper we introduce an efficient two algorithms, Three-Dimension Hamiltonian Broadcast (3-DHB) and Three-Dimension Six Ports Hamiltonian Broadcast (3-DSPHB) which used broadcast communication facility with deadlock-free wormhole routing in general threedimensional networks. In this paper the behaviors of these algorithms were compared using simulation. The results presented in this paper indicate that the advantage of the proposed algorithms.
This document introduces computer networking concepts. It defines a network as connecting two or more computers to share resources like files, printers, and storage. Network topologies include bus, star, ring and mesh configurations for connecting devices either physically or logically. The document also discusses client-server models, peer-to-peer networking, intranets vs the Internet, and network hardware and software components.
This document provides an introduction to computer networking concepts. It defines what a network is and explains that networks allow computers to share resources like files, printers, and storage. It then covers network topologies including bus, star, ring and mesh; common network devices like switches, routers and hubs; and different types of networks including local area networks (LANs), wide area networks (WANs) and metropolitan area networks (MANs). It also discusses client-server models and peer-to-peer networks.
Iterative network channel decoding with cooperative space-time transmissionijasuc
This document summarizes an iterative network-channel decoding scheme for cooperative space-time transmission with network coding. The scheme uses convolutional codes as network codes at the relay node and Reed-Solomon codes as channel codes at the user nodes. An iterative joint network-channel decoder exchanges soft information between convolutional code-based network decoder and Reed-Solomon code-based channel decoders. Extrinsic information transfer analysis is performed to investigate the convergence properties of the proposed iterative decoder.
Design of an Efficient Communication Protocol for 3d Interconnection NetworkIJMTST Journal
Three-dimensional integrated circuits (3D ICs) provide better device integration, reduced signal delay and reduced interconnect power. They additionally give better layout flexibility by permitting heterogeneous integration, by taking the advantage of intrinsic capability of reducing the wire length in 3D ICs, 3D NOC Bus Hybrid mesh layout was suggested. This layout provides an apparently significant stage to implement economical multicast routings for 3D networks-on-chip. A unique multicast partitioning and routing strategy for the 3D NOC-Bus Hybrid mesh architectures to improve the system performance and to decrease the power consumption is being proposed. The planned design exploits the useful attribute of a single-hop (bus-based) interlayer communication of the 3D stacked mesh design to supply superior hardware multicast support. Finally customized partitioning approach and an effective routing method is given to decrease the average hop count and network latency. Compared to the recently designed 3D NOC architectures being capable of supporting hardware multicasting, huge simulations with traffic profiles reveals design exploitation, which is the planned multicast routing strategy will facilitate significant performance enhancements.
Optimization of ipv6 packet’s headers over ethernetIAEME Publication
This document discusses optimizing IPv6 packet headers over Ethernet frames. It proposes:
1. Creating "master packets" that contain all header fields but no data, and "slave packets" that contain only fixed header fields, an ID, tag, and data. This reduces repeated header information.
2. Processing starts with the master packet headers, then slave packets require less processing as they only contain fixed header fields and data.
3. This optimization aims to reduce processing time by decreasing repeated header contents, allowing more space for data in each packet and faster transmission speeds.
An Efficient Wireless Backhaul Utilizing MIMO Transmission and IPT ForwardingCSCJournals
Wireless backhaul has been received much attention as an enabler of future broadband mobile communication systems because it can reduce deployment cost of pico-cells, an essential part of high capacity system. A high performance network, high throughput, low average delay and low packet loss rate, is highly appreciated to sustain the increasing proliferation in multimedia transmissions. The critical issue reducing the performance of wireless backhaul is the interference occurred in the network due to simultaneous nodes transmissions. In this research, we propose a high performance wireless backhaul using the low interference sensitivity MIMO based nodes. MIMO transmission has a better BER performance over SISO one even with the same transmission rate and bandwidth, which means that MIMO can operate at lower SINR values than SISO and give the same performance. This MIMO robust performance against interference gives us a greater benefit when adopted as a wireless interface in wireless backhaul than SISO. These facts motivated us to use the IEEE 802.11n the current MIMO standard to design a MIMO based wireless backhaul. In addition and to justify our assumptions, we investigate the effect of MIMO channels correlation, a major drawback in MIMO transmission, upon the system performance, and prove the robustness of the scheme under different MIMO channels correlation values. After proving the effectiveness of MIMO as a wireless interface for wireless backhaul, we further improve the performance of this MIMO-backhaul using the high efficient Intermittent Periodic Transmit (IPT) forwarding protocol. IPT is a reduced interference packet forwarding protocol with a more efficient relay performance than conventional method in which packets are transmitted continuously form the source nodes. By using these two techniques (IEEE 802.11n (MIMO) + IPT), wireless backhaul nodes can meet more demanding communication requirements such as higher throughput, lower average delay, and lower packet dropping rate than those achieved by simply applying IEEE 802.11n to conventionally relayed backhaul. The proposed wireless backhaul will accelerate introduction of picocell based mobile communication systems.
The document discusses the Transparent Interconnection of Lots of Links (TRILL) protocol. It begins by describing some problems with the existing Spanning Tree Protocol (STP), such as inefficient paths, underutilized bandwidth, lack of multipath forwarding, and slow convergence. It then introduces TRILL as a solution, which uses routing bridges and IS-IS routing to calculate optimal layer 2 paths. Key benefits of TRILL include shortest path forwarding, multipath forwarding for better bandwidth utilization, reduced forwarding table sizes, loop mitigation, and VLAN support. TRILL headers are also described.
The document introduces computer networking concepts including definitions, advantages, disadvantages, classifications and topologies. It defines a network as connecting computers to share resources. Local area networks connect computers in a small area like a building, while wide area networks connect LANs across cities/countries. Key networking hardware includes network interface cards, repeaters, hubs, bridges, routers and switches.
The document discusses communication protocols and the OSI model. It provides details on each of the 7 layers of the OSI model and their functions. It also summarizes IBM's Systems Network Architecture (SNA) model, which maps to the 7 layers of OSI. SNA defines physical, data link, path, transmission, data flow, presentation and transaction layers that perform similar functions to their OSI counterparts.
This document summarizes a study comparing the performance of the AODV and MAODV routing protocols in a mobile ad hoc network (MANET) using the Network Simulator 2 (NS-2). The study introduces a malicious node to simulate a hacker attack and analyzes the impact on packet delivery ratio, end-to-end delay, and throughput under different node densities and pause times. The results show that MAODV has lower performance than AODV, and the difference increases as the number of nodes increases due to the greater impact of the malicious node. Future work could extend the study to include more malicious nodes and design a new protocol to detect and mitigate malicious nodes.
Neural network based energy efficient clustering and routingambitlick
This document summarizes a paper that proposes a neural network based approach for energy efficient clustering and routing in wireless sensor networks. The key points are:
1. It proposes a neural network based clustering algorithm to select cluster heads in a way that balances energy consumption.
2. It defines a routing metric based on transmission and reception energy and uses it to formulate the routing problem as a linear program to optimize energy efficiency.
3. It presents algorithms for cluster head selection using the neural network, and for multi-path routing and data transmission based on the routing metric and linear program formulation.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Investigating the Performance of NoC Using Hierarchical Routing ApproachIJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
Noise Tolerant and Faster On Chip Communication Using Binoc ModelIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
Area-Efficient Design of Scheduler for Routing Node of Network-On-ChipVLSICS Design
This document describes an area-efficient design for a scheduler used in routing nodes of a Network-on-Chip (NoC). The scheduler arbitrates between requests from input ports to access the switching fabric. The original scheduler design uses round-robin arbitration and has separate grant and accept arbiters. The proposed design folds the scheduler onto itself, reducing its area by 50% while maintaining the same scheduling functionality. Synthesis results show the modified scheduler has a 30% smaller area but requires two extra clock cycles per scheduling decision compared to the original design.
This document discusses different network topologies including bus, star, ring, mesh, tree, and hybrid topologies. It provides details on how each topology connects devices, how data is transferred, advantages and disadvantages of each. Bus topology uses a central backbone cable to connect all devices but if it fails the whole network fails. Star topology uses a central hub to connect devices in a point-to-point fashion, avoiding single point of failure issues but the hub remains a bottleneck. Ring topology connects devices in a continuous ring path allowing data to travel in one direction, but a single break disconnects the whole network. Hybrid topologies combine two or more standard topologies to utilize their advantages while reducing weaknesses.
ENERGY CONSUMPTION IMPROVEMENT OF TRADITIONAL CLUSTERING METHOD IN WIRELESS S...IJCNCJournal
In the traditional clustering routing protocol of wireless sensor network, LEACH protocol (Low Energy
Adaptive Clustering Hierarchy) is considered to have many outstanding advantages in the implementation
of the hierarchy according to low energy adaptive cluster to collect and distribute the data to the base
station. The main objective of LEACH is: To prolong life time of the network, reduce the energy
consumption by each node, using the data concentration to reduce bulletins in the network. However, in the
case of large network, the distance from the nodes to the base station is very different. Therefore, the
energy consumption when becoming the host node is very different but LEACH is not based on the
remaining energy to choose the host node, which is based on the number of times to become the host node
in the previous rounds. This makes the nodes far away from the base station lose power sooner.
In this paper, we give a new routing protocol based on the LEACH protocol in order to improve operating
time of sensor network by considering energy issues and distance in selecting the cluster-head (CH), at that
time the nodes with high energy and near the base station (BS) will have a greater probability of becoming
the cluster-head than the those in far and with lower energy.
Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Ar...TELKOMNIKA JOURNAL
The document discusses topology design for low latency Network-on-Chip (NoC) architectures. It proposes an 8x8 XX-Torus and 64-node XX-Ring topology to minimize latency by decreasing the node diameter from source to destination. It compares the performance of mesh, full-mesh, torus, and ring topologies to the proposed XX-Torus and XX-Ring topologies in terms of average latency. Simulation results show that the XX-Ring topology outperforms the other topologies by decreasing average latency by over 100% in some cases.
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
Comparative performance evaluation of routing algorithm and topology size for...journalBEEI
Wireless Network-on-Chip or WiNoC is an alternative to traditional planar on-chip networks. On-chip wireless links are utilized to reduce latency between distant nodes due to its capability to communicate with far-away node within a single hop. This paper analyzes the impact of various routing schemes and the effect of WiNoC sizes on network traffic distributions compared to conventional mesh NoC. Radio hubs (4×4) are evenly placed on WiNoC to analyze global average delay, throughput, energy consumption and wireless utilization. For validation, three various network sizes (8×8, 16×16 and 32×32) of mesh NoC and WiNoC architectures are simulated on cycle-accurate Noxim simulator under numerous traffic load distributions. Simulation results show that WiNoC architecture with the 16×16 network size has better average speedup (∼1.2×) and improved network throughputs by 6.36% in non-uniform transpose traffic distribution. As the trade-off, WiNoC requires 63% higher energy consumption compared to the classical wired NoC mesh.
A low complexity distributed differential scheme based on orthogonal space t...IJECEIAES
The document presents a new low complexity distributed differential scheme for decode-and-forward wireless relay networks. The proposed scheme uses orthogonal space time block coding and does not require channel state information or differential encoding. It achieves high data rates with low decoding complexity at the source, relay, and destination nodes. Computer simulations show the proposed differential technique outperforms reference strategies and enjoys low encoding and decoding complexity while providing full transmission rate.
The document discusses network-on-chip (NoC) technology. NoC uses a packet switched network approach to connect intellectual property cores on a chip. It provides advantages over traditional bus-based interconnects like higher bandwidth, energy efficiency, and scalability. NoCs operate using a layered approach with physical, transport, and transaction layers. Common routing algorithms for NoCs include dimension order routing, XY routing, fully adaptive routing, and minimal adaptive routing. NoCs allow for modular and reconfigurable integration of IP cores from different vendors.
Enhancement of Improved Balanced LEACH for Heterogeneous Wireless Sensor Netw...acijjournal
This document summarizes a research paper that proposes an enhancement to the Improved Balanced LEACH (IB-LEACH) routing protocol for heterogeneous wireless sensor networks. The proposed enhancement stores residual energy from each routing round in an "energy bank" to increase network lifetime. It also enhances the ACTIVE_ROUTE_TIMEOUT parameter in the underlying AODV routing protocol. Simulation results using MATLAB show the proposed approach improves network lifetime compared to previous methods. The document provides background on wireless sensor networks, routing protocols, LEACH clustering, and IB-LEACH before detailing the proposed enhancement and simulation results.
3D IC technology stacks multiple layers of active silicon circuits to reduce interconnect length and delay. Shorter global interconnects in 3D ICs are expected to reduce both switching energy and cycle time compared to conventional 2D designs. 3D fabrication involves bonding or epitaxial growth of multiple processed silicon wafers. EDA tools are needed to automate the placement, routing, and design of circuits across multiple layers to fully leverage 3D integration.
The document discusses investigating packet transmission strategies in a MIMO equipped mobile ad hoc network using space-time coding. It proposes a new scheduling algorithm that improves packet transmission rate and energy performance. The system is modeled in OPNET using 40 randomly distributed nodes. Simulation results show the new algorithm enhances transmission efficiency compared to other methods by controlling node firing and scheduling packet transmissions based on network conditions and traffic demands.
The improvement of end to end delays in network management system using netwo...IJCNCJournal
The document summarizes research on improving end-to-end delays in a network management system using network coding. Specifically, it applies network coding to manage radio and television broadcast stations in a wireless network. The study shows that a proposed "Fast Forwarding Strategy" using network coding outperforms a classical routing strategy in reducing end-to-end delays from source to destination. It analyzes end-to-end delays theoretically using network calculus and conducts a practical study on a network of broadcast stations, finding the proposed strategy reduces delays compared to the classical strategy.
Core Based Group Communication with Qos SupportIOSR Journals
This document summarizes a research paper on using core-based group communication to support quality of service (QoS) in broadband networks. It discusses using a core-based approach to fulfill increasing demands for internet services and multimedia applications. The paper proposes a new core selection method as an alternative to existing SPAN/COST approaches to make the core-based solution more flexible. It evaluates the performance of the new method through simulations and finds that the cost of the network varies directly with the number of sources and cores, and inversely with the number of receivers. The approach can calculate network costs for large node sizes more efficiently than SPAN/COST.
Similar to Diametrical Mesh of Tree (D2D-MoT) Architecture: A Novel Routing Solution for NoC (20)
Power System State Estimation - A ReviewIDES Editor
This document provides a review of power system state estimation techniques. It discusses both static and dynamic state estimation algorithms. For static state estimation, it covers weighted least squares, decoupled, and robust estimation methods. Weighted least squares is commonly used but can have numerical instability issues. Decoupled state estimation approximates the gain matrix for faster computation. Robust estimation uses M-estimators and other techniques to handle outliers and bad data. Dynamic state estimation applies Kalman filtering, leapfrog algorithms, and other methods to continuously monitor system states over time.
Artificial Intelligence Technique based Reactive Power Planning Incorporating...IDES Editor
This document summarizes a research paper that proposes using artificial intelligence techniques and FACTS controllers for reactive power planning in real-time power transmission systems. The paper formulates the reactive power planning problem and incorporates flexible AC transmission system (FACTS) devices like static VAR compensators (SVC), thyristor controlled series capacitors (TCSC), and unified power flow controllers (UPFC). Evolutionary algorithms like evolutionary programming (EP) and differential evolution (DE) are applied to find the optimal locations and settings of the FACTS controllers to minimize losses and costs. Simulation results on IEEE 30-bus and 72-bus Indian test systems show that UPFC performs best in reducing losses compared to SVC and TCSC.
Design and Performance Analysis of Genetic based PID-PSS with SVC in a Multi-...IDES Editor
Damping of power system oscillations with the help
of proposed optimal Proportional Integral Derivative Power
System Stabilizer (PID-PSS) and Static Var Compensator
(SVC)-based controllers are thoroughly investigated in this
paper. This study presents robust tuning of PID-PSS and
SVC-based controllers using Genetic Algorithms (GA) in
multi machine power systems by considering detailed model
of the generators (model 1.1). The effectiveness of FACTSbased
controllers in general and SVC-based controller in
particular depends upon their proper location. Modal
controllability and observability are used to locate SVC–based
controller. The performance of the proposed controllers is
compared with conventional lead-lag power system stabilizer
(CPSS) and demonstrated on 10 machines, 39 bus New England
test system. Simulation studies show that the proposed genetic
based PID-PSS with SVC based controller provides better
performance.
Optimal Placement of DG for Loss Reduction and Voltage Sag Mitigation in Radi...IDES Editor
This paper presents the need to operate the power
system economically and with optimum levels of voltages has
further led to an increase in interest in Distributed
Generation. In order to reduce the power losses and to improve
the voltage in the distribution system, distributed generators
(DGs) are connected to load bus. To reduce the total power
losses in the system, the most important process is to identify
the proper location for fixing and sizing of DGs. It presents a
new methodology using a new population based meta heuristic
approach namely Artificial Bee Colony algorithm(ABC) for
the placement of Distributed Generators(DG) in the radial
distribution systems to reduce the real power losses and to
improve the voltage profile, voltage sag mitigation. The power
loss reduction is important factor for utility companies because
it is directly proportional to the company benefits in a
competitive electricity market, while reaching the better power
quality standards is too important as it has vital effect on
customer orientation. In this paper an ABC algorithm is
developed to gain these goals all together. In order to evaluate
sag mitigation capability of the proposed algorithm, voltage
in voltage sensitive buses is investigated. An existing 20KV
network has been chosen as test network and results are
compared with the proposed method in the radial distribution
system.
Line Losses in the 14-Bus Power System Network using UPFCIDES Editor
Controlling power flow in modern power systems
can be made more flexible by the use of recent developments
in power electronic and computing control technology. The
Unified Power Flow Controller (UPFC) is a Flexible AC
transmission system (FACTS) device that can control all the
three system variables namely line reactance, magnitude and
phase angle difference of voltage across the line. The UPFC
provides a promising means to control power flow in modern
power systems. Essentially the performance depends on proper
control setting achievable through a power flow analysis
program. This paper presents a reliable method to meet the
requirements by developing a Newton-Raphson based load
flow calculation through which control settings of UPFC can
be determined for the pre-specified power flow between the
lines. The proposed method keeps Newton-Raphson Load Flow
(NRLF) algorithm intact and needs (little modification in the
Jacobian matrix). A MATLAB program has been developed to
calculate the control settings of UPFC and the power flow
between the lines after the load flow is converged. Case studies
have been performed on IEEE 5-bus system and 14-bus system
to show that the proposed method is effective. These studies
indicate that the method maintains the basic NRLF properties
such as fast computational speed, high degree of accuracy and
good convergence rate.
Study of Structural Behaviour of Gravity Dam with Various Features of Gallery...IDES Editor
The size and shape of opening in dam causes the
stress concentration, it also causes the stress variation in the
rest of the dam cross section. The gravity method of the analysis
does not consider the size of opening and the elastic property
of dam material. Thus the objective of study is comprises of
the Finite Element Method which considers the size of
opening, elastic property of material, and stress distribution
because of geometric discontinuity in cross section of dam.
Stress concentration inside the dam increases with the opening
in dam which results in the failure of dam. Hence it is
necessary to analyses large opening inside the dam. By making
the percentage area of opening constant and varying size and
shape of opening the analysis is carried out. For this purpose
a section of Koyna Dam is considered. Dam is defined as a
plane strain element in FEM, based on geometry and loading
condition. Thus this available information specified our path
of approach to carry out 2D plane strain analysis. The results
obtained are then compared mutually to get most efficient
way of providing large opening in the gravity dam.
Assessing Uncertainty of Pushover Analysis to Geometric ModelingIDES Editor
Pushover Analysis a popular tool for seismic
performance evaluation of existing and new structures and is
nonlinear Static procedure where in monotonically increasing
loads are applied to the structure till the structure is unable
to resist the further load .During the analysis, whatever the
strength of concrete and steel is adopted for analysis of
structure may not be the same when real structure is
constructed and the pushover analysis results are very sensitive
to material model adopted, geometric model adopted, location
of plastic hinges and in general to procedure followed by the
analyzer. In this paper attempt has been made to assess
uncertainty in pushover analysis results by considering user
defined hinges and frame modeled as bare frame and frame
with slab modeled as rigid diaphragm and results compared
with experimental observations. Uncertain parameters
considered includes the strength of concrete, strength of steel
and cover to the reinforcement which are randomly generated
and incorporated into the analysis. The results are then
compared with experimental observations.
Secure Multi-Party Negotiation: An Analysis for Electronic Payments in Mobile...IDES Editor
This document summarizes and analyzes secure multi-party negotiation protocols for electronic payments in mobile computing. It presents a framework for secure multi-party decision protocols using lightweight implementations. The main focus is on synchronizing security features to avoid agreement manipulation and reduce user traffic. The paper describes negotiation between an auctioneer and bidders, showing multiparty security is better than existing systems. It analyzes the performance of encryption algorithms like ECC, XTR, and RSA for use in the multiparty negotiation protocols.
Selfish Node Isolation & Incentivation using Progressive ThresholdsIDES Editor
The problems associated with selfish nodes in
MANET are addressed by a collaborative watchdog approach
which reduces the detection time for selfish nodes thereby
improves the performance and accuracy of watchdogs[1]. In
the related works they make use of credit based systems, reputation
based mechanisms, pathrater and watchdog mechanism
to detect such selfish nodes. In this paper we follow an approach
of collaborative watchdog which reduces the detection
time for selfish nodes and also involves the removal of such
selfish nodes based on some progressively assessed thresholds.
The threshold gives the nodes a chance to stop misbehaving
before it is permanently deleted from the network.
The node passes through several isolation processes before it
is permanently removed. Another version of AODV protocol
is used here which allows the simulation of selfish nodes in
NS2 by adding or modifying log files in the protocol.
Various OSI Layer Attacks and Countermeasure to Enhance the Performance of WS...IDES Editor
Wireless sensor networks are networks having non
wired infrastructure and dynamic topology. In OSI model each
layer is prone to various attacks, which halts the performance
of a network .In this paper several attacks on four layers of
OSI model are discussed and security mechanism is described
to prevent attack in network layer i.e wormhole attack. In
Wormhole attack two or more malicious nodes makes a covert
channel which attracts the traffic towards itself by depicting a
low latency link and then start dropping and replaying packets
in the multi-path route. This paper proposes promiscuous mode
method to detect and isolate the malicious node during
wormhole attack by using Ad-hoc on demand distance vector
routing protocol (AODV) with omnidirectional antenna. The
methodology implemented notifies that the nodes which are
not participating in multi-path routing generates an alarm
message during delay and then detects and isolate the
malicious node from network. We also notice that not only
the same kind of attacks but also the same kind of
countermeasures can appear in multiple layer. For example,
misbehavior detection techniques can be applied to almost all
the layers we discussed.
Responsive Parameter based an AntiWorm Approach to Prevent Wormhole Attack in...IDES Editor
The recent advancements in the wireless technology
and their wide-spread deployment have made remarkable
enhancements in efficiency in the corporate and industrial
and Military sectors The increasing popularity and usage of
wireless technology is creating a need for more secure wireless
Ad hoc networks. This paper aims researched and developed
a new protocol that prevents wormhole attacks on a ad hoc
network. A few existing protocols detect wormhole attacks but
they require highly specialized equipment not found on most
wireless devices. This paper aims to develop a defense against
wormhole attacks as an Anti-worm protocol which is based on
responsive parameters, that does not require as a significant
amount of specialized equipment, trick clock synchronization,
no GPS dependencies.
Cloud Security and Data Integrity with Client Accountability FrameworkIDES Editor
This document summarizes a proposed cloud security and data integrity framework that provides client accountability. The framework aims to address issues like lack of user control over cloud data, need for data transparency and tracking, and ensuring data integrity. It proposes using JAR (Java Archive) files for data sharing due to benefits like portability. The framework incorporates client-side verification using MD5 hashing, digital signature-based authentication of JAR files, and use of HMAC to ensure data integrity. It also uses password-based encryption of log files to keep them tamper-proof. The framework is intended to provide both accountability and security for data sharing in cloud environments.
Genetic Algorithm based Layered Detection and Defense of HTTP BotnetIDES Editor
A System state in HTTP botnet uses HTTP protocol
for the creation of chain of Botnets thereby compromising
other systems. By using HTTP protocol and port number 80,
attacks can not only be hidden but also pass through the
firewall without being detected. The DPR based detection
leads to better analysis of botnet attacks [3]. However, it
provides only probabilistic detection of the attacker and also
time consuming and error prone. This paper proposes a Genetic
algorithm based layered approach for detecting as well as
preventing botnet attacks. The paper reviews p2p firewall
implementation which forms the basis of filtering.
Performance evaluation is done based on precision, F-value
and probability. Layered approach reduces the computation
and overall time requirement [7]. Genetic algorithm promises
a low false positive rate.
Enhancing Data Storage Security in Cloud Computing Through SteganographyIDES Editor
This document summarizes a research paper that proposes a method for enhancing data security in cloud computing through steganography. The method hides user data in digital images stored on cloud servers. When data needs to be accessed, it is extracted from the images. The document outlines the cloud architecture and security issues addressed. It then describes the proposed system architecture, security model, and data storage and retrieval process. Data is partitioned and hidden in multiple images to improve security. The goal is to prevent unauthorized access to user data stored on cloud servers.
The main tasks of a Wireless Sensor Network
(WSN) are data collection from its nodes and communication
of this data to the base station (BS). The protocols used for
communication among the WSN nodes and between the WSN
and the BS, must consider the resource constraints of nodes,
battery energy, computational capabilities and memory. The
WSN applications involve unattended operation of the network
over an extended period of time. In order to extend the lifetime
of a WSN, efficient routing protocols need to be adopted. The
proposed low power routing protocol based on tree-based
network structure reliably forwards the measured data towards
the BS using TDMA. An energy consumption analysis of the
WSN making use of this protocol is also carried out. It is
found that the network is energy efficient with an average
duty cycle of 0:7% for the WSN nodes. The OmNET++
simulation platform along with MiXiM framework is made
use of.
Permutation of Pixels within the Shares of Visual Cryptography using KBRP for...IDES Editor
The security of authentication of internet based
co-banking services should not be susceptible to high risks.
The passwords are highly vulnerable to virus attacks due to
the lack of high end embedding of security methods. In order
for the passwords to be more secure, people are generally
compelled to select jumbled up character based passwords
which are not only less memorable but are also equally prone
to insecurity. Multiple use of distributed shares has been
studied to solve the problem of authentication by algorithms
based on thresholding of pixels in image processing and visual
cryptography concepts where the subset of shares is considered
for the recovery of the original image for authentication using
correlation function[1][2].The main disadvantage in the above
study is the plain storage of shares and also one of the shares
is being supplied to the customer, which will lead to the
possibility of misuse by a third party. This paper proposes a
technique for scrambling of pixels by key based random
permutation (KBRP) within the shares before the
authentication has been attempted. Total number of shares to
be created is dependent on the multiplicity of ownership of
the account. By this method the problem of uncertainty among
the customers with regard to security, storage, retrieval of
holding of half of the shares is minimized.
This paper presents a trifocal Rotman Lens Design
approach. The effects of focal ratio and element spacing on
the performance of Rotman Lens are described. A three beam
prototype feeding 4 element antenna array working in L-band
has been simulated using RLD v1.7 software. Simulated
results show that the simulated lens has a return loss of –
12.4dB at 1.8GHz. Beam to array port phase error variation
with change in the focal ratio and element spacing has also
been investigated.
Band Clustering for the Lossless Compression of AVIRIS Hyperspectral ImagesIDES Editor
Hyperspectral images can be efficiently compressed
through a linear predictive model, as for example the one
used in the SLSQ algorithm. In this paper we exploit this
predictive model on the AVIRIS images by individuating,
through an off-line approach, a common subset of bands, which
are not spectrally related with any other bands. These bands
are not useful as prediction reference for the SLSQ 3-D
predictive model and we need to encode them via other
prediction strategies which consider only spatial correlation.
We have obtained this subset by clustering the AVIRIS bands
via the clustering by compression approach. The main result
of this paper is the list of the bands, not related with the
others, for AVIRIS images. The clustering trees obtained for
AVIRIS and the relationship among bands they depict is also
an interesting starting point for future research.
Microelectronic Circuit Analogous to Hydrogen Bonding Network in Active Site ...IDES Editor
A microelectronic circuit of block-elements
functionally analogous to two hydrogen bonding networks is
investigated. The hydrogen bonding networks are extracted
from â-lactamase protein and are formed in its active site.
Each hydrogen bond of the network is described in equivalent
electrical circuit by three or four-terminal block-element.
Each block-element is coded in Matlab. Static and dynamic
analyses are performed. The resultant microelectronic circuit
analogous to the hydrogen bonding network operates as
current mirror, sine pulse source, triangular pulse source as
well as signal modulator.
Texture Unit based Monocular Real-world Scene Classification using SOM and KN...IDES Editor
In this paper a method is proposed to discriminate
real world scenes in to natural and manmade scenes of similar
depth. Global-roughness of a scene image varies as a function
of image-depth. Increase in image depth leads to increase in
roughness in manmade scenes; on the contrary natural scenes
exhibit smooth behavior at higher image depth. This particular
arrangement of pixels in scene structure can be well explained
by local texture information in a pixel and its neighborhood.
Our proposed method analyses local texture information of a
scene image using texture unit matrix. For final classification
we have used both supervised and unsupervised learning using
K-Nearest Neighbor classifier (KNN) and Self Organizing
Map (SOM) respectively. This technique is useful for online
classification due to very less computational complexity.
In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
We will explore the capabilities of AI in understanding XML markup languages and autonomously creating structured XML content. Additionally, we will examine the capacity of AI to enrich plain text with appropriate XML markup. Practical examples and methodological guidelines will be provided to elucidate how AI can be effectively prompted to interpret and generate accurate XML markup.
Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
How to Interpret Trends in the Kalyan Rajdhani Mix Chart.pdfChart Kalyan
A Mix Chart displays historical data of numbers in a graphical or tabular form. The Kalyan Rajdhani Mix Chart specifically shows the results of a sequence of numbers over different periods.
Driving Business Innovation: Latest Generative AI Advancements & Success StorySafe Software
Are you ready to revolutionize how you handle data? Join us for a webinar where we’ll bring you up to speed with the latest advancements in Generative AI technology and discover how leveraging FME with tools from giants like Google Gemini, Amazon, and Microsoft OpenAI can supercharge your workflow efficiency.
During the hour, we’ll take you through:
Guest Speaker Segment with Hannah Barrington: Dive into the world of dynamic real estate marketing with Hannah, the Marketing Manager at Workspace Group. Hear firsthand how their team generates engaging descriptions for thousands of office units by integrating diverse data sources—from PDF floorplans to web pages—using FME transformers, like OpenAIVisionConnector and AnthropicVisionConnector. This use case will show you how GenAI can streamline content creation for marketing across the board.
Ollama Use Case: Learn how Scenario Specialist Dmitri Bagh has utilized Ollama within FME to input data, create custom models, and enhance security protocols. This segment will include demos to illustrate the full capabilities of FME in AI-driven processes.
Custom AI Models: Discover how to leverage FME to build personalized AI models using your data. Whether it’s populating a model with local data for added security or integrating public AI tools, find out how FME facilitates a versatile and secure approach to AI.
We’ll wrap up with a live Q&A session where you can engage with our experts on your specific use cases, and learn more about optimizing your data workflows with AI.
This webinar is ideal for professionals seeking to harness the power of AI within their data management systems while ensuring high levels of customization and security. Whether you're a novice or an expert, gain actionable insights and strategies to elevate your data processes. Join us to see how FME and AI can revolutionize how you work with data!
Your One-Stop Shop for Python Success: Top 10 US Python Development Providersakankshawande
Simplify your search for a reliable Python development partner! This list presents the top 10 trusted US providers offering comprehensive Python development services, ensuring your project's success from conception to completion.
Cosa hanno in comune un mattoncino Lego e la backdoor XZ?Speck&Tech
ABSTRACT: A prima vista, un mattoncino Lego e la backdoor XZ potrebbero avere in comune il fatto di essere entrambi blocchi di costruzione, o dipendenze di progetti creativi e software. La realtà è che un mattoncino Lego e il caso della backdoor XZ hanno molto di più di tutto ciò in comune.
Partecipate alla presentazione per immergervi in una storia di interoperabilità, standard e formati aperti, per poi discutere del ruolo importante che i contributori hanno in una comunità open source sostenibile.
BIO: Sostenitrice del software libero e dei formati standard e aperti. È stata un membro attivo dei progetti Fedora e openSUSE e ha co-fondato l'Associazione LibreItalia dove è stata coinvolta in diversi eventi, migrazioni e formazione relativi a LibreOffice. In precedenza ha lavorato a migrazioni e corsi di formazione su LibreOffice per diverse amministrazioni pubbliche e privati. Da gennaio 2020 lavora in SUSE come Software Release Engineer per Uyuni e SUSE Manager e quando non segue la sua passione per i computer e per Geeko coltiva la sua curiosità per l'astronomia (da cui deriva il suo nickname deneb_alpha).
Fueling AI with Great Data with Airbyte WebinarZilliz
This talk will focus on how to collect data from a variety of sources, leveraging this data for RAG and other GenAI use cases, and finally charting your course to productionalization.
Skybuffer SAM4U tool for SAP license adoptionTatiana Kojar
Manage and optimize your license adoption and consumption with SAM4U, an SAP free customer software asset management tool.
SAM4U, an SAP complimentary software asset management tool for customers, delivers a detailed and well-structured overview of license inventory and usage with a user-friendly interface. We offer a hosted, cost-effective, and performance-optimized SAM4U setup in the Skybuffer Cloud environment. You retain ownership of the system and data, while we manage the ABAP 7.58 infrastructure, ensuring fixed Total Cost of Ownership (TCO) and exceptional services through the SAP Fiori interface.
Introduction of Cybersecurity with OSS at Code Europe 2024Hiroshi SHIBATA
I develop the Ruby programming language, RubyGems, and Bundler, which are package managers for Ruby. Today, I will introduce how to enhance the security of your application using open-source software (OSS) examples from Ruby and RubyGems.
The first topic is CVE (Common Vulnerabilities and Exposures). I have published CVEs many times. But what exactly is a CVE? I'll provide a basic understanding of CVEs and explain how to detect and handle vulnerabilities in OSS.
Next, let's discuss package managers. Package managers play a critical role in the OSS ecosystem. I'll explain how to manage library dependencies in your application.
I'll share insights into how the Ruby and RubyGems core team works to keep our ecosystem safe. By the end of this talk, you'll have a better understanding of how to safeguard your code.
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2024/06/building-and-scaling-ai-applications-with-the-nx-ai-manager-a-presentation-from-network-optix/
Robin van Emden, Senior Director of Data Science at Network Optix, presents the “Building and Scaling AI Applications with the Nx AI Manager,” tutorial at the May 2024 Embedded Vision Summit.
In this presentation, van Emden covers the basics of scaling edge AI solutions using the Nx tool kit. He emphasizes the process of developing AI models and deploying them globally. He also showcases the conversion of AI models and the creation of effective edge AI pipelines, with a focus on pre-processing, model conversion, selecting the appropriate inference engine for the target hardware and post-processing.
van Emden shows how Nx can simplify the developer’s life and facilitate a rapid transition from concept to production-ready applications.He provides valuable insights into developing scalable and efficient edge AI solutions, with a strong focus on practical implementation.
Programming Foundation Models with DSPy - Meetup SlidesZilliz
Prompting language models is hard, while programming language models is easy. In this talk, I will discuss the state-of-the-art framework DSPy for programming foundation models with its powerful optimizers and runtime constraint system.
Building Production Ready Search Pipelines with Spark and MilvusZilliz
Spark is the widely used ETL tool for processing, indexing and ingesting data to serving stack for search. Milvus is the production-ready open-source vector database. In this talk we will show how to use Spark to process unstructured data to extract vector representations, and push the vectors to Milvus vector database for search serving.
Digital Marketing Trends in 2024 | Guide for Staying AheadWask
https://www.wask.co/ebooks/digital-marketing-trends-in-2024
Feeling lost in the digital marketing whirlwind of 2024? Technology is changing, consumer habits are evolving, and staying ahead of the curve feels like a never-ending pursuit. This e-book is your compass. Dive into actionable insights to handle the complexities of modern marketing. From hyper-personalization to the power of user-generated content, learn how to build long-term relationships with your audience and unlock the secrets to success in the ever-shifting digital landscape.
5th LF Energy Power Grid Model Meet-up SlidesDanBrown980551
5th Power Grid Model Meet-up
It is with great pleasure that we extend to you an invitation to the 5th Power Grid Model Meet-up, scheduled for 6th June 2024. This event will adopt a hybrid format, allowing participants to join us either through an online Mircosoft Teams session or in person at TU/e located at Den Dolech 2, Eindhoven, Netherlands. The meet-up will be hosted by Eindhoven University of Technology (TU/e), a research university specializing in engineering science & technology.
Power Grid Model
The global energy transition is placing new and unprecedented demands on Distribution System Operators (DSOs). Alongside upgrades to grid capacity, processes such as digitization, capacity optimization, and congestion management are becoming vital for delivering reliable services.
Power Grid Model is an open source project from Linux Foundation Energy and provides a calculation engine that is increasingly essential for DSOs. It offers a standards-based foundation enabling real-time power systems analysis, simulations of electrical power grids, and sophisticated what-if analysis. In addition, it enables in-depth studies and analysis of the electrical power grid’s behavior and performance. This comprehensive model incorporates essential factors such as power generation capacity, electrical losses, voltage levels, power flows, and system stability.
Power Grid Model is currently being applied in a wide variety of use cases, including grid planning, expansion, reliability, and congestion studies. It can also help in analyzing the impact of renewable energy integration, assessing the effects of disturbances or faults, and developing strategies for grid control and optimization.
What to expect
For the upcoming meetup we are organizing, we have an exciting lineup of activities planned:
-Insightful presentations covering two practical applications of the Power Grid Model.
-An update on the latest advancements in Power Grid -Model technology during the first and second quarters of 2024.
-An interactive brainstorming session to discuss and propose new feature requests.
-An opportunity to connect with fellow Power Grid Model enthusiasts and users.