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CHP 01
Basic Elements of OS
Instruction Execution
Instruction Cycle with Interrupts
Interrupt Processing
Interrupts
User
Program
WRITE
WRITE
WRITE
I/O
Program
I/O
Command
END
1
2
3
2
3
4
5
(a) No interrupts
= interrupt occurs during course of execution of user program
User
Program
WRITE
WRITE
WRITE
I/O
Program
I/O
Command
Interrupt
Handler
END
1
2a
2b
3a
3b
4
5
(b) Interrupts; short I/O wait
User
Program
WRITE
WRITE
WRITE
1
(c) Interrupts; lo
Figure 1.5 Program Flow of Control Without and With In
User
Program
WRITE
WRITE
WRITE
I/O
Program
I/O
Command
END
1
2
3
2
3
4
5
(a) No interrupts
= interrupt occurs during course of execution of user program
User
Program
WRITE
WRITE
WRITE
I/O
Program
I/O
Command
Interrupt
Handler
END
1
2a
2b
3a
3b
4
5
(b) Interrupts; short I/O wait
User
Program
WRITE
WRITE
WRITE
1
(c) Interrupts
Figure 1.5 Program Flow of Control Without and With
Memory Hierarchy
Cache Memory
CHP 02
The Operating System as a User/Computer Interface
A view of operating system services
The Operating System as Resource Manager
Typical process implementation
Key Elements of an Operating System for multiprogramming
Simple Batch Processing System
CHP 3
Process Control Block
Two-State Process Model
Queuing Diagram
c
Five State Process Model
Using Two Queues
One Suspend State
Multiple Blocked Queues
Two Suspend State
OS Control Tables
Structure of Process image in Virtual Memory
CHP 04
Single/Multithreaded
Single/Multithreaded Processes
Threads vs Processes
Types of Parallelism (Data and Task)
ULT, KLT & Combined
Relationships between ULT States and Process States
CHP 7
Addressing Requirements for a Process
Hardware Support for Relation
Process Control Block
Program
Data
Stack
Current top
of stack
Entry point
to program
Process control
information
Increasing
address
values
Branch
instruction
Reference
to data
Figure 7.1 Addressing Requirements for a Process
Process Control Block
Program
Data
Stack
Figure 7.8 Hardware Support for Relocation
Comparator
Interrupt to
operating system
Absolute
address
Process image in
main memory
Relative address
Base Register
Bounds Register
Adder
CHP 8
Address Translation in a Paging System
Use of a Translation Lookaside Buffer
Operation of Paging and Translation Lookaside Buffer

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DiagramsOS.pdf