computer organisation and architecture_ppt.pptx

COMPUTER ORGAN ISATION
AND
ARCHITECTURE
Course code : ACSC07
III semester
Regulation : UG -20
Prepared by
Dr.D.SREENIVASULU, Asst.Professor
DEPARTMENT OF CSE (DATA SCIENCE)

COMPUTER ORGANISATION AND ARCHITECTURE
MODULE–1
INTRODUCTION
TO
COMPUTER ORGANISATION

COMPUTER ORGANISATION AND ARCHITECTURE
COMPUTER ORGANISATION AND ARCHITECTURE :
COMPUTER ORGANISATION :
Computer Organisation is the way how the Hard ware components
connected and operated together to form a computer system
COMPUTER ARCHITECTURE :
Computer Architecture is the structure and behaviour of a computer
system .It includes data formats , instruction set and techniquies for
addressing memory

CONTENTS
 Basic Computer organization
 CPU organization
 Memory sub system organization and interfacing
 Input / Output sub system organization and interfacing
 Simple computer levels of programming languages
 Assembly language instructions
 Instruction set architecture design
 Simple Instruction set architecture

GENERATIONS OF COMPUTERS
First Generation :
 These generation computers were introduced in the year 1940 - 1956
 The devices used used in this generation is vacuum tubes for
circuitry and magnetic drums for memory .
 These computers were very expensive to operate and generated a lot
of heat, which was often the cause of malfunctions.
 First generation computers relied on machine language, understood
by computers, to perform operations
 Input was based on punched cards and paper tape, and output was
displayed on printouts.
 The examples of first generation computers are UNIVAC1

Second Generation :
 These Generation computers were introduced in the year
1956 - 1956
 The transistors replace vacuum tubes in the second generation of
computers.
 The transistor was invented at Bell Labs in 1947 but did not see
widespread use in computers until the late 1950s.
 The transistor were smaller, faster, cheaper, more efficient and
reliable than their first-generation predecessors.
 Second-generation computers still relied on punched cards for input
and printouts for output.
 The examples of first generation computers are IBM 7090

Third Generation:
 These Generation computers were introduced in the year
1956 - 1956
 The development of the integrated circuit was the hallmark of the
third generation of computers.
 Transistors were miniaturized and placed on silicon chips, called
semiconductors, which drastically increased the speed and efficiency
of computers.
 Instead of punched cards and printouts, users interacted with third
generation computers through keyboards and monitors and
interfaced with an operating system
 The examples of first generation computers are IBM 360

Fourth Generation:
 These Generation computers were introduced in the year1972
onwards
 The microprocessor brought the fourth generation of computers, as
thousands of integrated circuits were built onto a single silicon chip.
 The Intel 4004 chip, developed in 1971, located all the components
of the compute from the central processing unit and memory to
input/output controls on a single chip.
 In 1981 IBM introduced its first computer for the home user, and in
1984 Apple introduced the Macintosh.
 Microprocessors also moved out of the realm of desktop computers
and into many areas of life as more and more everyday products
began to use microprocessors.

Fifth Generation: Artificial Intelligence (Present and Beyond)
 Fifth generation computing devices, based on (AI)artificial
intelligence, are still in development, though there are some
applications, such as voice recognition , that are being used today.
 The use of parallel processing and superconductors is helping to
make artificial intelligence a reality.
 Quantum computation and molecular and nanotechnology will
radically change the face of computers in years to come.

TYPES OF COMPUTERS
TYPES OF COMPUTERS :
Based on size and power the computers are classified into four types
namely
1. Micro computers
2. Mini computers
3. Main Frame computers
4. Super computer
1.MICRO COMPUTERS :
 Micro computers are also known as personal computers. These
computers are small in size and less in expensive cost.
 It has low computing power and only one person can use one
system at a time
 Examples of Micro computers are Desk tops , Lap-tops and Tablets

TYPES O F COMPUTERS
MINI COMPUTERS :
 Mini computers are medium in size and cost.
 These computers are easy to use and it uses multi user environment
and normally 10 to 16 users can work at a time.
 These computers are used in small business applications in our daily
life. :
 Examples of these computer are VAX
MAIN FRAME COMPUTERS :
 Main Frame computers are large in size and high cost .
 These computers are used in large Business organisations and
Universities
 These systems are multi user systems and nearly 100 users can work
at a time.

TYPES O F COMPUTERS
SUPER COMPUTERS :
 Super Computers are fastest and high expensive computers
 These computers having high computing power.
 Used in very large organisations like weather fore casting and
space explorations.
 Examples of the computers are PARAM ,CRA and SUMMIT.

Contents
Basic computer organization :
• CPU organization
• Memory subsystem organization and interfacing
• Input or output subsystem organization and interfacing
• A simple computer levels of programminglanguages
• Assembly language instructions
• A simple instruction setarchitecture.

BASIC COMPUTER ORGANIZATION
BASIC COMPUTER ORGANIZATION :
The basic computer organization has three main components:
1. CPU 2. Memory Unit 3. I/O Unit

CENTRAL PROCESSING UNIT (CPU) :
Central processing unit has two units
1.Control Unit and 2. ALU
CONTROL UNIT :
The control unit co-ordinates the the following information
 Stores the information in Memory.
 Processes the information in ALU.
 Provides the results through the output units .
 Control unit also generates a signal for the system control bus
such as read , write and I/O signals.
 The control unit controls the CPU and it receives the data from
the register unit which generates the control signal
ALU :
 The ALU performs the arithmetic operations add,sub,mul,div etc
 Logical operations like AND , OR , and NOT operations

MEMORY UNIT :
 Memory is an important unit in computer organisation . It is used
to store the data and the program instructions.
 Computer memory consist of different types of memories organised
in a hierarchy order.
 The memory is mainly divided into two basic types based on the
data retention.
1. Primary memory or Main memory
2. Secondary Memory or Auxilary memory
PRIMARY MEMORY :
 This memory is also known as main memory and is retained the
data When the computer system is on.Once the system is switched
off the data will be lost.This memory is referred as volatile or
temporary memory.
Ex : RAM , Cache memory.

SECONDARY MEMORY :
 The secondary memory is also called as Auxilary memory and
is Used to store the data permanently . It retains the data even
the system is switched off. This memory is referred permanent
or Non-volatile memory.
EX : CD-ROM Disks ,Pen Drives ,Hard Disks.
RAM ( RANDAM ACCESS MEMORY ) :
 This memory often referred to as read/write memory. Unlike
the ROM it initially contains no data.
Types of RAM’s :
Dynamic RAM :
 Initially data is stored in the DRAM chip, charging its memory
cells to their maximumvalues.
Static RAM :
 In Static RAM Once the data is written to SRAM, its contents
stay valid it does not have to be refreshed.

Static RAM is faster than DRAM but it is also much more expensive.
Cache memory in the personal computer is constructed from SRAM.
ROM (READ ONLY MEMORY) :
 ROM is programmed with data as chip isfabricated.
Types of ROM’S :
PROM :
Program has been written onto a PROM, it remains there
for ever.
PROM is a memory chip on which data can be written only
EPROM :
In EPROM the stored data to be erased and new data to be loaded.
Such an erasable reprogrammable ROM is usually called an EPROM..
The chip is erased by being placed under UV light, which causes the
capacitor to leak their charge.

EEPROM :
 EEPROM memory is one that can have both programmed and
erased eclectically, such chips called EEPROM.
 The only disadvantage of EPROM is that different voltages are need
for erasing ,writing ,reading and stored data.
FLASH MEMORY :
 A special type of EEPROM is called a flash memory.It is electrically
erase data in blocks rather than individuallocations.
 It is well suited for the applications that writes blocks of data and
can be used as a solid state hard disk. It is also used for data storage
in digital computer

Input :
 The main function of the input unit is to provide data that will be
operated by the CPU as per program instruction.
 The computer system can accept the input from the input device
connected to the computer system.
Output :
 The main function of the out put unit is to present the
data to the user and processed by the CPU as per program
instruction.

BUS SYSTEM :
 A Bus consisting of a set of wires . The components of the
computer system connected to the wires.
 A bus system is the communication system that transfers data
between all the major components of the system.
 To send the data or information through buses. There are 3 types of
buses used namely
1. Address bus 2.Data bus 3. Control bus
 Data bus is used to transfer data between the various
components in a computer system.
 When the computer components wants to access some particular
memory location , it places the corresponding address on the
address bus.

 The control bus is the collection of signals that control how the
processor communicates with the rest of the system.
 The read and write control lines control the direction of data on
the databus.

LIST OF REGISTERS :

CPU ORGANIZATION
Accumulator (AC ) :
 An accumulator is a register for short-term, intermediate storage
of arithmetic and logic data in a computer's central processing
unit.
 In a modern computers, any register can function as an
accumulator.
Program Counter (PC) :
 Program Counter is a CPU register that holds the address of the
next instruction to be read from RAM memory after the current
instruction is executed.
 As each instruction gets executed, the program counter
increments its stored value by 1. After each instruction is fetched,
the program counter points to the next instruction in the
sequence.

Memory subsystem organization
Computer memory hierarchy :
 In a computer system , different types of memories are
used.These memories are organisedin hierarchy order to
optimise the CPU performence.This is called the memory
hierarchy.

Memory Sub-System Organisation

Instruction Format
Instruction Format :
 Computer programs are written in High Level Language , the
CPU can decode and execute machine instructions in Binary
Format.
 During compilation process , the compiler converts the High
Level Program instructions into low level machine instructions in
a specific format. This machine instruction format is defined as
instruction format.
 The instruction format is simply sequence of binary bits 0 and 1
contained in machine instruction. These bits are grouped
together called fields.

Instruction format
Standard Instruction format

Instruction format
 Address Mode :
Data operated by the CPU stored in main memory .It is located in
CPU registers . It is located in 16th bit of 16 bits register.
 OP Code mode :
During program execution , the instruction is placed in
instruction register. Op code is represented in 12th,13th,14 th
bits of 16 bits register.
 Operand mode :
Operand mode specifies the address of data operated by the
processor . It is located in 1st to 11th bits of 16 bits register.

Instruction cycle
Instruction cycle :
 The main function of CPU is to execute the program . The computer
program consists of a number of instructions
 In order to execute the program the operating system allocates
necessary resources.
 The CPU initiates the program execution by fetching the data and
instruction from the main memory RAM. This CPU mechanism is
called instruction cycle.
 Simply the instruction cycle is the time required by the CPU to
execute one single program instruction.

Instruction cycle
Instruction register (IR) :
 Holds the instructions that are currently being executed. Its
output is available for the control circuits which generates the
timing signals that control the various processing elements in
one execution of instruction.
Program Counter (PC) :
 This is another specialized register that keeps track of execution
of a program. It contains the memory address of the next
instruction to be fetched and executed.
The other two registers which facilitate communication with
memory are: -
Memory Address Register (MAR):
 It holds the address of the location to be accessed.
Memory Data Register (MDR):
 It contains the data to be written into or read out of the
address location.

 Computer programming languages are divided into 3categories.
 High level language
 Assembly level language
 Machine level language
 High level languages are platform independent that is these programs
can run on computers with different microprocessor and operating
systems without modifications. Languages such as C++, Java and
FORTRAN are high level languages.
 Assembly languages are at much lower level of abstraction.Each
processor has its own assembly language
 The lowest level of programming language is machine level
languages. These languages contain the binary values that cause the
microprocessor to perform certain operations. When microprocessor
reads and executes an instruction it's a machine language
instruction.
A Simple Computer- Levels of PL

Figure 1.8: Levels of programminglanguages

 High level language programs are compiled and assembly level
language programs are assembled.
 A program written in the high level language is input to thecompiler.
 compiler checks to make sure every statement in the program is valid.
When the program has no syntax errors the compiler finishes the
compiling the program that is source code and generates an object
code file.
 An object code is the machine language equivalent of
source code.
 A linker combines the object code to any other object
code. This combinedcode stores in the executable file.

 Programmers don't written the programs in machine language
rather programs written in assembly or high level are the
converted into machine level and then executed by
microprocessor.
 High level language programs are compiled and assembly level
language programs are assembled.
 A program written in the high level language is input to the
compiler
. The compiler checks to make sure every statement in the
program is valid. When the program has no syntax errors the
compiler finishes the compiling the program that is source code
and generates an object code file.
 An object code is the machine languageequivalentof source code.
 Alinkercombines the object code to any other object code.
 This combined code storesin the executable file.

 Instructiontypes :
• Assembly languages instructions are grouped
together based on the operation they performed
• Data transferinstructions
• Data operational instructions
• Program control instructions
 Data transfer instructions
 Load the data from memory into the microprocessor:
• These instructions copy data from memory into a
microprocessor register.
 Store the data from the microprocessor into the memory:
• This is similar to the load data expect data is copied in the
opposite direction from a microprocessor register to memory.
Assembly Language Instructions

Basic operational Concepts
An Instruction consists of two parts, an Operation code and
operand/s as shown below:
1. OPERAND/s
2. OPCODE
Let us see a typical instruction
ADD LOC A, R0
This instruction is an addition operation. The following are the steps
to execute the instruction :
Step 1: Fetch the instruction from main memory into the processor
Step 2: Fetch the operand at location LOC A from main memory
I in to the processor
Step 3: Add the memory operand (i.e. fetched contents of LOC A)
to the contents of register R0.
Step 4: Store the result (sum) in R0.

The same instruction can be realized using two instructions as
Load LOC A, R1
Add R1, R0
The steps to execute the instructions can be enumerated as below:
Step 1 : Fetch the instruction from main memory into the processor
Step 2 : Fetch the operand at location LOC A from main memory into
the processor Register R1
Step 3 : Add the content of Register R1 and the contents of
register R0
Step 4 : Store the result (sum) in R0.

Instruction Set Architecture
The Instruction Set Architecture (ISA) :
The ISA is the part of the processor. It serves as the boundary
between software and hardware. The ISA of a processor can be
described as five catagories.
 Operand Storage in the CPU
 No. of explicit named operands
 Operand location
 Operations
 Type and size of operands

Types of Instruction Set Architecture :
The three most common types of ISA’s are:
 Stack :
The operands are implicitly on top of the stack.
 Accumulator :
One operand is implicitly the accumulator.
 General Purpose Register (GPR) :
All operands are explicitly mentioned, they are either
registers or memory locations.

Let us consider the assembly code of C = A + B ;
in all three architectures are :
The i8086 has many instructions that use implicit operands
although it has a general register set.
STACK ACCUMULATOR GPR
PUSH A LOAD A LOAD R1,A
PUSH B ADD B ADD R1,B
ADD STORE C STORE R1,C
POP C -- --

STACK
 Advantages :
Simple Model of expression evaluation . Short instructions.
 Disadvantages:
A stack can't be randomly accessed . It itself is accessed every
operation
ACCUMULATOR
 Advantages :
Short instructions.
 Disadvantages :
The accumulator is only temporary storage so memory traffic is
the highest for this approach.

GPR
 Advantages:
1. Makes code generation easy.
2.Data can be stored for long periods in registers.
 Disadvantages:
1.All operands must be named leading to longer instructions.

MODULE-II
ORGANIZATION OF A COMPUTER

Course outcomes
The course should enable the students to:
CO2 Recall different number systems, binary addition and
subtraction, 2’s complement representation for the usage of
instructions in digital computers.
CO3 Explain the register transfer language; register transfer, bus
and memory transfer for implementation of micro
operations.

JUSTIFICATIONS FOR CO-PO MAPPING:
Course
Outcomes
(COs)
POs /
PSOs
Justification for mapping (Students will be able
to)
CO2
PO 1 Illustrate the arithmetic formulate (knowledge) of
instructions used in digital computers by applying the
principles of mathematics and science for solving complex
engineering problems.
PO 2 Understand the given arithmetic functions and formulate
to the organization of computer using principles of
mathematics and engineering science
PSO1 Illustrate the concept of number system for obtaining of
digital data to build the embedded system

Course
Outcomes
(COs)
POs /
PSOs
to)
CO3 PO 1 Apply (knowledge) the register transfer language, bus and
memory transfer characteristics for implement the micro
operations by analyzing complex engineering problems
using the principles of mathematics, engineering science.
PO 2 Understand the register transfer language bus and
memory transfer problem statement and finding the
solution implementation of micro operations by analyzing
complex engineering problems
PSO1 Understanding the register transfer language for
developing the processor in embedded technology

Contents
Register transfer :
• Register transfer language
• Register transfer
• Bus and memory transfers
• Arithmetic micro operations
• Logic micro operations
• Shift micro operations
Control unit :
• Control memory
• Address sequencing
• Micro program example and
• Design of control unit.

Register Transfer
Terminology
Digital system :
 A Digital system is an interconnection of digital hardware
modules
 These modules are constructed from the digital componets
such as ALU ,control unit , registers and decoders.
 These are inter connected with common data and control path
to form a digital computer system.

Register Transfer Language ( RTL )

Register Transfer
Basic Symbols for Register Transfers
Symbol Description Examples
Letters &
numerals
Denotes a register MAR, R2
Parenthesis ( ) Denotes a part of a
register
R2(0-7), R2(L)
Arrow ← Denotes transfer of
information
R2 ← R1
Comma , Separates two micro
operations
R2 ← R1, R1 ← R2

Bus Transfer
Bus Transfer :
 A Digital system composed of many registers and the information
is transfer from register to another through paths.
 The path is the number of wires connecting to all the registers.
Separate lines are used for each register so excess number of
wires are required to connect each register . In order to avoid the
excessive usage of wires a Common Bus System is used.
 A Bus structure or common bus structure is more efficient for
transferring information between the registers.
 Control signals determines which register is selected by the bus
during register transfer.

Bus Transfer
 There are two ways of constructing a common bus system.
1. Using Multiplexers
2. Using Tri – State Buffers
Multiplexers :
 A Multiplexer is combinational circuit that selects binary
information from one of many inputs and directs it to a single
out put line . The selection of a particular input connected by a
set of selection lines.
 Multiplexers in common bus system selects one of many
registers whose binary information is placed on the bus using
select inputs.

Memory Transfer
Memory Transfer Operations :
Standard Notations :
 Data being read or write is called as memory word (M)
 The address of memory word (M) is specified by
enclosing the address in square brackets followed by
letter M.
Ex : M [AR ]
Where AR = Address Register.

Binary Adder :
 The digital circuit that performs the arithmetic sum of two bits is
called half adder.
 The digital circuit that performs the arithmetic sum of three bits
is called full adder
 The digital circuit that generates the arithmetic sum of two
binary numbers of any length is called a binary adder.
 The binary adder is constructed with full adder circuits
connected in cascade , with the out put carry from one full
adder connected to the input of the next full adder.
 An n bit binary adder requires n full adders.
Arithmetic Micro operations

Binary Adder :
Fig : 4-bit binary adder

Binary Adder / Subtractor :
 The Binary Adder / Subtractor circuit performs two operations
addition and subtraction.
 The F A circuit has three inputs . First input from A0 ,second is
Bo and third is a carry input Co.
 The EX-OR gate has two inputs Bo and M . Bo is register input
and M is mode bit .It has two values either 1 or 0 , If M is 1 , the
circuit is a Subtractor and M is 0 , the circuit is an Adder.

Binary Incrementer :
The Binary Incrementer micro operation increments the
contents of the register by one using a binary counter. is
implemented by using half adders.
One of the inputs to the least significant half adder (HA)
is connected to logic-1 .
The output carry from one half adder is connected to one
of the inputs of the next-higher-order half adder.
The generated out put is displayed in s0 through s3.
This circuit can be implemented to n-bit binary
incermenter by including n-half adders.

x y
H A
C S
S0
x y
H A
C S
x y
H A
C
x y
H A
C S
Binary Incrementer :
A3 A2 A1 A0 1
Fig : 4- bit binaryIncrementer
S3
C 4 s1
s2

4-bit arithmetic Circuit :
 4-bit arithmetic circuit is used to perform all seven arithmetic
operations.
 This circuit contains 4 full adders and 4 multiplexers to choose
different operations.
 There are two 4-bit inputs A and B and a output D.
 The four Inputs from A connected to Adder and the B input is
given to input of Multiplexers.
 The multiplexers data also receives the complement of B .
 The remaining two data inputs are connected to the Logic-0
and logic 1.
 The four multiplexers are controlled by two selection inputs
S1 and S0.

Arithmetic Circuit
Fig: 4-bitArithmeticcircuit

Arithmetic Circuit
 The input carry Cin goes to the carry input of the FA in the
least significant position .
 The other carries a connected from one stage to the next.
 The output of the Binary Adder is calculated by using Arithmetic sum
D= A+Y+Cin here A is 4-bit Binary number at X inputs.
 Y is 4-bit binary number at Y inputs of the binary adder.
 Cin is the input carry.
 In the above equation by controlling the value of Y with two control
inputs S1 and S0 and making the Cin 1 or 0 the above circuit performs
all the arithmetic operations.

Arithmetic Circuit
Table : Arithmetic Circuit Functiontable

Logic Micro operations
 Logic micro operations specify the operations for strings of bits
stored in registers .
 Logic microoperations are bit-wise operations, i.e., they work on
the individual bits of data.
 The logic microoperation exclusive-OR with the contents of two
registers R1 and R2 is symbolized by the statement:
P : R1 R1 R2
Ex: R1=1010 R2=1100
if P=1 then
1010 =R1
1100 =R2
0110 =R1 after P=1

List of Logic Microoperations
 There are 16 different microoperations that can be
performed with two binary operations.
 Most of the systems implement four of these ^,V, and .
Table :Truth Table for 16 functions of TwoVariables
X Y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Table : 16 Microoperations

Hardware Implementation
 Toimplement these micro operations it uses Logic gates.
 Most of the computers implement only four functions like AND , OR,
NOT and XOR .

Logic Microoperations
Applications :
 Logic microoperations can be used to manipulate individual bits or
a portions of a word in a register
 There are Six applications of logic micro operations namely
• Selective set
• Selective complement
• Selective clear
• Mask (Delete)
• Insert
• Clear

Selective Set :
 If the bits in register B is 0 , then there is no need to change the
bits in Register A .
 If the bits in register B is 1 , then the corresponding bits in
Register A is set i.e 1 .
1 0 1 0 A ( before)
1 1 0 0 B ( logic operand)
1 1 1 0 A (after)
 The OR microoperation is used to perform the selective set
of bits in register.

Selective Complement :
bits in register A .
register A is complemented.
1 0 1 0 A ( A before )
1 1 0 0 B (Logic Operand)
0 1 1 0 A (A after)
`
 The EX-OR micro operation is used to selective complement bits
of register.

Selective Clear :
bits in register A .
register A is clear state.
1 0 1 0 A ( Abefore)
1 1 0 0 B ( Logical Operand )
0 0 1 0 A ( After )
 The Boolean operation performed on the individual bits in AB'.

Mask :
 If the bits in register B is 1 , then there is no need to change the bits
in register A .
register A is masked i.e cleared.
1 0 1 0 A ( Before )
1 1 0 0 B ( Logical operand )
1 0 0 0 A ( After)
 The AND micro operation is used to perform the mask operation in
order to make the bits zero.

Insert :
 An insert operation is used to introduce a specific bit pattern into
A register, leaving the other bit positions unchanged
 This is done as a mask operation to clear the desired bit positions,
followed by
 An OR operation to introduce the new bits into the desired positions
 Example Suppose you wanted to introduce 1010 into the low order
four bits of A . 1010 1100 A ( Original )
0011 1100 A ( Desired )
1010 1100
0000 1111 ( Mask )
0000 1100
0011 0000 ( OR )
0011 1100 ( Desired )

Clear :
 The Clear operation compares the words in A and B and produces an
all 0's result if the two numbers are equal.
 This operation is achieved by exclusive-OR operation.
1 0 1 0 A ( Before )
1 1 0 0 B
0 1 1 0 A
( Logic Operand )
( After )

SHIFT MICROOPERATIONS
 Shift micro operations are used to shift the contents of the register
either from left to right or from right to left.
 During shift left serial input transfers a bit towards right side.
 During shift right serial input transfers a bit towards left side. The
information transferred through the serial input determines thetype
of shift.
 There are 3 types of shifts
 Logical shift
 Circular shift
 Arithmetic shift

Shift Microoperations
 Notations used to denote logical shift microoperationsare:
shl ----> For logical shift left
shr ----> For logical shiftright
Examples :
R2  shl R2 R3  shr R3
Circular Shift Micro operations :
 In a circular shift the serial input bit is shifted out of the other end
of the register. There are two types of circular shift operations
 1.Circular Shift right operation
 2. Circular Shift left operation

 Circular shift right operation:
 Circular shift left operation:
 In a RTL, the following notation is used
– cil
– cir
for a circular shift left
for a circular shiftright
Examples:
• R2  cir R2 R3  cil R3

Arithmetic Shift :
 An arithmetic shift is meant for signed binary numbers (integer)
 An arithmetic left shift multiplies a signed number by two
 An arithmetic right shift divides a signed number by two
Arithmetic shift right operation:
Arithmetic shift left operation:
0
n
sig
bit
n
sig
bit

Shift Micro operations
In a RTL, the following notation is used
– Ashl for an arithmetic shift left
– Ashr for an arithmetic shift right
Examples:
• R2  ashr R2
• R3  ashl R3

4-bit CombinationalShifter

Table : Function Table
 When S=1 the input data is shifted to left
 When s=0 the input data is shifted to right.

Arithmetic Logic Shift Unit
 All the three operations are implemented with a single circuit.
• Fig:One stage of ALSUnit

Arithmetic Logic Shift Unit
Function Table forArithmetic Logic shift unit

Control Unit
Control Memory
 A Memory is a part of the control unit is known as control
memory which is programmed to initiate the sequence of micro
operations
 This memory is assumed as Read only memory (ROM ) in which
the control information is permanently stored. Every word in
ROM address specifies a micro instruction.
 Every micro instruction contains two category of bits
1. Control bits - initiates the micro operation
2. Special bits - determines the address of next micro instruction.

Control Memory
Micro programmed control organisation
The general configuration of micro programmed control unit
is given below
Fig : Microprogrammed Control Unit

Control Memory
1. Control Address Register :
The Control memory address register specifies the address of the
micro instruction.
2. Control Data register :
The Control data register holds the micro instruction read from
memory .It includes two categories of bits namely
1. control bits 2. special bits
The control data register allows the execution of the micro
operation specified by the control word with the generation of the
address of the next micro instruction . This register is also called as
the pipeline register.

Control Memory
3. Control Memory ( ROM ) :
Micro Programs are stored in control memory register.Here the control
memory is designated as ROM .There fore it is not possible to perform
any modifications on control unit .
4. Micro Program Sequencer ( Next Address Generator circuit ) :
This circuit computes the address of the next micro instruction with the
special bits of micro instruction received from control memory.
The functions of micro program sequencer are incrementing the control
address register by one.

Address Sequencing
Address Sequencing :
In a given micro instruction certain bits are used to initiate the micro
operation and the remaining bits are used to generate the address of
the next micro instruction .This process is called as Address
Sequencing.
This sequencing is used to generate the next micro instruction address.
There are four approaches used in address sequencing.
1. Control Address Register ( CAR )
2. Sub routine Register (SBR )
3. Branch Logic
4. Mapping Logic

Address Sequencing
1. Control Address Register ( CAR ) :
 For every micro instruction there will be an address
 Control Address Register is a register that stores the first micro
instruction address.
 Once first micro instruction is executed, CAR value gets
incremented by 1.This is called as address sequencing.
2. Sub routine Register (SBR ) :
 Sub routine contains a collection of micro instructions which are
used to perform the specific task.
 After completing the task the control transfers to next instruction
The next instruction will be stored in sub routine register.

Address Sequencing
3.Branch Logic :
This login can be performed in two ways
1. Conditional branch 2. unconditional branch
 In conditional branch , the condition is checked .If the condition is
satisfied then load the address to CAR .Here select the status bit
and branch logic.
 In unconditional branch without checking the condition ,the
corresponding address is loaded into the CAR.
4. Mapping Logic :
 Mapping process is used when branch to micro program routine of
the micro operation.

Subroutines
 Subroutines are programs that are used by other routines to
accomplish a particular task. A subroutine can be called from
any point within the main body of the micro program.
 Frequently, many micro programs contain identical sections of
code. Microinstructions can be saved by employing
subroutines that use common sections of microcode.
 For example, the sequence of microoperations needed to
generate the effective address of the operand for an
instruction is common to all memory reference instructions.
Address Sequencing

 This sequence could be a subroutine that is called from
within many other routines to execute the effective address
computation.
 Micro programs that use subroutines must have a provision
for storing the return address during a subroutine call and
restoring the address during a subroutine return.
Address Sequencing

Design of Control Unit
Control Unit is designed in two ways
1. Hard wired control 2. Micro program control
 Hard wired control means the control logic is implemented
with the help of hard ware components like gates decoders .
 Micro program control means the control logic is implemented
with the help of software or a program.
 Micro Program is the collection of micro instructions. Each
instruction contains three micro operation fields F1,F2 , F3 of
three bits size.F1 represents arithematic circuit ,F2 represents
Logic circuit and F3 represents the shift circuit.

 The control memory is included in the diagram to show the
interaction between the sequencer and the memory attached
to it.
 There are two multiplexers in the circuit. The first multiplexer
selects an address from one of four sources and routes it into
a control address register CAR .

 The input logic circuit in Fig. has three inputs, l0, l1, and T, and
three outputs, S0, S1, and L.Variables So and S, select one of
the source addresses for CAR .
 Variable L enables the load input in SBR. The binary values of
the two selection variables determine the path in the
multiplexer.

MODULE-III
CPU AND COMPUTER ARITHMETIC

Course outcomes
CO4 Analyze cost performance and design trade-offs in designing
and constructing a computer processor including memory.
CO5 Demonstrate computer architecture concepts related to
design of modern processors, memories and I/Os used for
implementation of specific applications
CO6 Estimate the performance of various classes of machines,
memories, pipelined architectures etc. for high throughput
network processors.
CO7 Illustrate the basics of hardwired and micro-programmed
control of the CPU which generates the control signals to
fetch and execute instructions

Course
Outcomes
(COs)
POs /
PSOs
to)
CO4 PO 1 Analyze (understand) the cost performance and design
trade-offs for computer architecture by applying the
principles of science for engineering problems.
CO5 PO 1 Determine (understand) the computer architecture
concepts (knowledge) from their characteristics by
applying the principles of science for engineering
problems.
CO6 PO 1 Analyze (Understand) the various classes of machines,
memories architecture and performance by applying the
principles of mathematics, science to the solutions of
complex engineering problems.
PO 2 Understand the input and output characteristics of
architecture for problem formulation to determine
modern processors and memories using mathematics
principles.

Course
Outcomes
(COs)
POs /
PSOs
to)
CO7 PO 1 Illustrate characteristics of hardwired and micro-
programmed control of the CPU for solving complex
engineering problems generates control signals by
applying mathematics, science and engineering
fundamentals.
PO 2 Analyze execute instruction problem statements control
signals using mathematics principles.

Contents
CPU design:
• Instruction cycle
• Data representation
• Memory reference instructions
• Input-output and interrupt
• Addressing modes
• Data transfer and manipulation
• Program control.
Computer arithmetic:
• Addition and subtraction
• Floating point arithmetic operations
• Decimal arithmetic unit.

Instruction Cycle
Instruction Cycle :
 Each program consisting of sequence of instructions.
 The CPU initiates the program execution by Instruction Cycle fetching
the data and instruction from the main memory . This CPU
mechanism is called instruction cycle.
 In basic computer system, each instruction is subdivided into Four
phases:
1. Fetch an Instruction from memory.
2. Decode the Instruction.
3. Read the effective address from the memory if
the instruction has an indirect address.
4. Execute the Instruction.

Instruction Cycle
Fetch and Decode
 Initially the program counter PC is loaded withthe address of the
first instruction.

Instruction Cycle
Fig: Register Transfer for the fetchphase

Instruction Cycle
 In the above diagram shows the transfer of first two
statements(T0 and T1).
 When timing signal T0=1then Place the contents of PC onto the bus
by making the bus selection inputs S2S1S0 equal to 010.
 Transfer the contents of the bus to AR by enabling the LD input of
AR.
 When timing signal T1=1 then Enable the read input ofmemory.
 Place the contents of Memory onto the bus by makingS2S1S0=111.
 Transfer the contents of the bus to IR by enabling the LD input of IR.
 Increment PC by enabling the INR input ofPC.

Instruction Cycle
Determine the Type of Instruction
 After executing the timing signal T1 the control unit determines the
type of instruction that is read frommemory.
 If D7=1 and the instruction must be a register-reference or input-out
type.
 If D7=0 the operation code must be one of the other seven values 000
through 110 specifying a memory –referenceInstruction.
 The symbolic representation is :
D'7IT3 :
D'7I'T3 :
D7I'T3 :
D7IT3 :
AR M[AR]
Nothing
Execute a register-reference instr.
Execute an input-output instr.

Instruction Cycle
Fig : Flowchart for InstructionCycle

Memory-Reference Instructions
Basically Computer uses three types of instructions namely
1. Memory Reference Instructions
2. Register Reference Instructions
3. I/O Reference Instructions
Memory Reference Instructions :
 Instruction Format of Memory Reference Instruction is as shown
below.
15 14 12 0
I=0 Direct
I=1 Indirect
It is a 16 bit instruction register
0 – 11 - represents the address of the instruction
11 – 14 - represents the OP – CODE and holds Data lines D0 – D6
15 - represents the Direct or Indirect address
I OP-CODE ADDRESS

Memory-Reference Instructions
Fig: Flowchart for Memory Reference Instructions

INSTRUCTION CYCLE
Instruction Cycle :
 Each program consisting of sequence of instructions.
 The CPU initiates the program execution by Instruction Cycle
fetching the data and instruction from the main memory . This CPU
mechanism is called instruction cycle.
 In basic computer system, each instruction is subdivided into Four
phases:
1. Fetch an Instruction from memory.
2. Decode the Instruction.
3. Read the effective address from the memory if
the instruction has an indirect address.
4. Execute the Instruction.

Decimal Number System :
– The decimal number system in every day use employs the radix
10 system.
– The 10 symbols are 0,1,2,3,4,5,6,7,8 and 9.
– The string of digits 834.5 is interpreted
as: 8X102 + 3X101 + 4X100+5X10-1 =834.5
Binary Number System :
– Binary number system uses the radix 2.
– The two digit symbols used are 0 and 1.
– The string of symbols 1001 is interpretedas:
1 x 23 + 0 x 22 + 0 x 21 + 1x 20 =8+0+0+1=9
DATA REPRESENTATION

Octal Number System :
 Octal Number System uses radix 8.
 The Symbols used to represent the octal number system
is 0,1,2,3,4,5,6 and 7.
 The octal number is converted into decimal number system
by forming the sum of the weighted digits.
 Ex:
(736.4) 8= ?
= 7 x 82 + 3 x 81 + 6 x 80 +4 x 8-1
= 7 x 64 + 3 x 8 + 6 x 1 + 4/8 =(478.5)10
Data Representation

Hexadecimal Number System :
– The hexadecimal number system uses radix16.
– The symbols used to represent the hexadecimal numbersystem is
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E and F.
– The hexadecimal number is converted into decimal system
by forming the sum of the weighted digits.
Ex:
(F3)16 = ?
= F x 161 + 3 x160
= 15 x 16 + 3=(243)10
Data Representation

Decimal to Other Number Systems :
 Conversion from decimal to its equivalent representation in the
radix r system is carried our by separating the number into its
integer part and fraction part and converting each partseparately.
 The conversion of a decimal integer into a base r representation is
done by successive divisions by r and accumulation of the
reminders.
 The conversion of a decimal fraction to radix r representation is
accomplished by successive multiplication by r and accumulation of
the integer digits obtained.
Data Representation

Binary to Octal and Hexadecimal Conversion
BCD:
 BCD is used to represent the decimal numbers system to binary
number system
 Each octal digit corresponds to three binary numbers i.e 8=2^3.
 Each hexadecimal digit corresponds to four binary numbers i.e
16=2^4.
Binary, octal, and hexadecimal conversion
1 2 7 5 4 3
1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1
A F 6 3
Octal
Binary
Hexa

COMPLEMENT OF NUMBERS
Complement of Numbers :
 Complement no’s are used in digital systems to simplify the
subtraction operations .There are two types of complements for the
base ‘r ‘number system.
1. r's complement ( Radix complement )
2. (r-1)'s complement ( Diminished Radix complement )
No.system r’s complement (r-1 )’s complement
r=10 10’s 9’s
r=2 2’s 1’s
r=8 8’s 7’s
r=16 16’s 15’s
r’s complement = rn-N where N = Given number
n = Total no. of digits
r = Base

Complement of Numbers
Example :
Find 10’s complement of 5690
Here r=10 , N=5690 , n=4
r’s complement =rn-N i.e 104- 5690 = 10000-5690 = 4310 ( or )
10’s complement = 9’s complement + 1
= 4309 +1 = 4310
(r-1)’s complement = rn-N -1
(or )
9’s complement can be calculated by subtracting each digit with 9.
Example :
Find 9’s complement of 5690
Here r=10 , N=5690 , n=4
9’s complement = 104-5690-1 = 10000-5690-1 = 4309 ( or )
9’s complement of 5690 is 9999 – 5690 = 4309

ADDRESSING MODES
Addressing Modes :
 Addressing modes are used to determine the effective address of
the operands resides either in memory or in registers.
 The following are the various addressing modes used in computer
Organisation.
1. Immediate mode :
In immediate addressing mode the operand is present in the
place of the address.
2. Implied Mode :
Implied addressing mode means operand is implicitly defined
in the definition of the instruction.
3. Register Mode :
The corresponding register contains the contents of the
accumulator.

ADDRESSING MODES
4. Register Indirect mode :
Register contains the Effective address in order to determine
the operand.
5. Auto Increment mode :
This mode is similar to register indirect mode but it follows the
post increment approach . In this approach first the contents
will be accessed and then increment is done.
6. Auto Decrement mode :
This mode is similar to register indirect mode but it follows
the pre increment approach . In this approach first decrement
is done and then the contents will be accessed.
7. Direct Address Mode :
In this mode the instruction contains an address that address
is the effective address.

ADDRESSING MODES
. Indirect Address Mode :
In this mode the instruction contains an address that address is
not the effective address.
9. Relative Address Mode :
The contents of the PC is added to the address field to get the
effective address.
10. Index Register Mode :
The contents of the Index Register is added to the address field
to get the effective address.
11. Base Register Mode :
The contents of the Base Register is added to the address field

2). The R's Complement
 The r's complement of an n-digit number N in base r is defined
as r'-N for N is not 0.
 Add 1 to the low-order digit of its (R-1)'scomplement
Example
 10's complement of 8351 is 1648 + 1 = 1649
 2's complement of 1010 is 0101 + 1 = 0110
Complement of Numbers

Input-Output and Interrupt
• A Terminal with a keyboard and aPrinter.
Fig: Input-Output Configuration

• The terminal sends and receives serial information.
• The serial info. from the keyboard is shifted into INPR .
• The serial info. for the printer is stored in the OUTR.
• INPR and OUTR communicate with the terminal serially
and with the AC in parallel.
• The flags are needed to synchronize the timing difference
between I/O device and the computer.

Fig: Input-Output Instruction

Program Interrupt
Interrupt :
 An interrupt is an input signal to the processor indicating an
event need an immediate action.
 CPU receives an interrupt signal from the processor then CPU
stops execution of the current running program and control
transfers to the interrupt related program . After executing the
interrupt related program ,the control again transfers the original
program and executes that program.

 The interrupt is handled by the computer can be explained by means
of the flowchart of following Fig.
 An interrupt flip-flop R has two values either 1 or 0.
If R=0, then there is no interrupt and goes to an instruction cycle.
R=1, then there in an interrupt.
During the execution of the instruction cycle IEN is checked by the
control. If it is 0, it indicates that the programmer does not want to
use the interrupt, so control continues inturrup with the next
instruction cycle.
 If IEN is 1, control checks the flag bits. If both flags are 0, it indicates
that neither the input nor the output registers are ready for transfer
of information.
 In this case, control continues with the next instruction cycle. If either
flag is set to 1 while IEN = 1, flip-flop R is set to 1.
Program Interrupt

Program Interrupt
Fig: Flow chart for InterruptCycle

 An example of an interrupt cycle is as shown in the following Fig.
Suppose that an interrupt occurs and R is set to 1 while the control is
executing the instruction at address255.
 At this time, the return address 256 is in PC. The programmer has
previously placed an input-output service program in memory
starting from address 1120 and a BUN 1120 instruction at address1.
This is shown in Fig(a).
 When control reaches timing signal T0 and finds that R = 1, it
proceeds with the interrupt cycle. The content of PC (256) is stored in
memory location 0, PC is set to 1, and R is cleared to 0. At the
beginning of the next instruction cycle, the instruction that is read
from memory is in address 1 since this is the content of PC. The
branch instruction at address 1 causes the program to transfer to the
input-output service program at address 1120.
Program Interrupt

 This program checks the flags, determines which flag is set, and then
transfers the required input or output information. One this is done,
the instruction ION is executed to set IEN to 1 (to enable further
interrupts), and the program returns to the location where it was
interrupted. This is shown in Fig.(b).
Program Interrupt

Addressing Modes
Addressing Modes :
 Addressing modes are used to determine the effective address of the
operands resides either in memory or in registers.
 The following are the various addressing modes used in computer
Organisation.
1. Immediate mode :
In immediate addressing mode the operand is present in the place
of the address.
2. Implied Mode :
Implied addressing mode means operand is implicitly defined in
the definition of the instruction.
3. Register Mode :
The corresponding register contains the contents of the
accumulator.

Addressing Modes
4. Register Indirect mode :
Register contains the Effective address in order to determine
the operand.
5. Auto Increment mode :
This mode is similar to register indirect mode but it follows the
post increment approach . In this approach first the contents
will be accessed and then increment is done.
6. Auto Decrement mode :
This mode is similar to register indirect mode but it follows
the pre increment approach . In this approach first decrement
is done and then the contents will be accessed.
7. Direct Address Mode :
In this mode the instruction contains an address that address
is the effective address.

Addressing Modes
8. Indirect Address Mode :
In this mode the instruction contains an address that address is
not the effective address.
9. Relative Address Mode :
The contents of the PC is added to the address field to get the
effective address.
10. Index Register Mode :
The contents of the Index Register is added to the address field
11. Base Register Mode :
The contents of the Base Register is added to the address field

Data Transfer and Manipulation Instructions
Computer instructions can be classified into three categories.
1. Data TransferInstructions.
2. Data Manipulation Instructions.
3. Program Control Instructions.
1. Data Transfer Instructions :
 Data Transfer Instructions transfer the data from one location
to another location with out changing its content.
 Transfers the data from different locations i.e from
• Memory --------- Memory.
• Register --------- Register.
• Memory --------- Registers.
• Registers --------- Memory.
• Registers --------- I/O Devices.

Data Transfer Instructions
Table : Typical data TransferInstructions

Data Manipulation Instructions
Data Manipulation Instructions :
 Data Manipulation Instructions are mainly used to perform
operations on instructions.
 These Instructions are of three basic types.
1. Arithmetic Instructions
2. Logical and Bit Manipulation Instructions
3. Shift Instructions

1. Arithmetic Instructions :
 In Arithmetic Instructions , the first column represents the name
of the instruction and second column represents the mnemonic.
 The following are the various Arithmetic Instructions
Table : Arithmetic Instructions

2. Logical and Bit manipulation Instructions :
 The Logical Instructions are used to manipulate individual bits or
group of bits in a register.
 The following are the list of logical manipulation instructions.
Table : Logical and Bit Manipulation Instructions

3. Shift Instructions :
 Shift Instructions are used to shift the contents of the registereither
from left to right or from right to left.
 The following are the list of shift instructions
Table : Shift Instructions

Program Control
 When the program control instruction is executed it change the
address value in the program counter and cause the flow of control
to be altered.

Table: conditional branch instructions
Program Control

Computer Arithmetic
Addition / Subtraction of Signed Magnitude Data :
 In signed magnitude representation the first bit
represents sign bit and the remaining bits specifies the
magnitude.
 For example consider the binary no. 1 1 1 0 1
Here the first bit ‘1’ is the sign bit and remaining bits
represents the magnitude.
If the sign bit is ‘1’ , it is a negative no. where as the sign
bit is ‘0’,it is a positive no.
 The various possible combinations of
addition/ subtractions are as shown in the following
table.

Addition And Subtraction
Addition/Subtraction algorithm :
 In the following table ,the 1st four operations are addition operations
the next four operations are subtraction operations.
Addition operation :
 If the signs of A and B are same , add the two magnitudes and attach
the sign of A to the result.
 If the signs of A and B are different compare the magnitudes and
subtract the smaller number from the larger.
Subtraction operation :
 If the signs of A and B are different then add the two magnitudes
and attach the sign of A to the result.
 If the signs of A and B are same , compare the magnitudes and
subtract the smaller number from the larger.

Addition and Subtraction
TABLE: Addition and Subtraction of Signed MagnitudeNumbers

Addition AndSubtraction
Hardware Implementation:
 Let A and B be two registers that hold the magnitudes of the
numbers, and As and Bs be two flip-flops that hold the
corresponding signs.
 The result of the operation may be transferred to a third register: the
result is transferred into A and As .
 Thus A and As together form an accumulator register.

 Figure shows a block diagram of the hardware for implementing the
addition and subtraction operations.
 It consists of registers A and B and sign flip-flops A, and B,.
 Subtraction is done by adding A to the 2' s complement of B.
 The output carry is transferred to flip-flop E, where it can be
checked to determine the relative magnitudes of the twonumbers.
 The add-overflow flip-flop AVF holds the overflow bit when A and B
areadded.
 The addition of A plus B is done through the parallel adder.
 The S (sum) output of the adder is applied to the input of the A
register.
 The complementer provides an output of B or the complement of B
depending on the state of the mode controlM.

Figure: Hardware for signed magnitude addition and subtraction.

 When M=1, the 1's complement of B is applied to the adder, the input
carry is 1, and output S = A + B̀ + 1. This is equal to A plus the 2's
complement of B, which is equivalent to the subtractionA -B.
 The two signs A, and B are compared by an exclusive-OR gate.
 If the output of the gate Is 0, the signs are identical if it is 1, the signs
are different For an add operation, identical signs dictate that the
magnitudes be added.
 For a subtract operation, different signs dictate that the magnitudes
be added.
 The magnitudes are added with a micro operation EA <-A + B. where
EA is a register that combines E and A.
 The carry in E after the addition constitutes an overflow if it is equal
to 1.

 Addition and Subtraction with Signed-2'sComplement Data
 The leftmost bit of a binary number represents the sign bit: 0 for
positive and 1 for negative.
represented in 2' s
 If the sign bit is 1, the entire number is
complement form.
 The algorithm for adding and subtracting two binary numbers in
signed- 2' s complement representation is shown in the flowchart of
Fig.
 The sum is obtained by adding the contents of AC and BR (including
their sign bits).
 The overflow bit V is set to 1 if the exclusive-OR of the last two
carries is 1, and it is cleared to 0 otherwise.

Figure :Algorithm for adding and subtracting numbers in signed 2's complement representation.

Multiplication Algorithms
Multiplication Algorithm :
 Multiplication performs on two types of data
1. Signed Magnitude data
2. 2’s Complement data ( Booths Algorithm )
Hardware implementation of multiplication Algorithm :
 In multiplication algorithm three registers are used namely B , Q.
and A.
 B register is used to represent the multiplicand.
 Q register is used to represent the multiplier and
 A register is a temporary register initially it contains zero’s.
 Bs ,Qs and As are the flip-flops that hold the corresponding sign
bits.

 Complimenter is used to transfer the contents of B register to
parallel adder to register B.
 parallel adder is used to add the contents of register A and register B
 The sequence counter SC is initially set to a number equal to the
number of bits in the multiplier.
 Logical Shift Right operation is performed on E ,A, and Q .
 When the content of the counter reaches zero, the product is
formed and the process stops.
 The LSB of A is shifted into the MSB position of Q, the bit from E is
shifted into the most significant position of A, and 0 is shifted into E.

Figure : Hardware implementation for multiply operation.

Figure : Flowchart for multiply operation.

 Initially, the multiplicand is in B and the multiplier in Q. Their
corresponding signs are in Bs, and Qs, respectively.
 The signs are compared, and both A and Q are set to correspond to
the sign of the product since a double-length product will be stored
in registers A and Q.
 Registers A and E are cleared and the sequence counter SC is set to a
number equal to the number of bits of the multiplier.
 After the initialization, the low-order bit of the multiplier inQ, is
tested.
 If it is a 1, the multiplicand in B is added to the present partial
product in A . If it is a 0 , nothing is done.
 Multiplication algorithm is explained with an example.
For example consider
Multiplicand =B = 23 = 10111
Multiplier = Q = 19 = 10011

TABLE : Numerical Example for Binary Multiplier

Booth’s Multiplication Algorithm
Hardware implementation of Booth’s multiplication
Algorithm :
 In multiplication algorithm three registers are used
namely BR , QR ,and AC.
 BR register is used to represent the multiplicand.
 QR register is used to represent the multiplier and
 AC register is a temporary register initially it contains zero’s.
 Parallel adder is used to perform the subtraction operation.
 Qn is the LSB of the multiplier.
 Qn+1 is the extra flip-flop of initial values zero’s .

 Sequence Counter ( SC ) contains no. Which is equal to the no. of
bits of the Multiplier .
 Each time check the values of Qn and Qn+1.
Figure: Hardware for Booth algorithm.
Booth’s Multiplication Algorithms

Figure : Booth algorithm for multiplication o f signed 2's complement numbers.

 Booth’s Multiplication Algorithm is explained with an example
Let Multiplicand = -9
Multiplier = -13 then
9 = 01001 13 = 01101
-9 = 10110 +1 = 10111 -13 = 10010 +1 = 10011
-9 = 10111 and -13 = 10011
 If the two bits are equal i.e . 00 and 11 ,perform the ashr operation
QR with AC .
 If the two bits are equal to 01 , add BR to AC.
 If the two bits are equal to 10 , subtract the BR from AC.

TABLE: Example of Multiplication with Booth Algorithm

Figure : 2-bit by 2-bit arraymultiplier.
Array Multiplier

 The multiplicand bits are b1 and b0, the multiplier bits are a1 and
a0, and the product is c3 c2 c1 c0.
 The first partial product is formed by multiplying a0 by b1 b0.
 The multiplication of two bits such as a0 and b0 produces a 1 if both
bits are 1; otherwise, it produces a 0.
 This is identical to an AND operation and can be implemented with
an AND gate. As shown in the diagram, the first partial product is
formed by means of two AND gates.
 The second partial product is formed by multiplying a1 by b1 b0 and
is shifted one position to the left.
Array Multiplier

Figure : 4-bit by 3-bit arraymultiplier.
Array Multiplier

Division Algorithms
Figure : Example of binary division.

Figure: Example of binary division with digitalhardware.
Division Algorithms

 The hardware divide algorithm is shown in the flowchart of below Fig
The dividend is in A and Q and the divisor in B .
 The sign of the result is transferred into Q, to be part of the quotient.
 A constant is set into the sequence counter SC to specify the number
of bits in the quotient.
 As in multiplication, we assume that operands are transferred to
registers from a memory unit that has words o f nbits.
 Since a n operand must b e stored with its sign, one bit o f the word
will be occupied by the sign and the magnitude will consist of n - 1
bits.
Division Algorithms

Figure : Flowchart for divide operation.
Division Algorithms

Floating-Point Arithmetic
Addition and Subtraction :
 The Floating point addition/sustraction algorithm can be divided
into four consecutive steps:
1. Check for zeros.
2. Align the mantissas.
3. Add or subtract the mantissas.
4.. Normalize the result.
 Normalize the result during addition or subtraction, the two
floating-point operands are in AC and BR .
 The sum or difference is formed in the AC .

Floating point no.is represented as
Mantissa X Baseexponent
Where mantissa is floating point no. and Base is 10 and exponent is
the given value.
Ex : 0.456 X 103
Here .456 is Mantissa
10 as base and exponent is 3
Step 1 : ( check for zero’s )
1st no. = AC = 0.000
2nd no. = BR = 0.012
Here two no. are not equal to zero and use alignment of mantissa.

Step 2 : ( Align mantissa )
First no. = AC = 0.654321 X 10
3
Second no. = BR = 0.234000 X 10
-1
Perform addition / sustraction operations the exponential values are
equal
Here the two exponential no. are not equal and make the no. Equal
by using shift left or right operations.
. Make the first no exponent to 10
-1
by using shift right operation
Ac = 0.210000 X 10
-1
BR = 0.234000 X 10
-1
( or )
Make the second no exponent to 103
by using shift left operation
Ac = 0.654321 X 10
3
BR = 0.000023 X 10
3

From the above two operations the Mantissa with least exponent
will perform the operation.
Step 3 : ( add/sub mantissa )
After making the mantissas equal then perform add/sub operation.
Step 4 : ( Normalise result )
For example
1. 0.0054 X 10 4
2. 0.5432 X 10 4
In example -1 the MSB bit of mantissa is zero i.e it is not in
normalise result where as in example -2 the MSB bit is in non-zero of
normalise result

 The register organization for floating-point operations is shown in
Fig. There are three registers, BR, AC , and QR.
 Each register is subdivided into two parts.
 The exponent part uses the corresponding lowercase lettersymbol.
 It is assumed that each floating-point number has a mantissa in
signed magnitude representation and a biasedexponent

 A parallel-adder adds the two mantissas and transfers the sum into
A and the carry into E .
Figure : Registers for floating-point arithmeticoperations.

Figure : Addition and subtraction of floating-pointnumbers.

 The magnitude comparator attached to exponents a and b provides
three outputs that indicate their relativemagnitude.
 If the two exponents are equal, we go to perform the arithmetic
operation.
 If the exponents are not equal, the mantissa having the smaller
exponent is shifted to the right and its exponentincremented.
 This process is repeated until the two exponents areequal.
 The addition and subtraction of the two mantissas is identical to
the fixed-point addition and subtraction algorithm presented in
Fig.
 The magnitude part is added or subtracted depending on the
operation and the signs of the two mantissas.

Multiplication :
The multiplication of two floating-point numbers requires that
multiply the mantissas and add the exponents.
The multiplication algorithm can be subdivided into four parts
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas.
4. Normalize the product
 Steps 2 and 3 can be done simultaneously if seperate address are
available for the mantissas and exponents.
 The flowchart for floating-point multiplication is shown in Fig.
 The two operands are checked to determine if they contain a zero.

Two floating point no. are 0.1234 X 10
3
0.5432 X 10
5
Step 1 : ( check for zero’s )
Step 2 : ( Add Exponents )
 In this multiplication the alignment of mantissa is not necessary.
 In order to add the exponents by using the adder.
Step 3 : ( multiply mantissa )
 Multiply the mantissas by using sign fixed point magnitude
multiplication algorithm.
 Represent the mantissas of two numbers in Binary notation and
perform the multiplication
Step 4 : ( Normalise result )
 After performing multiplication there should not be an overflow
but possible to get under flow,this can be removed by using shift
left operation.
 Here A1 is the MSB of the mantissa.

Figure : Multiplication of floating-point numbers.
Floating-Point Arithmetic Operations

Division
The division algorithm can be subdivided into five parts:
1. Check for zeros.
2. Initialize registers and evaluate the sign.
3. Align the dividend.
4. Subtract the exponents.
5. Divide the mantissas.
 The flowchart for floating-point division is shown in Fig.
 The two operands are checked for zero.
 If the divisor is zero, it indicates an attempt to divide by zero, which
is an illegal operation.
 The operation is terminated with an errormessage.

Figure : Division of floating-point numbers.

Decimal Arithmetic Operations
BCD ( Binary Coded Decimal ) :
 BCD is an abbrevation for Binary Coded Decimal.Each decimal
number can be represented as 4 bit Binary code.It is also called as
8421 BCD code.
Ex : 3 --> 0011
10 --> 0001 0000
BCD Adder :
 BCD adder is a combinatinal circuit that adds two BCD numbers and
produces the out put in BCD.
 BCD adder consisting of 4 bit binary adder for addtion.
 BCD numbers can be represented in the range from 0 tp 9. The no.
greater than 9 is not a valid BCD no.

BCD Adder :
 Consider the arithmetic addition of two decimal digits in BCD,
together with a possible carry from a previous stage.
 Since each input digit does not exceed 9, the output sum cannot be
greater than 9 + 9 + 1 = 19, the 1 in the sum being an input-carry.
 Suppose that we apply two BCD digits to a 4-bit binaryadder.
 The adder will form the sum in binary and produce a result that may
range from 0 to 19.
 These binary numbers are listed in Table 10-4 and are labeled by
symbols K, Z8, Z4, Z2, and Z1.
 When the binary sum is greater than 1001, we obtain a non valid BCD
representation.
 The addition of binary 6 (0110) to the binary sum converts it to the
correct BCD representation.

 The logic circuit that detects the necessary correction can be derived
from the table entries.
 It is obvious that a correction is needed when the binary sum has an
output carry K = 1.
 The other six combinations from 1010 to 1 1 1 1 that need a
correction have a 1 in positionZ8.
 To distinguish them from binary 1000 and 1001 which also have a 1 in
position Z8 we specify further that either Z4 or z, must have a1.
 The condition for a correction and an output-carry can be expressed by
the Boolean function C = K + Z8 Z4 + Z8 Z2. When C = 1, it is necessary
to add 0110 to the binary sum and provide an output-carry for the
next stage.
 When the output-carry is equal to 0, nothing is added to the binary
sum.
 When it is equal to 1, binary 0110 is added to the binary sum through
the bottom 4-bit binary adder.

Figure : Block diagram of BCD adder.

Figure : One stage of a decimal arithmeticunit.
Addition and Subtraction
 The algorithms for arithmetic operations with decimal data are
similar to the algorithms for the corresponding operations with
binary data.
 The algorithm for addition and subtraction of binary signed-
magnitude numbers applies also to decimal signed-magnitude
numbers provided that we interpret the micro operation symbols in
the proper manner.

 Decimal data can be added in three different ways, as shown in The
parallel method uses a decimal arithmetic unit composed of as many
BCD adders as there are digits in the number.
 The sum is formed in parallel and requires only one rnicrooperation.
 In the digit-serial bit-parallel method, the digits are applied to a
single BCD adder serially, while the bits of each coded digit are
transferred in parallel.
 The sum is formed by shifting the decimal numbers through the BCD
adder one at a time.
 For k decimal digits, this configuration requires k microoperations,
one for each decimal shift.
 In the all serial adder, the bits are shifted one at a time through a full-
adder.

Figure: Three ways of adding decimal numbers.

Multiplication
 We are assuming here four-digit numbers, with each digit
occupying four bits, for a total of 16 bits for each number.
 There arethree registers, A, B, and Q, each having a corresponding
sign flip- flop AS, BS, and QS,.
 Registers A and B have four more bits designated by A, and B, that
provide an extension of one more digit to the registers.
 The BCD arithmetic unit adds the five digits in parallel and places
the sum in the five-digit Aregister.
 The end-carry goes to flip-flop E.
 The purpose of digit A, is to accommodate an overflow while
adding the multiplicand to the partial product duringmultiplication.

Figure : Registers for decimal arithmetic multiplication and division.
 The decimal multiplication algorithm is shown in Fig.
 Initially, the entire A register and B, are cleared and the sequence
counter SC is set to a number k equal to the number of digits in the
multiplier.
 The low-order digit of the multiplier in Q, is checked.

Figure : Flowchart for decimal multiplication.
 QL is checked again and the process is repeated until it is equal
to 0.

Division
 The decimal division algorithm is shown in Fig. It is similar to the
algorithm with binary data except for the way the quotient bits are
formed.
 The dividend (or partial remainder) is shifted to the left, with its most
significant digit placed inA.
 The divisor is then subtracted by adding its 10' s complement value.
Since Be is initially cleared, its complement value is 9 as required. The
carry in E determines the relative magnitude of A and B. If E = 0, it
signifies.

Figure : Flowchart for decimaldivision.

MODULE –IV
INPUT-OUTPUT ORGANIZATION

Course outcomes
CO8 Understand the memory hierarchy and its computer
architecture for improving the performance of processors.
CO9 Outline the basics of pipelined, superscalar, and RISC/CISC
architectures for understanding the basic functioning of a
processor

Course
Outcomes
(COs)
POs /
PSOs
to)
CO8 PO 1
Understand the memory hierarchy levels of
system and its concepts effect on the
performance processors applying science for the
solution of complex engineering problem.
CO9 PO 1
Compute (Knowledge) of various functions of
RISC and CISC architecture operates by applying
mathematics, science for engineering problems.
PSO1
Apply the knowledge of various functions of
RISC and CISC architecture in embedded
systems

Contents
Input or output organization:
• Input or output Interface
• Asynchronous data transfer
• Modes of transfer
• Priority interrupt
• Direct memory access.

I/O Interface :
 Input-output interface provides a method for transferring
information between internal storage and external I/O devices.
 CPU and Memory are the internal storage devices and all peripheral
devices connected out side the system are called external I/O
devices.
 Generally CPU can not access I/O devices directly because several
differences that exist between CPU and I/O devices.
 The CPU and memory are electronic devices where as the
Peripherals +++0
 electromechanical and electromagnetic devices so the operation of
CPU is different from the operation of peripherals.
 To communicate CPU , memory and peripherals a special
communication lines are required.
Input-output Interface

Differences between CPU and Peripheral devices
I/O devices :
1. I/O devices are slow in speed
2. I/O devices stores the information in bytes.
3. I/O devices stores the information in serial manner.
CPU :
1. Speed of CPU is fast.
2. CPU and Memory stores the information in words.
3. CPU executed the data in parallel manner.

I/O Bus and Interface Modules :
 In fig. CPU can not access I/O devices directly and it communicates
with I/O interface.
 The Bus is used to transfer the data from one device to another device.
 With the help of I/O Bus connect the CPU with interface.
 The I/O bus consists of data lines, address lines, and control lines
1. Data lines : It contains data accessible by CPU to perform
read/write operation.
2. Address line: contains the address of the device which is
accessible by the CPU.
3. Control line : It specifies which operation is to perform whether it is
read/write operation.
 The interface mainly contains two registers namely buffer register and
status register.

There are four types of commands used in I/O interface
1.Status command :
CPU checks the status register whether the status id free or not.
2.Control command :
To perform read/write operation as specified .
3. Input command :
In order to store the data in interface.
4.Output command :
In order to get the data for the CPU.
 Each interface decodes the address and control received from the
I/O bus, interprets them for the peripheral, and provides signals
for the peripheral controller.
 The magnetic disk, printer, and terminal are employed in
practically any general-purpose computer.
 The magnetic tape is used in some computers for backup storage.

Figure: Connection of I/O bus to input devices.

Isolated I/O Vs Memory mapped I/O :
 Generally CPU can access memory and I/O.There are two
approaches are used namely
1. Isolated I/O 2. Memory mapped I/O
Isolated I/O :
 In isolated I/O two seperate address spaces are used one for
memory location and the other for I/o devices.
 Address and Data lines are common to memory and I/O devices
where as control lines are different.
 I/O devices mapped with I/o space
 Decoding is easy and works faster.
 Here I/O address space is isolated from memory address that’s why
this is called Isolated I/O.

Memory mapped I/O :
 In memory mapped I/O one address space is used by the CPU and it
is assigned to memory location and I/O devices.
 The I/O and Memory shares same memory with Data lines, Address
lines and Control lines.
 Here only one set of read/write lines are used.
 I/O devices mapped with memory space
 Decoding is complex and more delay occurs in work.

Figure: Example of I/O interfaceunit.

Asynchronous Data Transfer
Data Transfer :
Data can transmitted from source to destination machine in two
ways
1. Synchronous data transfer
2. Asynchronous data transfer
Synchronous data transfer :
 In Synchronous data transfer source and destination machines
shares the common clock pulses
 Common clock pulse is applied to CPU and I/o devices . CPU
access speed is very fast and I/O devices are very slow so the
Synchronous data trasfer is not possible.
Asynchromous data transfer :
 In Asynchronous data transfer the source and destination
machines have their own clock pulses .There are two approaches
used namely
 1. Strobe method 2. Hand shaking method

Strobe Control :
 The strobe control method of asynchronous data transfer employs a
single control line to time for each transfer.
 The strobe may be activated by either the source or the
destination unit.
 The strobe may be activated by source is called source-initiated
transfer and the strobe activated by destination is called destination -
initiated transfer.
source-initiated transfer :
 The source unit first places the data on the data bus.
 The data bus carries the binary information from source unit to the
destination unit.
 After a brief delay the data settle to a steady value, the source
activates the strobe pulse for a sufficient time period to allow the
destination unit to receive the data.

Figure: Source-initiated strobe for data transfer

Destination -initiated transfer :
 Figure shows a data transfer initiated by the destination unit. In this
case the destination unit activates the strobe pulse, informing the
source to provide the data.
 The source unit responds by placing the requested binary
information on the data bus.
 The data must be valid and remain in the bus long enough for the
destination unit to accept it.
 The falling edge of the strobe pulse can be used again to trigger a
destination register.

Figure: Destination-initiated strobe for data transfer.

Handshaking :
 The disadvantage of the strobe method is that the source unit that
initiates the transfer has no way of knowing whether the destination
unit has actually received the data item that was placed in the bus.
 Similarly, a destination unit that initiates the transfer has no way of
knowing whether the source unit has actually placed the data on
the bus,.
 The handshake method solves this problem by introducing a second
control signal that provides a reply to the unit that initiates the
transfer.

Figure: source initiated transfer usinghandshaking.

Modes of Data Transfer :
Data transfer to and from CPU and I/O devices may be performed in the
following modes.
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)
 In Programmed I/O and Interrupt modes CPU act as the intermediate
path but in Direct memory Access I/O devices directly access the
memory.
Programmed I/O :
 Programmed I/O is used to transfer data between I/O devices and
CPU . In order to resolve the differences between CPU and I/O devices
by using I/O interface
Modes of Transfer

Programmed I/O
In I/O interface two types of registers are used namely
1. Data register and 2. Status register
The status register maintain the flag bit ‘F’ has the values may be
either 1 or 0 .
 The information present in I/O Bus is placed in Data register. The
Data register contains certain information , the flag bit value is set
to 1 then interface enables the data accepted line . It specifies that
the corresponding connection between CPU and interface.
 Three Buses used here are Data bus , Address bus and Control
bus.
 The information present in Data register will be send to CPU with
the help of Data bus
 CPU can access I/O device by specifying its address specified in
address bus.
 I/O read and write are the control lined that performs the read and
write operation.

Programmed I/O
 Flow chart of the programmed I/O is as shown below

Programmed I/O
 Every time CPU checks the status register where it has the value
1 or 0 .
 we are not utilising the efficiency of the CPU in efficient manner
 So the programmed I/O is nor efficient method.

 Transfer of data under programmed I/O is between CPU and
peripheral.
data into
 In direct memory access (DMA), the interface transfers
and out of the memory unit through the memory bus.
 The CPU initiates the transfer by supplying the interface with the
starting address and the number of words needed to be transferred
and then proceeds to execute othertasks.
the DMA requests memory cycles
 When the transfer is made,
through the memorybus.
 When the request is granted by the memory controller, the DMA
transfers the data directly into memory. The CPU merely delays its
memory access operation to allow the direct memory I/Otransfer.
Modes of Transfer

Example Of Programmed I/O
 An example of data transfer from an I/O device through an interface
into the CPU is shown in Fig.
 The device transfers bytes of data one at a time as they are available.
When a byte of data is available, the device places it in the I/O bus
and enables its data valid line.
 The interface accepts the byte into its data register and enables the
data accepted line.
 The interface sets a it in the status register that we will refer to as an
F or “flag” bit.
 The device can now disable the data valid line, but it will not transfer
another byte until the data accepted line is disabled by the interface.
Modes of Transfer

Modes of Transfer
Interrupt initiated I/O :
 The wastage of time of CPU can be avoided by using the interrupt
facility.
 In the mean time CPU can be busy in performing other useful tasks.
 When the I/O device is ready for data transfer , it generates an
interrupt request to the CPU.
 CPU can stops the execution of the present instruction & execute
the interrupt related instruction.
 After completing the interrupt related instruction , the CPU goes
back to the original instruction and executes that instruction.

Modes of Transfer
Priority Interrupt :
 When requests two or more devices simultaneously , the
CPU has to decide which request should be services first and
which one should be delayed.
 The CPU takes decision with the help of interrupt priorities.
 It accepts the request having the highest priority.
 The device which is having higher priority will be execute first and
the device having the lower priority will be execute last .
 Priority interrupts can be implemented by using two approaches
1. Software based approach -- Polling.
2. Hardware based approach -- Daisy chain priority

Modes of Transfer
S/W approach – Polling :
 S/W approach is implemented with the help of a program. CPU first
checks if the higher priority device generated interrupt signal or not.
 If it generates interrupt signal then CPU executes corresponding
interrupt instruction.
 If it does not generated interrupt signal CPU checks next higher
priority interrupt like wise it checks one by one.
 The branch addresses can be done by two ways
1. Vector interrupt Address ( VAD )
2. Non-Vector interrupt Address ( NVAD )

Modes of Transfer
Vector interrupt Address (VAD ) :
 In vector interrupt the I/O device interface will transfer the
address where the interrupt service routine is located and CPU is
not go to particular location
Non-Vector interrupt Address ( NVAD ) :
 In non-vector interrupt by default the CPU will go to the specific
location and execute all the content related interrrupt signal will
get executed.

Hardware approach -- Daisy-chaining Priority :
 The daisy-chaining method of establishing priority consists of a serial
connection of all devices that request an interrupt.
 The device with the highest priority is placed in the first position,
followed by lower-priority devices up to the device with the lowest
priority, which is placed last in the chain.
 This signal is received by device 1 at its PI (priority in) input. The
acknowledge signal passes on to the next device through the PO
(priority out) output only if device 1 is not requesting aninterrupt.
 If device 1 has a pending interrupt, it blocks the acknowledge signal
from the next device by placing a 0 in the PO output.
 It then proceeds to insert its own interrupt vector address (VAD) into
the data bus for the CPU to use during the interrupt cycle.
Priority Interrupt

Priority Interrupt
.
Figure: Daisy chain priority interrupt.

 A device with a 0 in its PI input generates a 0 in its PO output to
inform the next-lower priority device that the acknowledge signal
has been blocked.
 A device that is requesting an interrupt and has a 1 in its PI input
will intercept the acknowledge signal by placing a 0 in its PO
output. If the device does not have pending interrupts, it
transmits the acknowledge signal to the next device
Priority Interrupt

Direct Memory Access(DMA)
 The transfer of data between a fast storage device such as magnetic
disk and memory is often limited by the speed of the CPU.
Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of
transfer.
 This transfer technique is called direct memory access(DMA).
 During DMA transfer, the CPU is idle and has no control of the
memory buses.
Direct Memory Access (DMA)
Figure : CPU bus signals for DMAtransfer.

Direct Memory Access (DMA) :
 The I/O devices wants to access the memory directly with out CPU
involvement is known as Direct memory Access (DMA ).
 This method used to transfer the data at faster rate.
Operations performed by DMA :
 Initially I/O device wants to send the data to memory.
 First I/O device has to send DMA request ( DRQ ) to DMA
controller .
 Then DMA controller sends hold request ( HLQ ) to CPU.
 DMA controller waits until CPU sends hold acknowledgement
( HLDA ) to CPU over the system bus.

 CPU leaves the control over the system bus .
 CPU becomes slave and DMA controller becomes master.
 Now CPU is in Hold state and DMA controller has to manage the
operations over the system bus between CPU , Memory and I/O
devices.

Data transfer in DMA Controller :
 In order to release the CPU involvement , we uses the Direct
Memory Access.
 In DMA transfer DMA controller is responsible for transfer the
data between I/O devices and Memory.
 when ever I/O device is ready to transfer the data , it will send
DMA req to DMA Controller.
 DMA Controller receives DMA req from I/O device.
 Then DMA controller sends the Bus req ( BR ) signal to CPU .
 CPU receives the BR signal from DMA controller
 Once CPU receives the BR signal then it puts the data , address
and control Bus lines in high impedance state i.e in open circuit
and does not perform any operation.

 Then CPU sending Bus Grant ( BG ) signal to the DMA controller
 Once DMA controller receives the BG signal then it can access data,
address and control lines and it provides the DMA ack to the I/O
device.
 Now DMA is ready for transfer the data from I/O devices to
Memory.
 DMA controller maintains three registers namely
1. Address register : specifies starting address of memory.
2. Word count reg : specifies the no. of words count
3.control register : specifies whether it performs read/write
operation.

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