This document discusses memory organization and caching techniques. It begins by describing different types of primary memory (RAM, ROM) and secondary memory (magnetic disks, tapes, optical discs, flash). It then discusses RAM types (DRAM, SRAM), ROM types (PROM, EPROM, EEPROM), and caching principles including cache design considerations like addressing, size, mapping functions, and write policies. Memory management techniques like paging, segmentation, and virtual memory are also summarized.

1. ELECTRONICS & TELECOMMUNICATION
ENGINEERING DEPARTMENT
Unit No: 04
Memory Organization
Presented by
Mr.M.A.Chimanna
Date: 09.10.2019

2. COMPUTER ARCHITECTURE
Primary
• RAM
• ROM
• CACHE
Memory
Organization
Secondary
• Magnetic Disc
• Magnetic Tape
• Optical Disc
• Flash Memory

3. RAM [DRAM AND SRAM]
 DYNAMIC RAM
 A dynamic RAM (DRAM) is made with cells that store data as
charge on capacitors. The presence or absence of charge in a
capacitor is interpreted as a binary 1 or 0.
 DRAM structure for an individual cell that stores 1 bit.

4.  For the write operation, a voltage signal is applied to the bit
line; a high voltage represents 1, and a low voltage
represents 0. A signal is then applied to the address
line, allowing a charge to be transferred to the capacitor.
 For the read operation, when the address line is selected,
the transistor turns on and the charge stored on the
capacitor is fed out onto a bit line and to a sense amplifier.
The sense amplifier compares the capacitor voltage to a
reference value and determines if the cell contains a logic 1
or a logic 0.

5. STATIC RAM
 Four transistors (T1,T2,T3,T4) are cross connected in an
arrangement that produces a stable logic state.
 In logic state 1, point C1 is high and point C2 is low; in this
state,T1 and T4 are off and T2 and T3 are on.
 In logic state 0, point C1 is low and point C2 is high; in this
state,T1 and T4 are on and T2 and T3 are off. Both states are stable
as long as the direct current (dc) voltage is applied.
 Write –
Select Row
Cell Pulls One line low and one is high
 Read –
Drive Bit Lines
Select Row

6. FOR A WRITE OPERATION, THE DESIRED BIT VALUE IS
APPLIED TO LINE B, WHILE ITS COMPLEMENT IS APPLIED
TO LINE . THIS FORCES THE FOUR TRANSISTORS (T1, T2,
T3, T4) INTO THE PROPER STATE. FOR A READ OPERATION,
THE BIT VALUE IS READ FROM LINE B

7. TYPES OF ROM
 Programmable ROM (PROM)
 Erasable programmable read-only memory (EPROM)
 Electrically erasable programmable read-only memory
(EEPROM).

8. TOPIC: MEMORY MANAGEMENT
Reading: Stallings, Sections 8.3 and 8.4

9. MEMORY MANAGEMENT
 Uni-program – memory split into two parts
 One for Operating System (monitor)
 One for currently executing program
 Multi-program
 Non-O/S part is sub-divided and shared among
active processes
 Remember segment registers in the 8086
architecture
Data Segment, Code Segment, Extra
Segment
 Hardware designed to meet needs of O/S
 Base Address = segment address

10. SWAPPING
 Problem: I/O (Printing, Network, Keyboard, etc.) is so slow
compared with CPU that even in multi-programming system,
CPU can be idle most of the time
 Solutions:
 Increase main memory
Expensive
Programmers will eventually use all of this
memory for a single process
 Swapping

11.  Long term queue of processes stored on disk
 Processes “swapped” in as space becomes available
 As a process completes it is moved out of main memory
 If none of the processes in memory are ready (i.e. all I/O blocked)
 Swap out a blocked process to intermediate queue
 Swap in a ready process or a new process
 But swapping is an I/O process!
 It could make the situation worse
 Disk I/O is typically fastest of all, so it still is an improvement
What is Swapping?

12. PARTITIONING
 Splitting memory into sections to allocate to processes
(including Operating System)
 Two types
 Fixed-sized partitions
 Variable-sized partitions

13. FIXED-SIZED PARTITIONS (CONTINUED)
 Equal size or Unequal size partitions
 Process is fitted into smallest hole that will take it (best
fit)
 Some wasted memory due to each block having a hole of
unused memory at the end of its partition
 Leads to variable sized partitions

14. FIXED-SIZED
PARTITIONS

15. VARIABLE-SIZED PARTITIONS
 Allocate exactly the required memory to a process
 This leads to a hole at the end of memory, too small to use – Only
one small hole - less waste
 When all processes are blocked, swap out a process and bring in
another
 New process may be smaller than swapped out process
 Reloaded process not likely to return to same place in memory it
started in
 Another hole
 Eventually have lots of holes (fragmentation)

16. VARIABLE-SIZED PARTITIONS

17. PAGING (CONTINUED)
 Both unequal fixed-size and variable-size partitions
are inefficient in the use of memory.
 Suppose, however, that memory is partitioned into
equal fixed-size chunks that are relatively small, and
that each process is also divided into small fixed-size
chunks of some size. Then the chunks of a program,
known as pages, could be assigned to available
chunks of memory, known as frames, or page frames

18. PAGING EXAMPLE – BEFORE
Process A
Page 0
Page 1
Page 2
Page 3
13
14
15
16
17
18
19
20
21
Free frame list
13
14
15
18
20
In
use
In
use
In
use
In
use

19. PAGING EXAMPLE – AFTER
Process A
Page 0
Page 1
Page 2
Page 3
Free frame list
20
Process A
page table
13
14
15
18
13
14
15
16
17
18
19
20
21
In
use
In
use
In
use
In
use
Page 0
of A
Page 1
of A
Page 2
of A
Page 3
of A

20. VIRTUAL MEMORY
 That refinement is demand paging, which simply means that
 each page of a process is brought in only when it is needed,
that is, on demand
 Because a process executes only in main memory, that memory
is referred to as real memory. But a programmer or user
perceives a much larger memory—that which is allocated on
the disk. This latter is therefore referred to as virtual memory.
 Virtual memory allows for very effective multiprogramming
and relieves the user of the unnecessarily tight constraints of
main memory

21. SEGMENTATION
 There is another way in which addressable memory can be
subdivided, known as segmentation.
 Whereas paging is invisible to the programmer and serves the
purpose of providing the programmer with a larger address space,
segmentation is usually visible to the programmer and is
provided as a convenience for organizing programs and data and
as a means for associating privilege and protection attributes with
instructions and data.
 Segmentation allows the programmer to view memory as
consisting of multiple address spaces or segments. Segments are
of variable, indeed dynamic, size. Typically, the programmer or
the OS will assign programs and data to different segments.
There may be a number of program segments for various types of
programs as well as a number of data segments.

22. ADVANTAGES OF SEGMENTATION
 Simplifies handling of growing data structures – O/S will
expand or contract the segment as needed
 Allows programs to be altered and recompiled independently,
without re-linking and re-loading
 Lends itself to sharing among processes
 Lends itself to protection since O/S can specify certain
privileges on a segment-by-segment basis
 Some systems combine segmentation with paging

23. CACHE MEMORY PRINCIPLES
 Cache memory is intended to give memory speed
approaching that of the fastest memories available, and at
the same time provide a large memory size at the price of
less expensive types of semiconductor memories.


24.  Single Cache Memory
 The concept is illustrated in Figure 4.3a. There is a relatively
large and slow main memory together with a smaller, faster
cache memory. The cache contains a copy of portions of main
memory. When the processor attempts to read a word of
memory, a check is made to determine if the word is in the
cache If so, the word is delivered to the processor. If not, a
block of main memory, consisting of some fixed number of
words, is read into the cache and then the word is delivered to
the processor

25. THE L2 CACHE IS SLOWER AND TYPICALLY LARGER THAN THE L1
CACHE, AND THE L3 CACHE IS SLOWER AND TYPICALLY LARGER
THAN THE L2 CACHE.

26. STRUCTURE OF MAIN MEMORY & CACHE
MEMORY
 Main memory consists of up to 2n addressable words, with each
word having a unique n-bit address.
 For mapping purposes, this memory is considered to consist of a
number of fixed length blocks of K words each. That is, there are
M 2n/K blocks in main memory.
 The cache consists of m blocks, called lines. Each line contains K
words, plus a tag of a few bits. Each line also includes control bits
(not shown), such as a bit to indicate whether the line has been
modified since being loaded into the cache.
 The length of a line, not including tag and control bits, is the line
size

28. CACHE DESIGN
 Addressing
 Size
 Mapping Function
 Replacement Algorithm
 Write Policy
 Block Size
 Number of Caches

29. ADDRESSING
 When virtual memory is used, the address fields of machine
instructions contain virtual addresses. For reads to and writes
from main memory, a hardware memory management unit
(MMU) translates each virtual address into a physical address in
main memory.
 When virtual addresses are used, the system designer may
choose to place the cache between the processor and the MMU
or between the MMU and main memory A logical cache, also
known as a virtual cache, stores data
 using virtual addresses.
 The processor accesses the cache directly, without going
 through the MMU. A physical cache stores data using main
memory physical addresses.

31. Processor Type
Year of
Introduction
L1 cache L2 cache L3 cache
IBM 360/85 Mainframe 1968 16 to 32 KB — —
PDP-11/70 Minicomputer 1975 1 KB — —
VAX 11/780 Minicomputer 1978 16 KB — —
IBM 3033 Mainframe 1978 64 KB — —
IBM 3090 Mainframe 1985 128 to 256 KB — —
Intel 80486 PC 1989 8 KB — —
Pentium PC 1993 8 KB/8 KB 256 to 512 KB —
PowerPC 601 PC 1993 32 KB — —
PowerPC 620 PC 1996 32 KB/32 KB — —
PowerPC G4 PC/server 1999 32 KB/32 KB 256 KB to 1 MB 2 MB
IBM S/390 G4 Mainframe 1997 32 KB 256 KB 2 MB
IBM S/390 G6 Mainframe 1999 256 KB 8 MB —
Pentium 4 PC/server 2000 8 KB/8 KB 256 KB —
IBM SP
High-end server/
supercomputer
2000 64 KB/32 KB 8 MB —
CRAY MTAb Supercomputer 2000 8 KB 2 MB —
Itanium PC/server 2001 16 KB/16 KB 96 KB 4 MB
SGI Origin 2001 High-end server 2001 32 KB/32 KB 4 MB —
Itanium 2 PC/server 2002 32 KB 256 KB 6 MB
IBM POWER5 High-end server 2003 64 KB 1.9 MB 36 MB
CRAY XD-1 Supercomputer 2004 64 KB/64 KB 1MB —

32. DIRECT MAPPING
 The simplest technique, known as direct mapping, maps each
block of main memory into only one possible cache line. The
mapping is expressed as i = j modulo m
where
i cache line number
j main memory block number
m number of lines in the cache
 Figure shows the mapping for the first blocks of main memory.
Each block of main memory maps into one unique line of the
cache.The next blocks of main memory map into the cache in
the same fashion; that is, block Bm of main memory maps into
line L0 of cache, block Bm1 maps into line L1, and
so on.

34. WRITE POLICY
 When a block that is resident in the cache is to be
replaced, there are two cases to consider.
 If the old block in the cache has not been altered, then it
may be overwritten with a new block without first
writing out the old block.
 If at least one write operation has been performed on a
word in that line of the cache, then main memory must
be updated by writing the line of cache out to the block
of memory before
bringing in the new block.