RIKEN's presentation from recent International Supercomputer Conference - #ISC16. A closer look at their next-generation "Post-K" supercomputer based on #ARM and Fujitsu #HPC SoC
In this deck from the HPC User Forum in Austin, Yutaka Ishikawa from Riken AICS presents: Japan's post K Computer.
Watch the video presentation: http://wp.me/p3RLHQ-fJ6
Learn more: http://hpcuserforum.com
Introduction of Fujitsu's HPC Processor for the Post-K Computerinside-BigData.com
Toshio Yoshida from Fujitsu presented this deck at the 2016 Hot Chips conference. Slated for delivery sometime around 2022, the Post-K supercomputer. Originally targeted for completion in 2020, the ARM-based Post K supercomputer has a performance target of being 100 times faster than the original K computer within a power envelope that will only be 3-4 times that of its predecessor.
Charles Zhang from Phytium previewed the 64 Core Phytium chip at the 2015 Hot Chips conference. This week, the ARM chip was unveiled with a prototype server at Hot Chips 2016.
SGI: Meeting Manufacturing's Need for Production Supercomputinginside-BigData.com
In this slidecast, Tony DeVarco from SGI describes how the company delivers Production Supercomputing for SMEs.
For the manufacturing sector, SGI serves the needs of customers that require extreme performance with efficiency, and scalability with reliability. Leading organizations around the world combine SGI high performance computing servers, storage and software to solve some of the world’s most difficult problems.
Percy Tzelnic from Dell Technologies presented this deck at the HPC User Forum in Austin.
Watch the video presentation: http://insidehpc.com/2016/09/emc-in-hpc-the-journey-so-far-and-the-road-ahead/
Learn more: http://emc.com/
In this deck, Ronald P. Luijten from IBM Research in Zurich presents: DOME 64-bit μDataCenter.
I like to call it a datacenter in a shoebox. With the combination of power and energy efficiency, we believe the microserver will be of interest beyond the DOME project, particularly for cloud data centers and Big Data analytics applications."
The microserver’s team has designed and demonstrated a prototype 64-bit microserver using a PowerPC based chip from Freescale Semiconductor running Linux Fedora and IBM DB2. At 133 × 55 mm2 the microserver contains all of the essential functions of today’s servers, which are 4 to 10 times larger in size. Not only is the microserver compact, it is also very energy-efficient.
Watch the video: http://wp.me/p3RLHQ-gJM
Learn more: https://www.zurich.ibm.com/microserver/
Sign up for our insideHPC Newsletter: http://insideHPC/newsletter
Yutaka Ishikawa - Post-K and Arm HPC Ecosystem - Linaro Arm HPC Workshop Sant...Linaro
Yutaka Ishikawa - Post-K and Arm HPC Ecosystem - Linaro Arm HPC Workshop Santa Clara 2018
Bio: "Yutaka Ishikawa is the project leader of developing the post K
supercomputer. From 1987 to 2001, he was a member of AIST (former
Electrotechnical Laboratory), METI. From 1993 to 2001, he was the
chief of Parallel and Distributed System Software Laboratory at Real
World Computing Partnership. He led development of cluster system
software called SCore, which was used in several large PC cluster
systems around 2004. From 2002 to 2014, he was a professor at the
University Tokyo. He led a project to design a commodity-based
supercomputer called T2K open supercomputer. As a result, three
universities, Tsukuba, Tokyo, and Kyoto, obtained each supercomputer
based on the specification in 2008. He was also involved with the
design of the Oakleaf-PACS, the successor of T2K supercomputer in both
Tsukuba and Tokyo, whose peak performance is 25PF."
Session Title: Post-K and Arm HPC Ecosystem
Session Description:
"Post-K, a flagship supercomputer in Japan, is being developed by Riken
and Fujitsu. It will be the first supercomputer with Armv8-A+SVE.
This talk will give an overview of Post-K and how RIKEN and Fujitsu
are currently working on software stack for an Arm architecture."
In this deck, Jean-Pierre Panziera from Atos presents: BXI - Bull eXascale Interconnect.
"Exascale entails an explosion of performance, of the number of nodes/cores, of data volume and data movement. At such a scale, optimizing the network that is the backbone of the system becomes a major contributor to global performance. The interconnect is going to be a key enabling technology for exascale systems. This is why one of the cornerstones of Bull’s exascale program is the development of our own new-generation interconnect. The Bull eXascale Interconnect or BXI introduces a paradigm shift in terms of performance, scalability, efficiency, reliability and quality of service for extreme workloads."
Watch the video: http://wp.me/p3RLHQ-gJa
Learn more: https://bull.com/bull-exascale-interconnect/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this deck from the HPC User Forum in Austin, Yutaka Ishikawa from Riken AICS presents: Japan's post K Computer.
Watch the video presentation: http://wp.me/p3RLHQ-fJ6
Learn more: http://hpcuserforum.com
Introduction of Fujitsu's HPC Processor for the Post-K Computerinside-BigData.com
Toshio Yoshida from Fujitsu presented this deck at the 2016 Hot Chips conference. Slated for delivery sometime around 2022, the Post-K supercomputer. Originally targeted for completion in 2020, the ARM-based Post K supercomputer has a performance target of being 100 times faster than the original K computer within a power envelope that will only be 3-4 times that of its predecessor.
Charles Zhang from Phytium previewed the 64 Core Phytium chip at the 2015 Hot Chips conference. This week, the ARM chip was unveiled with a prototype server at Hot Chips 2016.
SGI: Meeting Manufacturing's Need for Production Supercomputinginside-BigData.com
In this slidecast, Tony DeVarco from SGI describes how the company delivers Production Supercomputing for SMEs.
For the manufacturing sector, SGI serves the needs of customers that require extreme performance with efficiency, and scalability with reliability. Leading organizations around the world combine SGI high performance computing servers, storage and software to solve some of the world’s most difficult problems.
Percy Tzelnic from Dell Technologies presented this deck at the HPC User Forum in Austin.
Watch the video presentation: http://insidehpc.com/2016/09/emc-in-hpc-the-journey-so-far-and-the-road-ahead/
Learn more: http://emc.com/
In this deck, Ronald P. Luijten from IBM Research in Zurich presents: DOME 64-bit μDataCenter.
I like to call it a datacenter in a shoebox. With the combination of power and energy efficiency, we believe the microserver will be of interest beyond the DOME project, particularly for cloud data centers and Big Data analytics applications."
The microserver’s team has designed and demonstrated a prototype 64-bit microserver using a PowerPC based chip from Freescale Semiconductor running Linux Fedora and IBM DB2. At 133 × 55 mm2 the microserver contains all of the essential functions of today’s servers, which are 4 to 10 times larger in size. Not only is the microserver compact, it is also very energy-efficient.
Watch the video: http://wp.me/p3RLHQ-gJM
Learn more: https://www.zurich.ibm.com/microserver/
Sign up for our insideHPC Newsletter: http://insideHPC/newsletter
Yutaka Ishikawa - Post-K and Arm HPC Ecosystem - Linaro Arm HPC Workshop Sant...Linaro
Yutaka Ishikawa - Post-K and Arm HPC Ecosystem - Linaro Arm HPC Workshop Santa Clara 2018
Bio: "Yutaka Ishikawa is the project leader of developing the post K
supercomputer. From 1987 to 2001, he was a member of AIST (former
Electrotechnical Laboratory), METI. From 1993 to 2001, he was the
chief of Parallel and Distributed System Software Laboratory at Real
World Computing Partnership. He led development of cluster system
software called SCore, which was used in several large PC cluster
systems around 2004. From 2002 to 2014, he was a professor at the
University Tokyo. He led a project to design a commodity-based
supercomputer called T2K open supercomputer. As a result, three
universities, Tsukuba, Tokyo, and Kyoto, obtained each supercomputer
based on the specification in 2008. He was also involved with the
design of the Oakleaf-PACS, the successor of T2K supercomputer in both
Tsukuba and Tokyo, whose peak performance is 25PF."
Session Title: Post-K and Arm HPC Ecosystem
Session Description:
"Post-K, a flagship supercomputer in Japan, is being developed by Riken
and Fujitsu. It will be the first supercomputer with Armv8-A+SVE.
This talk will give an overview of Post-K and how RIKEN and Fujitsu
are currently working on software stack for an Arm architecture."
In this deck, Jean-Pierre Panziera from Atos presents: BXI - Bull eXascale Interconnect.
"Exascale entails an explosion of performance, of the number of nodes/cores, of data volume and data movement. At such a scale, optimizing the network that is the backbone of the system becomes a major contributor to global performance. The interconnect is going to be a key enabling technology for exascale systems. This is why one of the cornerstones of Bull’s exascale program is the development of our own new-generation interconnect. The Bull eXascale Interconnect or BXI introduces a paradigm shift in terms of performance, scalability, efficiency, reliability and quality of service for extreme workloads."
Watch the video: http://wp.me/p3RLHQ-gJa
Learn more: https://bull.com/bull-exascale-interconnect/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Macromolecular crystallography is an experimental technique allowing to explore 3D atomic structure of proteins, used by academics for research in biology and by pharmaceutical companies in rational drug design. While up to now development of the technique was limited by scientific instruments performance, recently computing performance becomes a key limitation. In my presentation I will present a computing challenge to handle 18 GB/s data stream coming from the new X-ray detector. I will show PSI experiences in applying conventional hardware for the task and why this attempt failed. I will then present how IC 922 server with OpenCAPI enabled FPGA boards allowed to build a sustainable and scalable solution for high speed data acquisition. Finally, I will give a perspective, how the advancement in hardware development will enable better science by users of the Swiss Light Source.
Huawei’s requirements for the ARM based HPC solution readiness - Joshua MoraLinaro
Talk Title: Huawei’s requirements for the ARM based HPC solution readiness
Talk Abstract:
A high level review of a wide range of requirements to architect an ARM based competitive HPC solution is provided. The review combines both Industry and Huawei’s unique views with the intend to communicate openly not only the alignment and support in ongoing efforts carried over by other ARM key players but to brief on the areas of differentiation that Huawei is investing towards the research, development and deployment of homegrown ARM based HPC solution(s).
Speaker: Joshua Mora
Speaker Bio:
20 years of experience in research and development of both software and hardware for high performance computing. Currently leading the architecture definition and development of ARM based HPC solutions, both hardware and software, all the way to the applications (ie. turnkey HPC solutions for different compute intensive markets where ARM will succeed !!).
This presentation covers various partners and collaborators who are currently working with OpenPOWER foundation ,Use cases of OpenPOWER systems in multiple Industries , OpenPOWER Workgroups and OpenCAPI features .
"Algorithmic processing performed in High Performance Computing environments impacts the lives of billions of people, and planning for exascale computing presents significant power challenges to the industry. ARM delivers the enabling technology behind HPC. The 64-bit design of the ARMv8-A architecture combined with Advanced SIMD vectorization are ideal to enable large scientific computing calculations to be executed efficiently on ARM HPC machines. In addition ARM and its partners are working to ensure that all the software tools and libraries, needed by both users and systems administrators, are provided in readily available, optimized packages."
Learn more: https://developer.arm.com/hpc
and
http://hpcuserforum.com
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Implementing AI: High Performance Architectures: Large scale HPC hardware in ...KTN
The Implementing AI: High Performance Architectures webinar, hosted by KTN and eFutures, was the fourth event in the Implementing AI webinar series.
The focus of the webinar was the impact of processing AI data on data centres - particularly from the technology perspective. Prof. Simon McIntosh-Smith, Professor in High Performance Computing, University of Bristol, covered Large scale HPC hardware in the age of AI.
In this deck from the HPC Advisory Council Spain Conference, Dan Olds from OrionX discusses the High Performance Interconnect (HPI) market landscape, plus provides ratings and rankings of HPI choices today.
"The HPI market is the very high-end of the networking equipment market where high bandwidth and low latency are non-negotiable. It started out as a specialist proprietary segment but has blossomed into an indispensable, large, and growing area. Products in this category are used to build extreme-scale computing systems. They are typically not used for traditional telco, enterprise, or service provider networking needs. In this talk, we’ll take a look at the technologies and performance of their high-end technology and the coming battle between onloading vs. offloading interconnect architectures."
Watch the video presentation: http://wp.me/p3RLHQ-fON
Learn more: http://orionx.net/wp-content/uploads/2016/06/HPI-Environment-OrionX-Constellation-DataCenter-20160626.pdf
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this video from the HPC User Forum in Santa Fe, Yoonho Park from IBM presents: IBM Datacentric Servers & OpenPOWER.
"Big data analytics, machine learning and deep learning are among the most rapidly growing workloads in the data center. These workloads have the compute performance requirements of traditional technical computing or high performance computing, coupled with a much larger volume and velocity of data."
Watch the video: http://wp.me/p3RLHQ-gJv
Learn more: https://openpowerfoundation.org/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this video from the Rice Oil & Gas Conference, Brent Gorda from ARM presents: ARM in HPC.
"With the recent Astra system at Sandia Lab (#203 on the Top500) and HPE Catalyst project in the UK, Arm-based architectures are arriving in HPC environments. Several partners have announced or will soon announce new silicon and projects, each of which offers something different and compelling for our community. Brent will describe the driving factors and how these solutions are changing the landscape for HPC."
Watch the video: https://wp.me/p3RLHQ-jXS
Learn more: https://developer.arm.com/hpc
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this deck from the Linaro Connect conference, Brent Gorda presents an update on ARM for HPC.
"Arm-based systems are showing up in the HPC community and new silicon is coming. The architecture has also been selected for several of the exascale projects worldwide. Brent will talk about the aspects of Arm that are attractive to the HPC community, updates on projects and what we as a community can do to help accelerate adoption in this space."
Watch the video: https://insidehpc.com/2019/09/an-update-on-arm-in-hpc/
Learn more: https://developer.arm.com/tools-and-software/server-and-hpc
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Deep Learning Neural Network Acceleration at the Edge - Andrea GalloLinaro
Short
The growing amount of data captured by sensors and the real time constraints imply that not only big data analytics but also Machine Learning (ML) inference shall be executed at the edge. The multiple options for neural network acceleration in Arm-based platforms provide an unprecedented opportunity for new intelligent devices. It also raises the risk of fragmentation and duplication of efforts when multiple frameworks shall support multiple accelerators.
Andrea Gallo, Linaro VP of Segment Groups, will summarise the existing NN frameworks, accelerator solutions, and will describe the efforts underway in the Arm ecosystem.
Abstract
The dramatically growing amount of data captured by sensors and the ever more stringent requirements for latency and real time constraints are paving the way for edge computing, and this implies that not only big data analytics but also Machine Learning (ML) inference shall be executed at the edge. The multiple options for neural network acceleration in recent Arm-based platforms provides an unprecedented opportunity for new intelligent devices with ML inference. It also raises the risk of fragmentation and duplication of efforts when multiple frameworks shall support multiple accelerators.
Andrea Gallo, Linaro VP of Segment Groups, will summarise the existing NN frameworks, model description formats, accelerator solutions, low cost development boards and will describe the efforts underway to identify the best technologies to improve the consolidation and enable the competitive innovative advantage from all vendors.
Audience
The session will be useful for executives to engineers. Executives will gain a deeper understanding of the issues and opportunities. Engineers at NN acceleration IP design houses will take away ideas for how to collaborate in the open source community on their area of expertise, how to evaluate the performance and accelerate multiple NN frameworks without modifying them for each new IP, whether it be targeting edge computing gateways, smart devices or simple microcontrollers.
Benefits to the Ecosystem
The AI deep learning neural network ecosystem is starting just now and it has similar implications with open source as GPU and video accelerators had in the early days with user space drivers, binary blobs, proprietary APIs and all possible ways to protect their IPs. The session will outline a proposal for a collaborative ecosystem effort to create a common framework to manage multiple NN accelerators while at the same time avoiding to modify deep learning frameworks with multiple forks.
In this deck from ATPESC 2019, Ken Raffenetti from Argonne presents an overview of HPC interconnects.
"The Argonne Training Program on Extreme-Scale Computing (ATPESC) provides intensive, two-week training on the key skills, approaches, and tools to design, implement, and execute computational science and engineering applications on current high-end computing systems and the leadership-class computing systems of the future."
Watch the video: https://wp.me/p3RLHQ-luc
Learn more: https://extremecomputingtraining.anl.gov/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
"OpenHPC is a collaborative, community effort that initiated from a desire to aggregate a number of common ingredients required to deploy and manage High Performance Computing (HPC) Linux clusters including provisioning tools, resource management, I/O clients, development tools, and a variety of scientific libraries. Packages provided by OpenHPC have been pre-built with HPC integration in mind with a goal to provide re-usable building blocks for the HPC community. Over time, the community also plans to identify and develop abstraction interfaces between key components to further enhance modularity and interchangeability. The community includes representation from a variety of sources including software vendors, equipment manufacturers, research institutions, supercomputing sites, and others."
Watch the video: http://wp.me/p3RLHQ-gKz
Learn more: http://openhpc.community/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this deck from the 2019 UK HPC Conference, Dr. Oliver Perks from Arm presents: Arm as a Viable Architecture for HPC & AI.
"In the past two years Arm has transitioned from being a novelty research project for HPC to a viable candidate for large scale procurements. Through the advent of competitive processors, such as the Marvell ThunderX2, Arm is being taking increasingly seriously as an alternative to traditional X86 based supercomputers. Whilst the novelty lies within the architectural design, the most significant body of work has taken place in the ecosystem and applications space, ensuing a smooth transition for production scientific workloads. In this talk we will present the current status of Arm in HPC and scientific computing, and what to expect from future generations of Arm based processors. Additionally, we will cover the best practices for the adoption of Arm technology in a production HPC setting."
Watch the video: https://wp.me/p3RLHQ-kV5
Learn more: https://developer.arm.com/solutions/hpc
and
http://hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this deck from the Argonne Training Program on Extreme-Scale Computing 2019, Howard Pritchard from LANL and Simon Hammond from Sandia present: NNSA Explorations: ARM for Supercomputing.
"The Arm-based Astra system at Sandia will be used by the National Nuclear Security Administration (NNSA) to run advanced modeling and simulation workloads for addressing areas such as national security, energy and science.
"By introducing Arm processors with the HPE Apollo 70, a purpose-built HPC architecture, we are bringing powerful elements, like optimal memory performance and greater density, to supercomputers that existing technologies in the market cannot match,” said Mike Vildibill, vice president, Advanced Technologies Group, HPE. “Sandia National Laboratories has been an active partner in leveraging our Arm-based platform since its early design, and featuring it in the deployment of the world’s largest Arm-based supercomputer, is a strategic investment for the DOE and the industry as a whole as we race toward achieving exascale computing.”
Watch the video: https://wp.me/p3RLHQ-l29
Learn more: https://insidehpc.com/2018/06/arm-goes-big-hpe-builds-petaflop-supercomputer-sandia/
and
https://extremecomputingtraining.anl.gov/agenda-2019/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Tutti i dati aggiornati al 27 marzo 2015 sull’edilizia scolastica presentati al Miur in conferenza stampa dal Sottosegretario Davide Faraone.
http://passodopopasso.italia.it/temi/scuola/risorse-monitoraggio-trasparenza-il-quadro-sulledilizia-scolastica
Accelerating Hadoop, Spark, and Memcached with HPC Technologiesinside-BigData.com
DK Panda from Ohio State University presented this deck at the OpenFabrics Workshop.
"Modern HPC clusters are having many advanced features, such as multi-/many-core architectures, highperformance RDMA-enabled interconnects, SSD-based storage devices, burst-buffers and parallel file systems. However, current generation Big Data processing middleware (such as Hadoop, Spark, and Memcached) have not fully exploited the benefits of the advanced features on modern HPC clusters. This talk will present RDMA-based designs using OpenFabrics Verbs and heterogeneous storage architectures to accelerate multiple components of Hadoop (HDFS, MapReduce, RPC, and HBase), Spark and Memcached. An overview of the associated RDMA-enabled software libraries (being designed and publicly distributed as a part of the HiBD project for Apache Hadoop (integrated and plug-ins for Apache, HDP, and Cloudera distributions), Apache Spark and Memcached will be presented. The talk will also address the need for designing benchmarks using a multi-layered and systematic approach, which can be used to evaluate the performance of these Big Data processing middleware."
Watch the video presentation: http://wp.me/p3RLHQ-gzg
Learn more: http://hibd.cse.ohio-state.edu/
and
https://www.openfabrics.org/index.php/abstracts-agenda.html
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Macromolecular crystallography is an experimental technique allowing to explore 3D atomic structure of proteins, used by academics for research in biology and by pharmaceutical companies in rational drug design. While up to now development of the technique was limited by scientific instruments performance, recently computing performance becomes a key limitation. In my presentation I will present a computing challenge to handle 18 GB/s data stream coming from the new X-ray detector. I will show PSI experiences in applying conventional hardware for the task and why this attempt failed. I will then present how IC 922 server with OpenCAPI enabled FPGA boards allowed to build a sustainable and scalable solution for high speed data acquisition. Finally, I will give a perspective, how the advancement in hardware development will enable better science by users of the Swiss Light Source.
Huawei’s requirements for the ARM based HPC solution readiness - Joshua MoraLinaro
Talk Title: Huawei’s requirements for the ARM based HPC solution readiness
Talk Abstract:
A high level review of a wide range of requirements to architect an ARM based competitive HPC solution is provided. The review combines both Industry and Huawei’s unique views with the intend to communicate openly not only the alignment and support in ongoing efforts carried over by other ARM key players but to brief on the areas of differentiation that Huawei is investing towards the research, development and deployment of homegrown ARM based HPC solution(s).
Speaker: Joshua Mora
Speaker Bio:
20 years of experience in research and development of both software and hardware for high performance computing. Currently leading the architecture definition and development of ARM based HPC solutions, both hardware and software, all the way to the applications (ie. turnkey HPC solutions for different compute intensive markets where ARM will succeed !!).
This presentation covers various partners and collaborators who are currently working with OpenPOWER foundation ,Use cases of OpenPOWER systems in multiple Industries , OpenPOWER Workgroups and OpenCAPI features .
"Algorithmic processing performed in High Performance Computing environments impacts the lives of billions of people, and planning for exascale computing presents significant power challenges to the industry. ARM delivers the enabling technology behind HPC. The 64-bit design of the ARMv8-A architecture combined with Advanced SIMD vectorization are ideal to enable large scientific computing calculations to be executed efficiently on ARM HPC machines. In addition ARM and its partners are working to ensure that all the software tools and libraries, needed by both users and systems administrators, are provided in readily available, optimized packages."
Learn more: https://developer.arm.com/hpc
and
http://hpcuserforum.com
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Implementing AI: High Performance Architectures: Large scale HPC hardware in ...KTN
The Implementing AI: High Performance Architectures webinar, hosted by KTN and eFutures, was the fourth event in the Implementing AI webinar series.
The focus of the webinar was the impact of processing AI data on data centres - particularly from the technology perspective. Prof. Simon McIntosh-Smith, Professor in High Performance Computing, University of Bristol, covered Large scale HPC hardware in the age of AI.
In this deck from the HPC Advisory Council Spain Conference, Dan Olds from OrionX discusses the High Performance Interconnect (HPI) market landscape, plus provides ratings and rankings of HPI choices today.
"The HPI market is the very high-end of the networking equipment market where high bandwidth and low latency are non-negotiable. It started out as a specialist proprietary segment but has blossomed into an indispensable, large, and growing area. Products in this category are used to build extreme-scale computing systems. They are typically not used for traditional telco, enterprise, or service provider networking needs. In this talk, we’ll take a look at the technologies and performance of their high-end technology and the coming battle between onloading vs. offloading interconnect architectures."
Watch the video presentation: http://wp.me/p3RLHQ-fON
Learn more: http://orionx.net/wp-content/uploads/2016/06/HPI-Environment-OrionX-Constellation-DataCenter-20160626.pdf
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this video from the HPC User Forum in Santa Fe, Yoonho Park from IBM presents: IBM Datacentric Servers & OpenPOWER.
"Big data analytics, machine learning and deep learning are among the most rapidly growing workloads in the data center. These workloads have the compute performance requirements of traditional technical computing or high performance computing, coupled with a much larger volume and velocity of data."
Watch the video: http://wp.me/p3RLHQ-gJv
Learn more: https://openpowerfoundation.org/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this video from the Rice Oil & Gas Conference, Brent Gorda from ARM presents: ARM in HPC.
"With the recent Astra system at Sandia Lab (#203 on the Top500) and HPE Catalyst project in the UK, Arm-based architectures are arriving in HPC environments. Several partners have announced or will soon announce new silicon and projects, each of which offers something different and compelling for our community. Brent will describe the driving factors and how these solutions are changing the landscape for HPC."
Watch the video: https://wp.me/p3RLHQ-jXS
Learn more: https://developer.arm.com/hpc
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this deck from the Linaro Connect conference, Brent Gorda presents an update on ARM for HPC.
"Arm-based systems are showing up in the HPC community and new silicon is coming. The architecture has also been selected for several of the exascale projects worldwide. Brent will talk about the aspects of Arm that are attractive to the HPC community, updates on projects and what we as a community can do to help accelerate adoption in this space."
Watch the video: https://insidehpc.com/2019/09/an-update-on-arm-in-hpc/
Learn more: https://developer.arm.com/tools-and-software/server-and-hpc
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Deep Learning Neural Network Acceleration at the Edge - Andrea GalloLinaro
Short
The growing amount of data captured by sensors and the real time constraints imply that not only big data analytics but also Machine Learning (ML) inference shall be executed at the edge. The multiple options for neural network acceleration in Arm-based platforms provide an unprecedented opportunity for new intelligent devices. It also raises the risk of fragmentation and duplication of efforts when multiple frameworks shall support multiple accelerators.
Andrea Gallo, Linaro VP of Segment Groups, will summarise the existing NN frameworks, accelerator solutions, and will describe the efforts underway in the Arm ecosystem.
Abstract
The dramatically growing amount of data captured by sensors and the ever more stringent requirements for latency and real time constraints are paving the way for edge computing, and this implies that not only big data analytics but also Machine Learning (ML) inference shall be executed at the edge. The multiple options for neural network acceleration in recent Arm-based platforms provides an unprecedented opportunity for new intelligent devices with ML inference. It also raises the risk of fragmentation and duplication of efforts when multiple frameworks shall support multiple accelerators.
Andrea Gallo, Linaro VP of Segment Groups, will summarise the existing NN frameworks, model description formats, accelerator solutions, low cost development boards and will describe the efforts underway to identify the best technologies to improve the consolidation and enable the competitive innovative advantage from all vendors.
Audience
The session will be useful for executives to engineers. Executives will gain a deeper understanding of the issues and opportunities. Engineers at NN acceleration IP design houses will take away ideas for how to collaborate in the open source community on their area of expertise, how to evaluate the performance and accelerate multiple NN frameworks without modifying them for each new IP, whether it be targeting edge computing gateways, smart devices or simple microcontrollers.
Benefits to the Ecosystem
The AI deep learning neural network ecosystem is starting just now and it has similar implications with open source as GPU and video accelerators had in the early days with user space drivers, binary blobs, proprietary APIs and all possible ways to protect their IPs. The session will outline a proposal for a collaborative ecosystem effort to create a common framework to manage multiple NN accelerators while at the same time avoiding to modify deep learning frameworks with multiple forks.
In this deck from ATPESC 2019, Ken Raffenetti from Argonne presents an overview of HPC interconnects.
"The Argonne Training Program on Extreme-Scale Computing (ATPESC) provides intensive, two-week training on the key skills, approaches, and tools to design, implement, and execute computational science and engineering applications on current high-end computing systems and the leadership-class computing systems of the future."
Watch the video: https://wp.me/p3RLHQ-luc
Learn more: https://extremecomputingtraining.anl.gov/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
"OpenHPC is a collaborative, community effort that initiated from a desire to aggregate a number of common ingredients required to deploy and manage High Performance Computing (HPC) Linux clusters including provisioning tools, resource management, I/O clients, development tools, and a variety of scientific libraries. Packages provided by OpenHPC have been pre-built with HPC integration in mind with a goal to provide re-usable building blocks for the HPC community. Over time, the community also plans to identify and develop abstraction interfaces between key components to further enhance modularity and interchangeability. The community includes representation from a variety of sources including software vendors, equipment manufacturers, research institutions, supercomputing sites, and others."
Watch the video: http://wp.me/p3RLHQ-gKz
Learn more: http://openhpc.community/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this deck from the 2019 UK HPC Conference, Dr. Oliver Perks from Arm presents: Arm as a Viable Architecture for HPC & AI.
"In the past two years Arm has transitioned from being a novelty research project for HPC to a viable candidate for large scale procurements. Through the advent of competitive processors, such as the Marvell ThunderX2, Arm is being taking increasingly seriously as an alternative to traditional X86 based supercomputers. Whilst the novelty lies within the architectural design, the most significant body of work has taken place in the ecosystem and applications space, ensuing a smooth transition for production scientific workloads. In this talk we will present the current status of Arm in HPC and scientific computing, and what to expect from future generations of Arm based processors. Additionally, we will cover the best practices for the adoption of Arm technology in a production HPC setting."
Watch the video: https://wp.me/p3RLHQ-kV5
Learn more: https://developer.arm.com/solutions/hpc
and
http://hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
In this deck from the Argonne Training Program on Extreme-Scale Computing 2019, Howard Pritchard from LANL and Simon Hammond from Sandia present: NNSA Explorations: ARM for Supercomputing.
"The Arm-based Astra system at Sandia will be used by the National Nuclear Security Administration (NNSA) to run advanced modeling and simulation workloads for addressing areas such as national security, energy and science.
"By introducing Arm processors with the HPE Apollo 70, a purpose-built HPC architecture, we are bringing powerful elements, like optimal memory performance and greater density, to supercomputers that existing technologies in the market cannot match,” said Mike Vildibill, vice president, Advanced Technologies Group, HPE. “Sandia National Laboratories has been an active partner in leveraging our Arm-based platform since its early design, and featuring it in the deployment of the world’s largest Arm-based supercomputer, is a strategic investment for the DOE and the industry as a whole as we race toward achieving exascale computing.”
Watch the video: https://wp.me/p3RLHQ-l29
Learn more: https://insidehpc.com/2018/06/arm-goes-big-hpe-builds-petaflop-supercomputer-sandia/
and
https://extremecomputingtraining.anl.gov/agenda-2019/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Tutti i dati aggiornati al 27 marzo 2015 sull’edilizia scolastica presentati al Miur in conferenza stampa dal Sottosegretario Davide Faraone.
http://passodopopasso.italia.it/temi/scuola/risorse-monitoraggio-trasparenza-il-quadro-sulledilizia-scolastica
Accelerating Hadoop, Spark, and Memcached with HPC Technologiesinside-BigData.com
DK Panda from Ohio State University presented this deck at the OpenFabrics Workshop.
"Modern HPC clusters are having many advanced features, such as multi-/many-core architectures, highperformance RDMA-enabled interconnects, SSD-based storage devices, burst-buffers and parallel file systems. However, current generation Big Data processing middleware (such as Hadoop, Spark, and Memcached) have not fully exploited the benefits of the advanced features on modern HPC clusters. This talk will present RDMA-based designs using OpenFabrics Verbs and heterogeneous storage architectures to accelerate multiple components of Hadoop (HDFS, MapReduce, RPC, and HBase), Spark and Memcached. An overview of the associated RDMA-enabled software libraries (being designed and publicly distributed as a part of the HiBD project for Apache Hadoop (integrated and plug-ins for Apache, HDP, and Cloudera distributions), Apache Spark and Memcached will be presented. The talk will also address the need for designing benchmarks using a multi-layered and systematic approach, which can be used to evaluate the performance of these Big Data processing middleware."
Watch the video presentation: http://wp.me/p3RLHQ-gzg
Learn more: http://hibd.cse.ohio-state.edu/
and
https://www.openfabrics.org/index.php/abstracts-agenda.html
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
září - měsíc kohouta, jak využít kohoutí energie v byznysu, jak si upravit interiér v září, co psychologové nedokážou, nechte se nést vlnami života - flow
presentazione sintetica della tesi di alberto.garniga@gmail.com sul PBL come leva per l'innovazione organizzativa, metodologica e tecniologica nella scuola italiana.
A most wonderful characteristic of the Bible is its perfect consistency. That is, the entire Bible is perfectly true and trustworthy. Therefore, when any truth has been correctly learned from the Bible, that truth will never be negated or compromised by other Bible citations. This perfect consistency of the Bible is to be expected because the Bible is God’s Word.
This presentation discusses the following topics:
1. the three types of mobile architecture that are available in the market today
2. Oracle MAF
3. Impact on your services
4. Impact on security
5. Impact on scalability
6. Three uses cases to illustrate the previous topics
7. Summary
Arm A64fx and Post-K: Game-Changing CPU & Supercomputer for HPC, Big Data, & AIinside-BigData.com
Satoshi Matsuoka from RIKEN gave this talk at the HPC User Forum in Santa Fe.
"With rapid rise and increase of Big Data and AI as a new breed of high-performance workloads on supercomputers, we need to accommodate them at scale, and thus the need for R&D for HW and SW Infrastructures where traditional simulation-based HPC and BD/AI would converge, in a BYTES-oriented fashion. Post-K is the flagship next generation national supercomputer being developed by Riken and Fujitsu in collaboration. Post-K will have hyperscale class resource in one exascale machine, with well more than 100,000 nodes of sever-class A64fx many-core Arm CPUs, realized through extensive co-design process involving the entire Japanese HPC community.
Rather than to focus on double precision flops that are of lesser utility, rather Post-K, especially its Arm64fx processor and the Tofu-D network is designed to sustain extreme bandwidth on realistic applications including those for oil and gas, such as seismic wave propagation, CFD, as well as structural codes, besting its rivals by several factors in measured performance. Post-K is slated to perform 100 times faster on some key applications c.f. its predecessor, the K-Computer, but also will likely to be the premier big data and AI/ML infrastructure. Currently, we are conducting research to scale deep learning to more than 100,000 nodes on Post-K, where we would obtain near top GPU-class performance on each node."
Watch the video: https://wp.me/p3RLHQ-k6G
Learn more: https://en.wikichip.org/wiki/supercomputers/post-k
and
http://hpcuserforum.com
A New Direction for Computer Architecture Researchdbpublications
This paper we suggest a different computing environment as a worthy new direction for computer architecture research: personal mobile computing, where portable devices are used for visual computing and personal communications tasks. Such a device supports in an integrated fashion all the functions provided to-day by a portable computer, a cellular phone, a digital camera and a video game. The requirements placed on the processor in this environment are energy efficiency, high performance for multimedia and DSP functions, and area efficient, scalable designs. We examine the architectures that were recently pro-posed for billion transistor microprocessors. While they are very promising for the stationary desktop and server workloads, we discover that most of them are un-able to meet the challenges of the new environment and provide the necessary enhancements for multimedia applications running on portable devices.
Stay up-to-date on the latest news, events and resources for the OpenACC community. This month’s highlights covers the newly elected OpenACC.org vice president, 2019 OpenACC Annual Meeting, GPU Bootcamp at RIKEN R-CCS, a complete schedule of GPU hackathons and more!
OpenACC and Open Hackathons Monthly Highlights June 2022.pdfOpenACC
Stay up-to-date with the OpenACC and Open Hackathons Monthly Highlights. June’s edition covers the 2022 OpenACC and Hackathons Summit, NSF’s Traineeship Program, NVIDIA’s Academic Hardware Grant program, upcoming Open Hackathons and Bootcamps, recent research, new resources, and more!
In this video from the Argonne Training Program on Extreme-Scale Computing 2019, Jeffrey Vetter from ORNL presents: The Coming Age of Extreme Heterogeneity.
"In this talk, I'm going to talk about the high-level trends guiding our industry. Moore’s Law as we know it is definitely ending for either economic or technical reasons by 2025. Our community must aggressively explore emerging technologies now!"
Watch the video: https://wp.me/p3RLHQ-lic
Learn more: https://ft.ornl.gov/~vetter/
and
https://extremecomputingtraining.anl.gov/archive/atpesc-2019/agenda-2019/
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Linux has become one of the most important software to run the civil infrastructure systems such as power plants, water distribution, traffic control and healthcare. From computer system viewpoint, the systems require a very high level of quality on real-time performance, reliability and security to avoid serious failure. To overcome the issues to apply Linux on such systems, as the first step, we need to gather the actual requirements. Past few months, some companies who are interested in this area actually got together and discussed to put those requirements together. In this talk, we would like to share the current status of this requirement discussion and our future collaboration plan. Please join us to improve Linux together and make the world better place!
Stay up-to-date on the latest news, events and resources for the OpenACC community. This month’s highlights covers the newly released PGI 19.7, the upcoming 2019 OpenACC Annual Meeting, GPU Bootcamp at RIKEN R-CCS, a complete schedule of GPU hackathons and more!
OpenACC and Open Hackathons Monthly Highlights: July 2022.pptxOpenACC
Stay up-to-date with the OpenACC and Open Hackathons Monthly Highlights. July’s edition covers the 2022 OpenACC and Hackathons Summit, NVIDIA’s Applied Research Accelerator Program, upcoming Open Hackathons and Bootcamps, recent research, new resources, and more!
This lecture aims to give some food for thought regarding how the current High Performance Computing systems (hardware and software) tends to merge with Big Data ones (Machine Learning, Analytics and Enterprise workloads) in order to meet both workloads demands sharing the same clusters.
Stay up-to-date with the OpenACC Monthly Highlights. July's edition covers the OpenACC Summit 2021, upcoming GPU Hackathons and Bootcamps, PEARC21 panel review , recent research, new resources and more!
As a Presidio Fellow in Sustainability and Sports, at the Presidio Graduate School, San Francisco, CA, [http://www.presidio.edu/academics/presidiopro/certificates/sports- sustainability] I presented a class on energy efficiency and solar in sports stadiums and arenas. It covers related issues of advanced BIM (Building Information Modeling or Building Intelligence Management), Internet of Everything (IoT), continuous commissioning over building lifecycle, LED lighting systems, and more.
In this deckfrom the 2017 DDN User Group meeting at ISC, Judit Planas, Postdoctoral Researcher at Ecole Polytechnique Federale de Lausanne (EPFL) presents I/O Challenges in Brain Tissue Simulation (IME Neuromapp).
Learn more: https://insidehpc.com/2017/08/video-io-challenges-brain-tissue-simulation/
and
http://ddn.com
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Similar to ARM-based Supercomputer from Fujitsu and RIKEN - "Post-K" (20)
Welcome to the first live UiPath Community Day Dubai! Join us for this unique occasion to meet our local and global UiPath Community and leaders. You will get a full view of the MEA region's automation landscape and the AI Powered automation technology capabilities of UiPath. Also, hosted by our local partners Marc Ellis, you will enjoy a half-day packed with industry insights and automation peers networking.
📕 Curious on our agenda? Wait no more!
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Lovely Sinha, UiPath Community Chapter Leader, UiPath MVPx3, Hyper-automation Consultant, First Abu Dhabi Bank
10:20 A UiPath cross-region MEA overview
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12:15 To discover how Marc Ellis leverages tech-driven solutions in recruitment and managed services.
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91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
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Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
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Global APT activity, AI usage, actor and tactic profiles, and implications
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Enhancing Performance with Globus and the Science DMZ
ARM-based Supercomputer from Fujitsu and RIKEN - "Post-K"
1. The Next Flagship Supercomputer in Japan
Yutaka Ishikawa, Project Leader
AICS RIKEN
02:15 pm ‐ 02:45 pm, June 21, 2016
2. Outline of Talk
Introduction of the project
An Overview of the Japanese next flagship supercomputer, so-
called post K
Introduction of International Collaborations
System software stack for post K is being developed with
international collaborations
Concluding Remarks
2ISC'16, June 21, 2016
3. Flagship 2020 project
Developing the next Japanese flagship computer,
so-called “post K”
3
Disaster prevention
and global climate
Energy issues Industrial competitiveness Basic science
Society with health
and longevity
Developing a wide range of application codes,
to run on the “post K”, to solve major social
and science issues
Vendor partner
The Japanese government selected 9 social &
scientific priority issues and their R&D
organizations.
ISC'16, June 21, 2016
4. Disaster prevention
and global climate
Energy issues Industrial competitiveness Basic science
Society with health
and longevity
R&D Organization
4
Target ApplicationsArchitectural Parameters
• #SIMD, SIMD length, #core, #NUMA node
• cache (size and bandwidth)
• memory technologies
• specialized hardware
• Interconnect
• I/O network
ISC'16, June 21, 2016
To build an efficient execution environment in terms of
Power consumption,
Productivity, and
Usability
Application developers are involved in the design
5. Disaster prevention
and global climate
Energy issues Industrial competitiveness Basic science
Society with health
and longevity
R&D Organization
5
Target Applications
Architectural Parameters
• #SIMD, SIMD length, #core, #NUMA node
• cache (size and bandwidth)
• memory technologies
• specialized hardware
• Interconnect
• I/O network
ISC'16, June 21, 2016
To build an efficient execution environment in terms of
Power consumption,
Productivity, and
Usability
Application developers are involved in the design
Mutual understanding both
computer architecture/system software and applications
Looking at performance predictions
Finding out the best solution with constraints, e.g., power
consumption, budget, and space
Prediction of node-level
performance
Profiling applications,
e.g., cache misses
and execution unit
usages
Prediction Tool
Prediction of scalability
(latency and bandwidth)
6. Disaster prevention
and global climate
Energy issues Industrial competitiveness Basic science
Society with health
and longevity
R&D Organization
6
Target Applications
ISC'16, June 21, 2016
• DOE‐MEXT
• JLESC
• …
International
Collaboration
•
• HPCI Consortium
• PC Cluster Consortium
• OpenHPC
• …
Communities
• Univ. of Tsukuba
• Univ. of Tokyo
• Kyoto Univ.
Domestic
Collaboration
7. An Overview of post K
Hardware
Manycore architecture
6D mesh/torus Interconnect
3-level hierarchical storage system
Silicon Disk
Magnetic Disk
Storage for archive
7
Target performance:
100 times (maximum) of K by the capacity computing
50 times (maximum) of K by the capability computing
Power consumption of 30 - 40MW (cf. K computer: 12.7 MW)
Login
Servers
Login
Servers
Maintenance
Servers
Maintenance
Servers
I/O NetworkI/O Network
……
…
…
…
…
…
…
…
…
…
… Hierarchical
Storage System
Hierarchical
Storage System
Portal
Servers
Portal
Servers
System Software
Multi-Kernel: Linux with Light-weight Kernel
File I/O middleware for 3-level hierarchical storage
system and application
Application-oriented file I/O middleware
MPI+OpenMP programming environment
Highly productive programing language and libraries
ISC'16, June 21, 2016
8. What we have done
Software
OS functional design
Communication functional design
File I/O functional design
Programming languages
Mathematical libraries
8
• Node architecture
• System configuration
• Storage system
Continue to design
Hardware
Instruction set architecture
ISC'16, June 21, 2016
9. Instruction Set Architecture
ARM V8 HPC Extension
Fujitsu is a lead partner of ARM HPC extension development
Detailed features will be announced at Hot Chips 28 - 2016
9
http://www.hotchips.org/program/
Mon 8/22 Day1 9:45AM GPUs & HPCs
ARMv8‐A Next Generation Vector Architecture for HPC
Fujitsuʼs inheritances
FMA
Math acceleration primitives
Inter core barrier
Sector cache
Hardware prefetch assist
ISC'16, June 21, 2016
10. Outline of Talk
Introduction of FLAGSHIP2020 project
An Overview of post K system
Introduction of International Collaborations
Concluding Remarks
10
*The Icon is made by Freepik from www.flaticon.com
More than 10 research topics
Collaboration Categories
◎ Collaborative development of open source software
◎ Evaluation and analysis of benchmarks and technologies
◎ Standardization of mature technologies
◎ Pre-standardization interface coordination
◎ Collection and publication of open data
ISC'16, June 21, 2016
11. System Software Collaboration: Example (DOE-MEXT)
11
In terms of Collaborative development of open source software
• Argonne contribution: CH4 hackathon for LLC
• AICS contribution: a part of CH4 implementation
• Memory management for new memory hierarchy
• MPICH and LLC communication libraries
MPICH Software Structure
CH4: the successor of CH3, the current
abstract network device interface
◎ Collaborative development of open source software◎ Evaluation and analysis of benchmarks and technologies
ISC'16, June 21, 2016
12. System Software Collaboration: Example (DOE-MEXT)
12
Northwestern
University
• I/O Benchmarks and pnetCDF
implementations for Scientific
Big Data
PI: Takemasa Miyoshi, RIKEN AICS
“Innovating Big Data Assimilation technology for revolutionizing very‐short‐
range severe weather prediction”
An innovative 30-second super-rapid update numerical weather prediction system for 30-minute/1-
hour severe weather forecasting will be developed, aiding disaster prevention and mitigation, as well
as bringing a scientific breakthrough in meteorology.
The results of 100 ensemble simulations are read by
data assimilation processes and data size in total is
over 1.7 TB
◎ Collaborative development of open source software
ISC'16, June 21, 2016
13. System Software Collaboration: Example
13
• Twice meetings per year
• A researcher visits Intel for a few months
Lightweight kernel
McKernel is running on Intel Xeon and Xeon phi
• Understanding benefit of lightweight kernel
• Understanding differences of McKernel and mOS
• Standardization of API for lightweight kernel (Plan)
intel
◎ Evaluation and analysis of benchmarks and technologies ◎ Pre-standardization interface coordination
ISC'16, June 21, 2016
14. System Software Collaboration: Example (DOE-MEXT)
14
AICS and U Houston, U Tsukuba:
Extension of PGAS (Partitioned Global Address Space)
model with language constructs of multitasking
(multithreading) for manycore‐based exascale systems
(XcalableMP 2.0)
XMP, XcalableMP, is a directive-based language for distributed memory systems
• PGAS language for large scale distributed memory system
• HPF‐like concept and OpenMP‐like description with directives
• Two memory models: Global View and Local View
• Global View: PGAS, image of large array distributed into partial ones in nodes
• Local view: MPI‐like + Coarray notation is allowed
◎ Collaborative development of open source software◎ Evaluation and analysis of benchmarks and technologies
ANL and AICS, U. Tsukuba:
Runtime design for PGAS communication and
multitasking using Argobot light‐weight user‐
level thread.
ISC'16, June 21, 2016
15. Concluding Remarks
Fujitsu decided that post Kʼs CPU is based on ARM V8 with
HPC extension
The usability will be improved than the K computer by
changing architecture
More wide-range community support
The system software stack for Post K is being designed and
implemented with the leverage of international
collaborations
The software stack developed at RIKEN is Open source
It also runs on Intel Xeon and Xeon phi
RIKEN would like to contribute to OpenHPC
15ISC'16, June 21, 2016