ARM® Cortex™ M Energy Optimization 
Techniques - Using Instruction Cache 
Raahul Anand Raghavan, Lead Systems Architect, 
Glyton Solutions 
!1
Agenda 
• Before We Proceed! 
• Importance of energy optimization with Cortex M profile in 
context 
• Instruction cache in ARM® Cortex™ M 
• Energy Profiling & Results comparison 
• Turn ON I-CACHE 
• Turn OFF I-CACHE 
• Concludes 
!2
Before We Proceed! 
• In this presentation, we will be investigating role of 
I-CACHE when it comes to energy efficiency optimization 
• Involves Cortex M0+ based EVM and a suitable IDE 
• Official Documentation from ARM®, Silicon Labs will 
override information provided here. Treat official TRM’s as 
complete guides on Subject Matter 
• ARM® Cortex® M trademark - ARM Ltd 
• EFM®32, Silicon Labs SDK etc are registered trademarks 
!3
ARM® Cortex™ M Importance of Energy Optimization (1 / 2) 
• Typical products - Cortex M usage scenarios 
• Perpetually powered sensor products for industrial control 
• Energy harvesting is one key technology used to charge the battery pack when it comes to 
perpetually powered low power consumption sensor products 
• Products powering IOT (Internet of Things) 
• Wearable products catering to 
• Fitness trackers 
• Elderly / Patient assistance 
• …. 
• Whats one critical factor judging better end user / enterprise experience across all the products 
above ? 
• ALWAYS ON functionality 
• How do we achieve ALWAYS ON functionality ? 
• Best in class energy efficiency 
!4
ARM® Cortex™ M Importance of Energy Optimization (2 / 2) 
• What would be one of the best methods for extreme energy efficiency ? 
• Taking advantage of Architectural features 
• We will be discussing how one such architectural feature in ARM® Cortex™ M micro-controllers 
• I CACHE - Instruction Cache 
!5 
ARM® Cortex™ 
Core 
Cache Look-Up 
Logic 
SRAM CACHE 
Implementation 
IDCOD MUX 
CODE 
Memory Space 
(NV-FLASH) 
ICODE! 
AHB-LITE BUS 
ICODE! 
AHB-LITE BUS 
Instruction Cache 
DCODE! 
AHB-LITE BUS 
IDCODE! 
AHB-LITE BUS
ICACHE Implementation - EFM32 MCU’s from Silicon Labs 
• ICACHE 
• Connected directly to Cortex M Core 
• Acts as memory access filter between processor core and memory system 
• Consists 
• Access filter 
• Look-up logic 
• 128x32 SRAM (512 Bytes) 
• How does it work ? 
• Access filter checks if instruction access address falls in code space 
• On match , cache look-up and SRAM is enabled and instruction fetch happens 
• If no match , then ICACHE is bypassed and access is forwarded to memory 
system , then to NV memory such as NAND flash 
!6
How does ICACHE Impact energy efficiency ? 
• In the absence of ICACHE 
• Every instruction in CODE section, gets fetched from 
external FLASH 
• This involves read routines are always costly as it 
involves external peripheral access 
• The read routines to fetch instructions from external NV 
memory such as NAND is always costly (in terms of 
current consumption) compared to on-chip components 
• Another factor is that , there could be a risk of involving 
multiple read cycles for fetching instructions from 
external flash 
!7
Energy Profiling Results (1 / 2) 
• Following data might give an idea with respect to what 
would be the impact of having ICACHE turned ON and OFF 
• ICACHE Turned ON / OFF in EFM32 Zero Gecko 
• API used — MSC_EnableCache(bool ); 
• Does required configuration to turn ON or OFF ICACHE in 
memory system controller 
• Simple application measuring ambient temperature used 
• Simplicity Studio - Energy Profiler from Silicon Labs 
• On Board J-LINK debugger 
!8
Energy Profiling Results (2 / 2) 
Average Current Consumption — 60.45μA 
Average Power — 200.78μA 
Total Energy — 36.50mJ 
Average Current Consumption — 73.03μA 
Average Power — 242.48μA 
Total Energy — 44.28mJ 
!9 
ICACHE ON 
ICACHE OFF
Concludes! 
• Lets ensure to 
• Take advantage of any architectural functionality when 
it comes to achieving high energy efficiency 
• Take advantage of any ARM® Cortex™ M, silicon 
implementer specific functionality when it comes to 
achieving high energy efficiency 
!10

ARM® Cortex™ M Energy Optimization - Using Instruction Cache

  • 1.
    ARM® Cortex™ MEnergy Optimization Techniques - Using Instruction Cache Raahul Anand Raghavan, Lead Systems Architect, Glyton Solutions !1
  • 2.
    Agenda • BeforeWe Proceed! • Importance of energy optimization with Cortex M profile in context • Instruction cache in ARM® Cortex™ M • Energy Profiling & Results comparison • Turn ON I-CACHE • Turn OFF I-CACHE • Concludes !2
  • 3.
    Before We Proceed! • In this presentation, we will be investigating role of I-CACHE when it comes to energy efficiency optimization • Involves Cortex M0+ based EVM and a suitable IDE • Official Documentation from ARM®, Silicon Labs will override information provided here. Treat official TRM’s as complete guides on Subject Matter • ARM® Cortex® M trademark - ARM Ltd • EFM®32, Silicon Labs SDK etc are registered trademarks !3
  • 4.
    ARM® Cortex™ MImportance of Energy Optimization (1 / 2) • Typical products - Cortex M usage scenarios • Perpetually powered sensor products for industrial control • Energy harvesting is one key technology used to charge the battery pack when it comes to perpetually powered low power consumption sensor products • Products powering IOT (Internet of Things) • Wearable products catering to • Fitness trackers • Elderly / Patient assistance • …. • Whats one critical factor judging better end user / enterprise experience across all the products above ? • ALWAYS ON functionality • How do we achieve ALWAYS ON functionality ? • Best in class energy efficiency !4
  • 5.
    ARM® Cortex™ MImportance of Energy Optimization (2 / 2) • What would be one of the best methods for extreme energy efficiency ? • Taking advantage of Architectural features • We will be discussing how one such architectural feature in ARM® Cortex™ M micro-controllers • I CACHE - Instruction Cache !5 ARM® Cortex™ Core Cache Look-Up Logic SRAM CACHE Implementation IDCOD MUX CODE Memory Space (NV-FLASH) ICODE! AHB-LITE BUS ICODE! AHB-LITE BUS Instruction Cache DCODE! AHB-LITE BUS IDCODE! AHB-LITE BUS
  • 6.
    ICACHE Implementation -EFM32 MCU’s from Silicon Labs • ICACHE • Connected directly to Cortex M Core • Acts as memory access filter between processor core and memory system • Consists • Access filter • Look-up logic • 128x32 SRAM (512 Bytes) • How does it work ? • Access filter checks if instruction access address falls in code space • On match , cache look-up and SRAM is enabled and instruction fetch happens • If no match , then ICACHE is bypassed and access is forwarded to memory system , then to NV memory such as NAND flash !6
  • 7.
    How does ICACHEImpact energy efficiency ? • In the absence of ICACHE • Every instruction in CODE section, gets fetched from external FLASH • This involves read routines are always costly as it involves external peripheral access • The read routines to fetch instructions from external NV memory such as NAND is always costly (in terms of current consumption) compared to on-chip components • Another factor is that , there could be a risk of involving multiple read cycles for fetching instructions from external flash !7
  • 8.
    Energy Profiling Results(1 / 2) • Following data might give an idea with respect to what would be the impact of having ICACHE turned ON and OFF • ICACHE Turned ON / OFF in EFM32 Zero Gecko • API used — MSC_EnableCache(bool ); • Does required configuration to turn ON or OFF ICACHE in memory system controller • Simple application measuring ambient temperature used • Simplicity Studio - Energy Profiler from Silicon Labs • On Board J-LINK debugger !8
  • 9.
    Energy Profiling Results(2 / 2) Average Current Consumption — 60.45μA Average Power — 200.78μA Total Energy — 36.50mJ Average Current Consumption — 73.03μA Average Power — 242.48μA Total Energy — 44.28mJ !9 ICACHE ON ICACHE OFF
  • 10.
    Concludes! • Letsensure to • Take advantage of any architectural functionality when it comes to achieving high energy efficiency • Take advantage of any ARM® Cortex™ M, silicon implementer specific functionality when it comes to achieving high energy efficiency !10