Aging aware reliable multiplier design with

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Engineering

Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Aging-Aware Reliable Multiplier Design With
Adaptive Hold Logic
Abstract—Digital multipliers are among the most critical arithmetic functional
units. The overall performance of these systems depends on the throughput of the
multiplier. Meanwhile, the negative bias temperature instability effect occurs when
a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold
voltage of the pMOS transistor, and reducing multiplier speed. A similar
phenomenon, positive biastemperature instability, occurs when an nMOS transistor
is under positive bias. Both effects degrade transistor speed, and in the long term,
the system may fail due to timing violations. Therefore, it is important to design
reliable high-performance multipliers. In this paper, we propose an aging-aware
multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is
able to provide higher throughput through the variable latency and can adjust the
AHL circuit to mitigate performance degradation that is due to the aging effect.
Moreover, the proposed architecture can be applied to a column- or row-bypassing
multiplier. The experimental results show that our proposed architecture with 16
×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28%
performance improvement, respectively, compared with 16×16 and 32×32 fixed-
latency column-bypassing multipliers. Furthermore, our proposed architecture with
16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and
69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-
latency row-bypassing multipliers.

SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com

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Aging aware reliable multiplier design with

1. Logic Mind Technologies Vijayangar (Near Maruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Abstract—Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive biastemperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed- latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed- latency row-bypassing multipliers.

2. SOFTWARE REQUIREMENT:  ModelSim6.4c.  Xilinx 9.1/13.2. HARDWARE REQUIREMENT:  FPGA Spartan 3. PROJECT FLOW: First Review: Literature Survey Paper Explanation Design of Project Project Enhancement explanation Second Review: Implementing 40% of Base Paper Third Review Implementing Remaining 60% of Base Paper with Future Enhancement (Modification) For More Details please contact Logic Mind Technologies Vijayangar (NearMaruthi Medicals), Bangalore-40 Ph: 8123668124 // 8123668066 Mail: logicmindtech@gmail.com

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