This PPT explains ADC conversion techniques

1. ANALOG TO DIGITAL
CONVERSION TECHNIQUES

2. TECHNIQUES
• Analog to digital converter are classified into general groups based on the
conversion techniques.
• One technique involves comparing a given analog signal with the internally
generated reference voltages. This group includes successive approximation,
flash, delta modulation (DM), and adaptive delta modulation and flash type
converters.
• The technique involves changing an analog signal into tie or frequency and
comparing these new parameters against known values. This group includes
integrator convertors and voltage-to-frequency convertors.

3. 4.Type of ADC’s using various conversion techniques:
• I. Single ramp or single slop
• II. Dual slope
• III. Successive approximation
• IV. Flash

4. SINGLE SLOPE ADC
• It consists of a ramp generator and BCD or binary counters.
• The figure shown below shows the single slope ADC.

5. • At the start, the reset signal is provided to the ramp generator and the
counters. Thus counters are resettled to 0’s.
• The analog input voltage Vin
• is applied to the positive terminal of the comparator.
• As this is more positive than the negative input, the comparator output goes
high. The output of ramp generator is applied to the negative terminal of
the comparator.
• The high output of the comparator enables the AND gate which allows clock
to reach to the counters and also the high output starts the ramp.
• The ramp voltage goes positive until it exceeds the input voltage. When it
exceeds Vin
• , comparator output goes low. This disables AND gate which in turn stops
the clock to the counters. The control circuitry provides the latch signal
which is used to latch the counter date. The rest signal resets the counters
to 0’s and also resets the ramp generator. The latched data is then
displayed using decoder and a display device.

6. • Let us consider the practical example to understand the
working. Assume that the clock frequency is 1 MHz. There are
four BCD counters and the inputs Vin
• is 2.000 V.
• Now let ramp has a slope of 1 V/ms as shown in the figure
below. As the input is 2.000 V, the ramp will take 2 ms to reach
to 2 V and to stop the clock to the counters.

7. • Now how many pulses will reach to the counters duting 2ms ? It can
be calculated from frequency of the clock. The number of pulses
reaching to the counter in 2 ms is
2 𝑚𝑠
(1/1𝑀𝐻𝑧)
=2000.
• The comparator output going high will strobe. The latches and send
the count to the displays. Inserting a decimal point at the proper
point in the seven segment display gives a reading of 2.000. But we
want binary output. In such case instead of BCD counters, binary
counters must be used, where output will be straight binary coded.
• The main limitations of this circuits are,
i. Its resolutions is less. Hence for applications which required
resolution of 9 part in 20,000 or more, this ADC is not stable.
ii. Variations in ramp generator due to time, temperature or input
voltage sensitivity also cause a lot of problems.

8. THANK YOU