COmputer organization unit 3

1. WHY AM I TEACHING WHAT I AM TEACHING
COMPUTER ORGANIZATION
Contd....
VNRVJIET: ECE : CO WIT & WIL
Unit 3

2. Micro-programmed Control Unit
Unit-3
Microprogrammed Control: Control memory, address
sequencing, micro program example, and design of control
unit, hardwired control, and micro programmed control.

3. Computer Instructions(USER)
Micro Instruction(ADD)
Micro operation(Program)

4. Important Terms
• Hardwired Control Unit : When the control signals are
generated by hardware using conventional logic design
techniques, the control unit is said to be hardwired.
• Micro programmed control unit :A control unit whose
binary control variables are stored in memory is called
a micro programmed control unit.
• Dynamic microprogramming :A more advanced
development known as dynamic micro-programming
permits a micro-program to be loaded initially from an
auxiliary memory such as a magnetic disk. Control units
that use dynamic microprogramming employ a
writable control memory. This type of memory can be
used for writing.

5. • Control Memory: Control Memory is the storage in
the micro-programmed control unit to store the
micro-program.
• Writeable Control Memory: Control Storage whose
contents can be modified, allow the change in micro-
program and Instruction set can be changed or
modified is referred as Writeable Control Memory.
• Control Word: The control variables at any given
time can be represented by a control word string of 1
's and 0's called a control word.

6. Micro-operations : In computer central processing units,
micro-operations (also known as a micro-ops or μ-ops)
are detailed low-level instructions used in some designs
to implement complex machine instructions (sometimes
termed macro-instructions in this context).
Micro-instruction : A symbolic micro-program can be
translated into its binary equivalent by means of an
assembler. Each line of the assembly language micro-
program defines a symbolic microinstruction. Each
symbolic microinstruction is divided into five fields:
label, micro-operations, CD, BR, and AD.

7. • Micro program: A sequence of microinstructions constitutes a
micro-program. Since alterations of the microprogram are not
needed once the control unit is in operation, the control memory
can be a read-only memory (ROM). ROM words are made
permanent during the hardware production of the unit. The use of
a micro program involves placing all control variables in words of
ROM for use by the control unit through successive read
operations. The content of the word in ROM at a given address
specifies a microinstruction.
• Microcode: Microinstructions can be saved by employing
subroutines that use common sections of microcode. For example,
the sequence of micro operations needed to generate the effective
address of the operand for an instruction is common to all memory
reference instructions. This sequence could be a subroutine that is
called from within many other routines to execute the effective
address computation.

8. Micro-programmed Control
• Control Memory
• Address Sequencing
• Micro-program Example
• Design of Control Unit

9. Figure: Structure of the Computer
A main memory,
which stores both
data and instructions
A control unit, which
interprets the instructions
in memory and causes
them to be executed.
Input/output
(I/O)
equipment
operated by the
control unit
(For Reference)

10. Figure: Computer Hardware Configuration
MUX
AR
10 0
PC
10 0
Address Memory
2048 x 16
MUX
DR
15 0
Arithmetic
logic and
shift unit
AC
15 0
SBR
6 0
CAR
6 0
Control memory
128 x 20
Control unit
(For Reference)

11. Control Unit for the basic computer
I
Instruction Register (IR)
15 14 13 12 11 - 0
3 x 8
decoder
7 6 5 4 3 2 1 0
Control
logic
gates
D0
15 14 . . . . 2 1 0
4 x 16
Sequence decoder
4-bit
sequence
counter
(SC)
Increment (INR)
Clear (CLR)
Clock
Other inputs
Control
outputs
D
T
T
7
15
0
CU consists of:
•Two decoders
•A sequence counter
•No. of control logic
gates
(For Reference)

12. Control Memory
• CONTROL MEMORY
– is a memory that is part of a control unit.
– Its function is to initiate sequences of Microoperations.
• MICROOPERATIONS
– These Microoperations (one or more ) are specified by Microinstruction.
– Complexity is derived from the number of sequences of microoperations.
• MICROINSTRUCTION
– Each word in control memory contains within it a microinstruction.
• CONTROL WORD
– is control variable represented by a string of 1's and 0‘s.
• MICROPROGRAM is
– a sequence of microinstructions.

13. • Micro programmed control unit
– A control unit whose binary control variables are
stored in memory.
• Control memory can be a read-only memory
(ROM)
• But Dynamic microprogramming (writable
control memory)
– permits a microprogram to be loaded initially
from an auxiliary memory such as a magnetic
disk.

14. • A microprogrammed control unit have two
separate memories:
– main memory
– control memory
• Main memory
– is available to the user for storing the programs.
– contents may alter when the data are manipulated
– user's program in it consists of machine
instructions and data

15. • Control Memory
– holds a fixed microprogram
– cannot be altered by the occasional user
– consists of microinstructions
• that specify various internal control signals for execution of
register micro-operations
– Each MACHINE INSTRUCTION initiates a series of
MICROINSTRUCTIONS in control memory
– These MICROINSTRUCTIONS generate the
MICROOPERATIONS
• to fetch the instruction from main memory
• to evaluate the effective address
• to execute the operation specified by the instruction
• to return control to the fetch phase in order to repeat the
cycle for the next instruction

16. TABLE:
Symbolic Microprogram
(Partial)
(For Reference)

17. Microprogrammed control Organization
• Control Address Register
– specifies the address of the microinstruction
• Control Data Register
– holds the Microinstruction read from Memory
– Called as Pipeline Register.
• Next Address
– must be determined, after these operations are executed
– may also be a function of external input conditions
Figure: Microprogrammed control organization

18. • Next address generator is sometimes called a
MICROPROGRAM SEQUENCER
– it determines the address sequence that is read
from control memory
• Typical functions of a microprogram sequencer
are
– incrementing the Control Address Register (CAR) by
one
– loading into the CAR an address
– transferring an external address, or loading an
initial address to start the control operations
Figure: Microprogrammed control organization

19. • System can operate without the control data
register by applying a single-phase clock to the
address register.
• Control word and next-address information are
taken directly from the control memory.
• ROM (Control Memory) operates as a
Combinational Circuit, with the address value as
the input and the corresponding word as the
output.
• In the example, assume a single-phase clock,
– Only Address Register receives clock pulses
– So NO need to use a Control Data Register
– Sequencer and Control Memory do NOT need a clock
as those are combinational circuits

20. • Main advantage of the micro-programmed
control
– once the hardware configuration is established, there
should be NO NEED for further HARDWARE or
WIRING CHANGES.
– If we want to establish a different control sequence
for the system, all we need to do is specify a
DIFFERENT SET OF MICROINSTRUCTIONS
(MICROPROGRAM) in control memory.

21. Address Sequencing
• Routine
– is a group of Microinstructions stored in control memory
• Each COMPUTER INSTRUCTION has its OWN MICROPROGRAM
ROUTINE (a sequence of microinstructions) in control memory.
• Address sequencing capabilities required in a control
memory are:
1. Incrementing of the Control Address Register (CAR)
2. Unconditional Branch or Conditional Branch, depending on
status bit conditions
3. A Mapping Process from the bits of the instruction to an
address for control memory
4. A facility for subroutine call and return

22. Figure: Selection of address for control memory
Figure shows a block diagram of
SELECTING the NEXT
MICROINSTRUCTION ADDRESS
CONTROL ADDRESS REGISTER (CAR)
receives the address from FOUR
DIFFERENT PATHS
• INCREMENTER increments the
content of the Control Address
Register (CAR) by one
• BRANCHING is achieved by
specifying the branch address in
one of the fields of the
microinstruction
– Conditional branching depends
on specific status bit in order to
determine its condition
• EXTERNAL ADDRESS is
transferred into control memory
via a MAPPING Logic Circuit
• RETURN ADDRESS for a
subroutine is stored in a
Subroutine Register (SBR)

23. Conditional Branching
• Status Conditions are special bits in the system
that provide parameter information such as
– carry-out of an adder
– sign bit of a number
– mode bits of an instruction
– input or output status conditions
• Branch address is specified by status bits,
together with the field in the microinstruction.
• Branch Logic provides decision-making
capabilities in the control unit.

24. • Branch Logic hardware may be implemented in a variety of
ways
– Test the specified condition and branch to the indicated
address if the condition is met;
– otherwise, the address register is incremented
– This can be implemented with a Multiplexer
• For Example, there are EIGHT status bit CONDITIONS in the
system
– Three bits (select bits) in the microinstruction are used to
specify any one of eight status bit conditions
– If the selected status bit is in the 1 state, multiplexer transfer
the branch address into CAR
– Otherwise, it is 0, multiplexer causes the address register to be
incremented
• An UNCONDITIONAL branch microinstruction loads the
branch address into the CAR from control memory

25. Mapping of Instruction
• For example (Fig.),
– A computer instruction has an operation code of 4 bits ( specifies 16
instructions)
– Assume Control Memory has 128 words (requires address of 7 bits)
• For each OPERATION CODE there exists a MICROPROGRAM ROUTINE in
control memory
• One simple MAPPING PROCESS that converts the 4-BIT OPERATION CODE to
a 7-BIT ADDRESS for CONTROL MEMORY is shown in Fig.
– This mapping consists of placing a 0 in the Most Significant Bit of the address,
– transferring the four operation code bits, and clearing the two Least Significant
Bits of the Control Address Register
• This provides for each COMPUTER INSTRUCTION a MICROPROGRAM
ROUTINE with a capacity of FOUR MICROINSTRUCTIONS
Fig.: Mapping from
INSTRUCTION CODE to
MICROINSTRUCTION ADDRESS

26. MAPPING OF INSTRUCTIONS
ADD Routine
AND Routine
LDA Routine
STA Routine
BUN Routine
0000
0001
0010
0011
0100
OP-codes of Instructions
ADD
AND
LDA
STA
BUN
0000
0001
0010
0011
0100
.
.
.
Direct Mapping
Address
0 0000 00
0 0001 00
0 0010 00
0 0011 00
0 0100 00
Mapping
Bits 0 xxxx 00
ADD Routine
Address
AND Routine
LDA Routine
STA Routine
BUN Routine
Control
Memory

27. • The mapping function is sometimes
implemented by means of an integrated called
programmable logic device or PLD
• A PLD is similar to ROM in concept, except that it
uses AND and OR gates with internal electronic
fuses
• The interconnection between inputs, AND gates,
OR gates, and outputs can be programmed as in
ROM
• A mapping function that can be expressed in
terms of Boolean expressions can be
implemented conveniently with a PLD.

28. Subroutines
• Microprograms that use subroutines must have a
provision for storing the RETURN address
• This may be accomplished by placing the
incremented output from the CAR into a subroutine
register and branching to beginning of the
subroutine
• The best way to structure a register file that stores
addresses for subroutines is to organize the
registers in a last-in, first-out (LIFO) stack

29. Microprogram Example
Computer Configuration
• The block diagram of the
computer configuration is
shown in Fig.
• It consists of two memory
units:
– a main memory for
storing instructions and
data
– a control memory for
storing the microprogram
• Four registers (AR, PC, DR,
AC)are associated with the
processor unit
• Two with the control unit
– Control Address Register
CAR
– a subroutine register SBR
Figure: Computer Hardware Configuration
MUX
AR
10 0
PC
10 0
Address Memory
2048 x 16
MUX
DR
15 0
Arithmetic
logic and
shift unit
AC
15 0
SBR
6 0
CAR
6 0
Control memory
128 x 20
Control unit

30. • Transfer of information among
the registers in the processor is
done through MULTIPLEXERS
rather than a common bus
– DR can receive information from
AC, PC, or Memory
– AR can receive information from
PC or DR
– PC can receive information only
from AR
• Arithmetic, logic, and shift unit
performs microoperations with
data from AC and DR and places
the result in AC
• Memory receives its address
from AR
• Input data written to memory
come from DR
• Data read from memory can go
only to DR
Figure: Computer Hardware Configuration
MUX
AR
10 0
PC
10 0
Address Memory
2048 x 16
MUX
DR
15 0
Arithmetic
logic and
shift unit
AC
15 0
SBR
6 0
CAR
6 0
Control memory
128 x 20
Control unit

31. • Fig (a) depicts COMPUTER INSTRUCTION format
• Fig (b) lists FOUR of the 16 possible Memory-Reference instructions
• each Computer Instruction must be Microprogrammed
Figure: COMPUTER INSTRUCTIONS

32. Microinstruction Format
• Microinstruction format for the Control Memory is shown in Fig.
• Microinstruction contains 20 bits
• These are divided into FOUR functional parts
• Microoperation Field
– Further divided into three fields F1, F2, and F3
• CD field
– selects status bit conditions
• BR field
– specifies the type of branch to be used
• AD field
– contains a branch address
– It is 7 bits wide, since the control memory has 128 = 27 words
Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

39. • Microoperations are sub-divided into
three fields of three bits each (F1,F2,F3)
• Three bits in each field are encoded to
specify 7 distinct micro-operations
(listed in Table)
TABLE: Symbols and Binary Code
for MICROINSTRUCTION fields

40. • This gives a total of 21 microoperations (7 from each field (F1,F2,F3))
• NO more than 3 microoperations can be chosen for one
Microinstruction
Example:
• A microinstruction can specify two simultaneous microoperations
from F2 and F3 and none from F1
• Nine bits of the microoperation fields will then be
000 100 101 (F1 F2 F3)
• Two or more conflicting microoperations CANNOT be specified
simultaneously
For example,
– a microoperation field 010 001 000 has NO MEANING
AC0 (F1) ACAC-DR (F2) NOP
– because it specifies the operations to clear AC to 0 and subtract DR
from AC at the same time

41. • TRANSFER-TYPE micro-
operations symbols use FIVE
letters
– First Two Letters designate the
Source Register
– Third Letter is always a ‘T’
– Last Two Letters designate the
Destination Register
For example,
– microoperation that specifies
the transfer
AC  DR (F1 = 100)
– has the symbol DRTAC, which
stands for a transfer from DR to
AC

42. • CD (Condition) field consists of TWO bits
• These bits are encoded to specify FOUR Status Bit Conditions (as listed in
Table)
– U,I,S and Z
• First condition is always a 1
– So, CD = 00 (symbol U) will always find the condition to be TRUE
– In conjunction with BR (branch) field, it provides an UNCONDITIONAL BRANCH
operation
• Indirect bit ‘I’ (bit 15 of DR) after an instruction is read from memory
• Sign bit of AC (bit 15 of AC) provides the next status bit
• Zero value ‘Z’ is a binary variable whose value
– is equal to 1 if all the bits in AC = 0
Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

43. • BR (Branch) field consists of TWO bits
• It is used, in conjunction with the address field AD, to choose the address of
the next microinstruction
– When BR = 00, the control performs a jump (JMP) operation (which is similar to a
branch)
– When BR = 01, it performs a call to subroutine (CALL) operation
• Two operations are identical except that
– a CALL microinstruction stores the RETURN address in the Subroutine Register
(SBR)
• JUMP and CALL operations depend on the value of the CD field
– If CD = 1 (indirect address bit), the next address in the AD field is transferred to the
Control Address Register (CAR)
– Otherwise, CAR is incremented by 1
Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

44. • RETURN from subroutine is accomplished with a BR = 10
– This causes the transfer of the return address from SBR to CAR
• MAPPING from the operation code bits of the instruction
to an address for CAR is accomplished when the BR = 11
• Last two conditions in the BR field are independent of the
values in the CD and AD fields
Figure: MICROINSTRUCTION CODE FORMAT (20 bits)

45. Symbolic Microinstructions
• Each line of the Assembly Language Microprogram
defines a symbolic microinstruction
• A Symbolic Microprogram can be translated into its
binary equivalent by means of an ASSEMBLER
• Each Symbolic Microinstruction is divided into FIVE
fields:
– Label, Microoperations, CD, BR, AD

46. • LABEL field
– may be empty or it may specify a symbolic address
– A label is terminated with a colon (:)
• Microoperations field
– consists of one or two or three symbols, separated by commas
• CD field
– has one of the letters U, I, S, or Z
• BR field
– contains one of the four symbols (JMP, CALL, RET, MAP)
Example:

47. • AD field specifies a value for the address field of the
microinstruction in one of three possible ways:
a. With a symbolic address, which must also appear as a LABEL (INDRCT)
b. With the symbol NEXT to designate the next address in sequence
c. When the BR field contains a RET or MAP symbol,
-- the AD field is left EMPTY and is converted to seven zeros by the
assembler
• ORG is a PSEUDOINSTRUCTION to define the ORIGIN, or FIRST
ADDRESS (here 64), of a Microprogram Routine (FETCH)
– Ex:- symbol ORG 64 informs the assembler to place the next
microinstruction in control memory at decimal address 64 (binary
address 1000000)
Example:

48. The Fetch Routine
• Control Memory has 128 words, and each word contains 20 bits
• To Microprogram the control memory,
– First 64 words (addresses 0 to 63) are to be occupied by the Routines for
the 16 instructions (EX:- ADD, BRANCH, STORE, EXCHANGE)
– Last 64 words (addresses 64 to 127) may be used for Other purpose (EX:-
FETCH, INDRCT)
• A convenient starting location for the FETCH routine is address 64
• MICROINSTRUCTIONS needed for the FETCH Routine are:

49. • FETCH routine needs THREE MICROINSTRUCTIONS, which are placed in
control memory at addresses 64, 65, and 66
• Using the assembly language conventions, write the SYMBOLIC
MICROPROGRAM for the FETCH routine as follows:
• Translation of the symbolic microprogram to BINARY produces the
following BINARY MICROPROGRAM:
.
(64)
(65)
(66)
(Microinstruction-1)
(Microinstruction-2)
(Microinstruction-3)
(64)
(65)
(66)

50. TABLE: Symbols and Binary Code
for MICROINSTRUCTION fields

51. Symbolic MICROPROGRAM
• Several MICROINSTRUCTIONS in each routine
– for evaluating the effective address
– for executing the instruction
• If the microinstructions for the indirect address are
stored as a subroutine
– it is symbolized by INDRCT
– and is located after fetch routine, (shown in Below Table)
• Below table shows the symbolic microprogram for the
fetch routine and the microinstruction routines that
execute FOUR computer instructions

52. TABLE:
Symbolic Microprogram
(Partial)

53. • Fig (a) depicts COMPUTER INSTRUCTION format
• Fig (b) lists FOUR of the 16 possible Memory-Reference instructions
• each Computer Instruction must be Microprogrammed
Figure: COMPUTER INSTRUCTIONS
(For Reference)

54. MAPPING OF INSTRUCTIONS
ADD Routine
AND Routine
LDA Routine
STA Routine
BUN Routine
0000
0001
0010
0011
0100
OP-codes of Instructions
ADD
AND
LDA
STA
BUN
0000
0001
0010
0011
0100
.
.
.
Direct Mapping
Address
0 0000 00
0 0001 00
0 0010 00
0 0011 00
0 0100 00
Mapping
Bits 0 xxxx 00
ADD Routine
Address
AND Routine
LDA Routine
STA Routine
BUN Routine
Control
Memory
(For Reference)

55. • Assume,
– MAP microinstruction at the end of
the FETCH routine caused a branch
to address ‘0’
– ADD routine is stored in address ‘0’
ADD Routine
• First microinstruction in the ADD
routine CALLS subroutine INDRCT,
conditioned on status bit ‘I’
– If I = 1, a branch to INDRCT occurs
– and RETURN address (address 1 in
this case) is stored in the subroutine
register SBR
– INDRCT subroutine has two
microinstructions:
– Memory has to be accessed (READ)
to get the Effective Address
– then transferred to AR (DRTAR)
– Return from subroutine (RET)
transfers the address from SBR to
CAR
• Thus returning to the Second
microinstruction of the ADD routine

56. • ADD instruction execution is carried out by the
microinstructions at addresses 1 and 2
• First MICROINSTRUCTION
– READS the operand from memory into DR
• Second MICROINSTRUCTION
– performs an ADD MICROOPERATION with the content of DR and
AC and
– then JUMPS back to the beginning of the FETCH routine
(addresses 0)
(addresses 1)
(addresses 2)

57. • BRANCH instruction
– should cause a branch to the
effective address if AC < 0 (sign
is negative)
• BRANCH routine starts by
checking the value of S (status
bit )
• If S=0, NO branch occurs and
– Next microinstruction causes a
JUMP back to the FETCH
routine, WITHOUT altering the
content of PC
• If S = 1,
– First JMP microinstruction
transfers control to location
OVER
– Microinstruction at this
location calls the INDRCT
subroutine If I = 1
– Effective Address is then
transferred from AR to PC and
– microprogram JUMPS back to
the FETCH routine
=0
=1
=1

58. • STORE routine
– again uses the INDRCT
subroutine if I=1
– content of AC is
transferred into DR
– Memory WRITE
operation is initiated to
store the content of DR
in a location specified by
the effective address in
AR
• EXCHANGE routine
– READS the operand from
the Effective Address
and places it in DR
– contents of DR and AC
are interchanged in the
third microinstruction
– original content of AC
that is now in DR is
stored back in memory
=1

59. Binary Microprogram
• Symbolic Microprogram must be translated to Binary either by
means of an Assembler Program or by the user if the
microprogram is simple
• Equivalent binary form of the microprogram is listed in Below Table
• Addresses for control memory are given in both decimal and
binary
• Binary content of each microinstruction is derived from the
symbols and their equivalent binary values
– Address 3 has NO equivalent in the symbolic microprogram since the
ADD routine has only three microinstructions at addresses 0, 1, and 2
– next routine starts at address 4
– Even though address 3 is NOT used, some binary value must be
specified for each word in control memory
– all 0' s in the word are specified, since this location will never be used

60. TABLE: Binary Microprogram for Control Memory (Partial) TABLE: Symbolic Microprogram (Partial)

61. TABLE: Binary Microprogram for Control Memory (Partial)

62. • The Binary microprogram listed in Table specifies
the WORD CONTENT of the Control Memory
• When a ROM is used for the control memory,
– the microprogram binary list provides the truth table
for fabricating the unit
– This fabrication is a HARDWARE PROCESS and consists
of creating a mask for the ROM so as to produce the
1's and 0's for each word
– Bits of ROM are FIXED (internal links are fused
during the hardware production)
• To modify the instruction set of the computer,
– it is necessary to generate a NEW MICROPROGRAM
and mask a NEW ROM

63. • If a WRITABLE control memory is employed,
– the ROM is REPLACED by a RAM
• Advantage of employing a RAM for the control
memory is that
– Microprogram can be altered simply by writing a new
pattern of 1's and 0's without resorting to hardware
procedures
– There is flexibility of choosing the instruction set of a
computer dynamically by changing the microprogram
under processor control
• Most microprogrammed systems use a ROM for
the control memory
– because it is CHEAPER and FASTER than a RAM
– and to PREVENT the occasional user from CHANGING
the ARCHITECTURE of the system

64. Design of Control Unit
• For example,
• when F1 = 101 (DR to AR),
– there is a transfer from the
content of DR(0-10) to AR
• when F1 = 110 (PC to AR),
– there is a transfer from PC
to AR
• Outputs 5 and 6 of
Decoder F1 are connected
to the Load input of AR
• If AR is enabled,
– information from the
MULTIPLEXERS is
transferred to AR
• MUXs select
– information from DR when
output 5 is active
– from PC when output 5 is
inactive
Fig: Decoding of Microoperation fields
Figure shows the Decoding of
Microoperation fields with three
Decoders and some other connections

65. Microprogram Sequencer
• ADDRESS SELECTION PART of Microprogrammed control
unit is called a Microprogram Sequencer
• Purpose of a microprogram sequencer is
– to PRESENT an ADDRESS to the control memory
– so that a microinstruction may be read and executed
• Internal structure of a typical microprogram sequencer for
control unit is illustrated in below Fig.
Figure: Microprogrammed control organization

66. • There are two multiplexers in
the circuit
• Mux1
– selects an address from one of
four sources
– routes it into a control address
register CAR
• MUX2
– tests the value of a selected
status bit
– result of the test is applied to an
input logic circuit
• Output from CAR provides the
address for the control memory
• Content of CAR is incremented
and applied to MUX1 inputs and
to the subroutine register SBR
• Other three inputs to MUX1
come
– from the address field of the
present microinstruction
– from the output of SBR
– from an external source that
MAPS the instruction
3 2 1 0
S1 MUX1
External
(MAP)
SBR
Load
Incrementer
CAR
Input
logic
I0
T
MUX2
Select
1
I
S
Z
Test
Clock
Control memory
Microops CD BR AD
L
I1
S0
. . .
. . .
Fig: Microprogram Sequencer for a control memory

67. • MUX2 selects one of the status
bits from CD (condition) field
of microinstruction
• If the bit selected is equal to 1,
– the T (test) = 1;
– otherwise, T=0
• T value together with the BR
(branch) field go to an input
logic circuit
• Input logic determine the type
of operations
• Typical sequencer operations
are:
– Increment
– branch or jump
– Call and return from
subroutine
– load an external address
– push or pop the stack
3 2 1 0
S1 MUX1
External
(MAP)
SBR
Load
Incrementer
CAR
Input
logic
I0
T
MUX2
Select
1
I
S
Z
Test
Clock
Control memory
Microops CD BR AD
L
I1
S0
. . .
. . .
Fig: Microprogram Sequencer for a control memory