These slides use concepts from my (Jeff Funk) course entitled analyzing hi-tech opportunities to analyze how the economic feasibility of 3D integrated circuits (ICs) is becoming better and this will enable the continuation of Moore’s Law. 3D ICs involve the stacking of transistors and memory cells on top of each other in order to increase the number of transistors per chip area and thus continue Moore’s Law. As opposed to attempting to further reduce the feature sizes, engineers build up. They increase the number of layers of transistors and memory cells just as they have increased the number of layers of metal interconnect. To do this, they connect the different layers of transistors and memory cells with so-called Vias that are fabricated from copper.
IC suppliers began shipping 3D ICs in 2006 and these shipments have gradually grown and expanded from simple structured ICs such as image sensors to power ICs, and more recently memories, microprocessors, and ASICs. It is easier to increase the number of layers on simple than complex structured ICs. The global 3D IC market is expected to grow from $2.21 billion in 2009 to $6.55 billion in 2016 at a compound annual rate of 16.9% from 2011 to 2016.
Although it is hard to compare actual 2D and 3D ICs, simulations allow us to easily do such comparisons. For example, simulations found that chip area is almost 50% less and the metal length is about 28% less for 3D than 2D chips. The shorter metal length means that speeds will be faster since the electrons have less distance to travel. Simulations show that timing delay is 37%, 57% and 65% shorter for 2, 3, and 4-layer 3D ICs, data transfer rates are faster, and operating frequency is about 30% fasters for 3D than 2D ICs. Simulations also show that power consumption is lower for 3D ICs, achieving a 40% reduction with 4-layer 3D ICs as compared to 2D ICs.
Perhaps more importantly, these simulations show that 3D ICs are theoretically cheaper to develop and manufacture. The reason is that 3D ICs can use larger feature sizes than can 2D ICs in order to achieve the same densities of transistors per chip. These larger feature sizes reduce the cost of equipment such as photolithographic equipment, whose costs are rising rapidly. Simulations show that capital costs for 3D ICs are 5% and R&D costs are those of 2D ICs. For manufacturing costs, simulations of flash memory that the advantage of 3D ICs increases as the size of flash memory increases reaching 50% with 256Gb.
All of this suggests that Moore’s Law will continue for many years. Combined with the reductions in feature size that were mentioned earlier from International Technology Roadmap for Semiconductors, there is probably another 10-20 years left in Moore’s Law just from 3D ICs and smaller feature sizes. Nevertheless, challenges remain for 3D ICs. The simulations assume similar yields when in reality it will be harder to achieve similar yields on 3D as 2D ICs given the increa