A CMUT Microphone Fabricated Using a CMOS Process presentation made at MUT 2019 workshop, in Grenoble, France. This work covers the implementation of the design method of high SNR MCM microphone, simulation of the design, Low-noise amplifier design and also the proof-of-concept fabrication and verification.

1. A CMUT Microphone
Fabricated using
a CMOS Process
A. Atalar, H. Koymen, M. Yilmaz*, K. Enhos, I. Koymen, S. Tasdelen
Bilkent University, *Bilkent University UNAM, Ankara TURKEY
18th MUT Workshop, 11-12 June 2019 Grenoble, France 1

2. Micromachined Silicon Microphones
State-of-the-art:
• Very compliant perforated membrane fabricated using silicon
micromachining
• Pressure compensated gap
• Resonance frequency slightly higher than maximum audio frequency
• A separate wire-bonded or integrated low-noise high-input-
impedance amplifier:
• Single-stage low-noise JFET amplifier operating from 3 to 5V supply.
• JFET is preferred because it has a low 1/f noise.
• The noise of the bias resistor is negligible compared to the sensor noise.
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3. Micromachined silicon microphones
• Silicon micromachined sensor is inherently noisy, since the air in the
gap causes mechanical noise.
• A surface-mount metallic package with an acoustic port
• Not water-proof
• ~15V bias voltage
• High sensitivity: −38 dBV/Pa
• SNR>60dB with 1 Pa acoustic signal
• Single cell
• About 1mm2 die size
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4. Micromachined silicon microphones
Top view Bottom view Packaged microphone
A. Dehé, M. Wurzer, M. Füldner and U. Krumbein, “The Infineon Silicon MEMS Microphone“, Sensor 2013
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5. CMUT as a microphone
• A vacuum gap CMUT is basically a lossless sensor → inherently very
low noise microphone
• Water-proof
• The sensitivity is lower because of lower compliance of the CMUT
plate.
• SNR will be determined by the noise generated in the amplifier
connected to the CMUT
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6. Three independent input variables:
• VDC: Bias voltage
• Fb/Fg<1: The ratio of ambient pressure to the pressure necessary to
touch the center of the plate to bottom
• VDC/VC<1:The ratio of bias voltage to the collapse voltage under
ambient pressure
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7. Analytic procedure to find the dimensions
• Determine the ratio of collapse voltage under pressure to that under
vacuum, VC/Vr, from
VC/Vr =0.9961-1.0468* Fb/Fg +0.06972 *(Fb/Fg -0.25)2+0.01148 *(Fb/Fg )6
Find Vr (collapse voltage in vacuum)
• Determine relative depression of CMUT plate, XP/tge, from the solution of
3(x- Fb/Fg )/{[(1/(1-x)-tanh-1(x½)/x½]/x – (VDC/Vr)2}=0
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8. Procedure to find the dimensions *
Determine the minimum dimensions of CMUT
tmmin=15/2 (ε0/P0)½ (XP/tge)(Fb/Fg)½ Vr
amin=15 (Y0/(15(1-σ2)P0)¼ (ε0/P0)½ (XP/tge)¾(Fb/Fg)¾ Vr
tge=3/2 (ε0/P0)½ (Fb/Fg)½ Vr
CMUT can be scaled with a scale factor K, without changing the open-circuit
voltage sensitivity
a= K3 amin
tm =K4 tmmin
* US Patent 10284963: “High performance sealed-gap capacitive microphone”
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9. Why is there a lower limit on size?
Because of elastic nonlinearity limit:
• To stay in the linear region, the center displacement of a circular plate
should be less than 1/5 of the plate thickness.
• Independent of the radius of the plate!
E. Ventsel and T. Krauthammer, Thin Plates and Shells, 1st ed., New
York, NY: Marcel Dekker, 2001.
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10. Open-circuit voltage sensitivity of the CMUT
microphone below the resonance
VOC/P= 2.01 (VDC/P0) (FB/FG) g’ / [(VDC/Vr g’)2+g(¾ − ½(VDC/Vr)2 g’’)]
with
g= tanh-1(u½)/u½
g’=(1/(1−u)−g)/2u
g’’=(1/(1−u)2−3g’)/2u
and u=XP/tge
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11. Experimental verification
• Fb/Fg=0.49
• VDC/VC=0.34
• VDC=72V
• Calculated CMUT radius= 520μm
• Calculated CMUT plate thickness = 16μm
• Calculated CMUT gap = 4.4μm
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12. Experimental verification
• Sensitivity formulas are verified using a single cell CMUTs manufactured
using wafer bonding technique and measured using low-noise electronics
Plate (Si) radius: 545μm
Plate (Si) thickness: 16μm (15μ Si + 1μ SiO2)
Gap: 4.4μm
VDC= 72V
Capacitance = 2.4pF
Predicted sensitivity: −64.9 dB re V/Pa
Predicted sensitivity after amplifier input cap
voltage drop: −69.2 dB re V/Pa
Measured sensitivity: −69 dB re V/Pa
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13. Min. CMUT plate thickness for 15V bias voltage
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14. Min. CMUT plate thickness for 20V bias voltage
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15. Min. CMUT plate radius for 15V bias voltage
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16. Min. CMUT plate radius for 20V bias voltage
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17. Dimensions of CMUT microphone
• Dimensions are larger than typical CMUTs
• Thicknesses for the range FB/FG=0.7 to 0.8 are compatible with 0.6μm
or 0.35μm CMOS processes
• Gap increases linearly with increasing bias voltage, VDC.
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18. CMUT effective gap height for 15V bias voltage
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19. CMUT effective gap height for 20V bias voltage
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20. CMUT open-circuit voltage for 15V bias (1 Pa)
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21. CMUT open-circuit voltage for 20V bias
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22. Open-circuit voltage sensitivity
Depends on
• Fb/Fg strongly (Fb/Fg from 0.6 to 0.8 → sensitivity increases by 7.6dB)
• Signal strength varies with ambient pressure: Slightly lower signal at higher
altitudes
• VDC moderately (VDC from 15 to 20 → sensitivity increases by 2.5dB)
• VDC/VC weakly (from 0.6 to 0.8 → sensitivity increases by 1.5dB)
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23. Fitting the largest number of
CMUT cells in a given area
• Choose K>1 to increase the radius of CMUT cells to fit the cells snugly
in the given area
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24. Number of CMUT cells within a 1.1 x 1.1 mm
with 15V bias voltage
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25. CMUT capacitance with bias voltage of 15V
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26. CMUT capacitance with bias voltage of 20V
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27. CMUT capacitance/area versus bias voltage
CMUT capacitance/area
• Decreases as the bias voltage is increased
• Decreases as Fb/Fg increases
• Increases as VDC/VC increases
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28. Low-noise CMOS amplifier
• Single stage nMOS amplifier with a resistive load (25dB gain)
• 1/f noise is inversely proportional to WL product (total gate area)
• Increasing the gate area reduces the 1/f noise
• Input capacitance of the amplifier is also proportional to WL product
• Increasing the input capacitance reduces the signal because of
capacitive divider.
• There is an optimum value of transistor size.
• Current noise must be minimized using a very large bias resistor
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29. Low-noise amplifier
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30. Integrated A-weighted
amplifier input noise (20-20KHz)
Amplifier input
capacitance= 77pF
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31. SNR for 1 Pa acoustic signal and 15V bias
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32. SNR for 1 Pa acoustic signal and 20V bias
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33. SNR optimization
SNR of the microphone can be increased if
• The ambient pressure is allowed to depress the CMUT plate
significantly → Choose a Fb/Fg as large as possible
• Choose VDC/VC as large as possible (operate close to collapse)
• Choose a convenient bias voltage (~15V)
• Use multiple cells to increase the capacitance
• K scaling factor should be used to size the CMUT cells to fit in the
given area snugly
• Optimize W/L ratio of the amplifier
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34. SNR improvement
• VDC/VC from 0.6 to 0.8 → 4.0dB improvement
• Fb/Fg from 0.6 to 0.8 → 3.5dB improvement
• VDC from 15V to 20V → 0.75dB improvement
• It is possible to obtain SNR>60dB
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35. Selection of CMOS foundry
suitable for CMUT microphone
• Etch holes are defined as PADs, to remove the passivation oxide
• Small PADs should be allowable in design rules
• VIA is the cut in the oxide between two metal layers
• Large VIA’s at the same size as the etch holes should be allowable
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36. CMUT microphone cells in CMOS
• Needs to be in octagon shape, since the design rules do not allow a
circular shape. 45° shapes are allowed.
• Radius of the circle is converted into an equivalent apothem of the
octagon.
• Four etch holes for every CMUT cell.
• Etch holes are shared with neighboring CMUT cells.
• Proper metal/oxide layers are combined to give the desired plate
thickness.
• A thin polysilicon layer can be used as sacrificial layer.
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37. A single CMUT microphone cell top view
Defined as PADs.
MCM plate
Etch holes
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38. CMUT electrodes
• Silicon substrate as the bottom electrode
• With a positive bias voltage, we need p+ region as the electrode
• Metals with passivation oxide on top as the top electrode
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39. CMOS fabrication
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40. CMOS after fabrication
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41. Post-processing
• XeF2 as dry polysilicon etchant
Can handle large aspect ratio needed to generate the gap.
About 5μm/min etch rate †
1000:1 selectivity for oxide
• Conformal parylene C coating to be used for sealing the etch holes.
† Xactix Inc., Pittsburgh Pennsylvania
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42. After metal etching
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43. After dry polysilicon etching (XeF2)
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44. After sealing (parylene C)
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45. 25 CMUT cells with amplifier and bonding
pads
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46. Advantages of the new CMUT microphone
• Can be made smaller than 1mm2 at the expense of SNR
• Halving the total microphone size reduces SNR 4.2dB
• Very small microphones possible
• Can be made larger than 1mm2 to increase the SNR further:
• Doubling the size improves SNR about 4.2dB.
• Water-proof, potentially low-cost
• EMI shielding in CMOS chip
• Easily integrated into CMOS chips with electronics (amplifier and
charge pump)
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47. Conclusions
• CMUT can be used as a water-proof microphone
• Optimal dimensions can be found analytically
• Very low noise sensor
• With a high W/L ratio CMOS amplifier, it is possible to obtain 60dB
SNR
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48. Future work
• Prototype CMUT microphones to be delivered in July as part of
multiproject wafer run
• Post processing of received chips
• Verification of predicted SNR values.
• Integration of charge pump to generate 15V bias source in the next
multiproject wafer run
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