This document contains the contents page and programs for various microprocessor lab experiments using the 8085 microprocessor. It includes 23 programs covering topics like data transfer, arithmetic operations, sorting, string operations and interfacing programs. The programs are written in 8085 assembly language and include code segments, data segments and explanations.
The 8086 instruction set includes 8 categories of instructions: data transfer, arithmetic, branch, loop, machine control, flag manipulation, shift/rotate, and string instructions. Some key instructions include MOV for data transfer, PUSH/POP for stack operations, ADD/SUB for arithmetic, JMP for branching, LOOP for looping, and SHIFT/ROTATE for bitwise operations.
Programming with 8085-Microprocessor and interfacingAmitabh Shukla
Here are the key steps to separate the digits of a hexadecimal number and store them in two locations:
1. Load the packed BCD number into the accumulator register using LDA instruction
2. Mask the lower nibble using ANI instruction with F0H to isolate the lower digit
3. Rotate the accumulator right through carry three times using RRC instruction to shift the higher digit into the lower position
4. Store the lower and higher digits into two separate memory locations
This separates the digits of the hexadecimal number by isolating and adjusting the position of each digit, allowing them to be stored independently.
The document is a lab manual for a Microprocessor and Microcontroller lab. It contains:
1. An introduction and syllabus covering digital and linear circuits, 8-bit microprocessors and microcontrollers, and various experiments.
2. Details of experiments with an 8-bit microprocessor (8085) including arithmetic operations, sorting/searching arrays, code conversions, and interfacing analog devices.
3. Details of experiments with an 8-bit microcontroller (8051) including programming basics and interfacing devices like stepper motors.
4. Objectives, apparatus, algorithms, programs, procedures, inputs/outputs for each experiment.
The document provides an overview of the Motorola DSP563xx family of processors. It describes the core architecture which includes a data ALU, MAC unit, address generation unit, program control unit, and on-chip memory. It also discusses the internal buses and on-chip peripherals. The DSP563xx family is used in applications such as wireless infrastructure and modem banks. Members of the family have different memory and peripheral configurations while sharing a standardized DSP56300 core.
The document discusses the different addressing modes of the 8086 processor. It explains that addressing modes refer to the different ways a processor can access data. It then describes the 8 addressing modes of the 8086 - immediate, direct, register, register indirect, indexed, register relative, based indexed, and relative based indexed. For each mode, it provides an example of how the MOV instruction is used with that addressing mode and how the physical address is calculated.
The 8086 instruction set includes 8 categories of instructions: data transfer, arithmetic, branch, loop, machine control, flag manipulation, shift/rotate, and string instructions. Some key instructions include MOV for data transfer, PUSH/POP for stack operations, ADD/SUB for arithmetic, JMP for branching, LOOP for looping, and SHIFT/ROTATE for bitwise operations.
Programming with 8085-Microprocessor and interfacingAmitabh Shukla
Here are the key steps to separate the digits of a hexadecimal number and store them in two locations:
1. Load the packed BCD number into the accumulator register using LDA instruction
2. Mask the lower nibble using ANI instruction with F0H to isolate the lower digit
3. Rotate the accumulator right through carry three times using RRC instruction to shift the higher digit into the lower position
4. Store the lower and higher digits into two separate memory locations
This separates the digits of the hexadecimal number by isolating and adjusting the position of each digit, allowing them to be stored independently.
The document is a lab manual for a Microprocessor and Microcontroller lab. It contains:
1. An introduction and syllabus covering digital and linear circuits, 8-bit microprocessors and microcontrollers, and various experiments.
2. Details of experiments with an 8-bit microprocessor (8085) including arithmetic operations, sorting/searching arrays, code conversions, and interfacing analog devices.
3. Details of experiments with an 8-bit microcontroller (8051) including programming basics and interfacing devices like stepper motors.
4. Objectives, apparatus, algorithms, programs, procedures, inputs/outputs for each experiment.
The document provides an overview of the Motorola DSP563xx family of processors. It describes the core architecture which includes a data ALU, MAC unit, address generation unit, program control unit, and on-chip memory. It also discusses the internal buses and on-chip peripherals. The DSP563xx family is used in applications such as wireless infrastructure and modem banks. Members of the family have different memory and peripheral configurations while sharing a standardized DSP56300 core.
The document discusses the different addressing modes of the 8086 processor. It explains that addressing modes refer to the different ways a processor can access data. It then describes the 8 addressing modes of the 8086 - immediate, direct, register, register indirect, indexed, register relative, based indexed, and relative based indexed. For each mode, it provides an example of how the MOV instruction is used with that addressing mode and how the physical address is calculated.
This document discusses various addressing modes of the 8086 microprocessor. It defines addressing modes as how operands are specified in an instruction. There are 8 main addressing modes - immediate, direct, register, register indirect, indexed, register relative, based indexed, and relative based indexed. Each mode is explained with examples of how operand values are accessed from memory or registers to perform operations. The document also discusses intrasegment and intersegment addressing modes which specify if the source and destination locations are within the same memory segment or different segments.
The document discusses assembly language programming concepts including the stack segment, stack, stack instructions, subroutines, macros, and recursive procedures. It provides examples and explanations of these concepts. It also includes sample programs and solutions related to stacks, subroutines, and other assembly language topics.
The stack is a group of memory locations used for temporary storage of data during program execution. Data is stored onto the stack in reverse order using PUSH instructions and retrieved using POP instructions. The stack pointer register (SP) points to the top of the stack. Subroutines use the stack to store the return address by pushing it onto the stack with a CALL instruction and popping it back into the program counter with a RET instruction. Conditional and restart CALL instructions transfer program flow based on flag settings or to fixed memory locations.
The document contains 10 programs written in 8085 assembly language. Program 1 exchanges two 16-bit numbers. Program 2 adds or subtracts two 8-bit numbers. Program 3 adds two 16-bit numbers. Program 4 subtracts two 16-bit numbers where X is greater than Y. Program 5 adds two variable length numbers. Program 6 performs a block transfer. Program 7 performs a block transfer in reverse order. Program 8 adds 10 decimal numbers. Program 9 displays hexadecimal numbers from 00 to FF. Program 10 performs four-digit BCD addition.
Interfacing of 8051 with 8255 Programmable Peripheral Interface.pdfSrikrishna Thota
The document discusses interfacing the 8051 microcontroller with the 8255 Programmable Peripheral Interface (PPI). It explains that the 8051 has limited I/O ports, so the 8255 is used to provide additional ports (Port A, B, C). It describes the components needed, including the 8051, 8255, decoder and logic gates. It provides the address mapping for the 8255 ports and the control logic design. An algorithm and assembly code example is given to read inputs from 8255 Port A and B, add the values, and output the result to Port C.
The document contains programs to perform addition, subtraction, multiplication, and division of two 8-bit numbers using the 8085 microprocessor. It also contains a program to find the largest number in an array. For each program, it provides the aim, algorithm, program code, input/output observations, and confirms that the program was successfully executed.
The document contains programs to perform various operations on 8-bit numbers like addition, subtraction, multiplication, division using 8085 microprocessor. It also contains programs to find the largest/smallest number in an array, and to arrange an array of numbers in ascending order. The programs demonstrate various instructions of 8085 like load, move, add, subtract, compare, jump etc to perform the given tasks.
This document contains the contents and program descriptions for various programs to be completed as part of a Microprocessor Lab course. There are 23 interfacing programs and 20 8085 microprocessor programs described, including programs to transfer data blocks with and without overlap, add/multiply/divide numbers, implement counters, check codes, and interface with keyboards, displays, and other peripherals.
1. The 8254 contains three independent 16-bit counters/timers that can be programmed to operate in different modes.
2. Each counter can be programmed to count from 1 to 65535 and has a programmable control word to select the operating mode.
3. The 8254 supports various timer modes like one-shot, continuous square wave, event counter, and software/hardware triggered one-shot for applications like timing, delay generation, and pulse width modulation.
The document discusses interrupts in the 8085 microprocessor. It defines interrupts as a mechanism to suspend normal execution and service external devices or instructions. The 8085 has hardware and software interrupts. Hardware interrupts can be maskable or non-maskable. Maskable interrupts like RST 7.5, 6.5, 5.5 and INTR can be enabled and disabled, while the non-maskable TRAP interrupt cannot. Software interrupts use RST instructions to redirect execution to subroutines.
The 80386 microprocessor provides 11 addressing modes, including register, immediate, direct, register indirect, based, index, scaled index, based index, based scaled index, based index with displacement, and based scaled index with displacement addressing modes. These addressing modes indicate how the source and destination addresses for instructions are accessed and located in memory or registers. The addressing modes allow data to be accessed using registers, immediate values, memory addresses formed from registers and offsets.
This document provides an overview of the instruction set of the 8085 microprocessor. It begins by defining what an instruction is and the classification of the 8085 instruction set. It then proceeds to describe various data transfer, arithmetic, logical, branching, and control instructions in detail through opcode, operands, examples, and before/after execution illustrations. The document aims to provide a comprehensive reference for the complete set of 246 instructions supported by the 8085 microprocessor.
This document describes the design and implementation of a 32-bit floating point adder according to the IEEE 754 standard using VHDL. It includes block diagrams of the main components: a pre-adder block to prepare the operands, an adder block to perform the addition or subtraction, and a standardization block to normalize the result. It also provides details on the steps involved, including extracting the sign, exponent and mantissa of the operands, handling special cases like zero, infinity and NaN, aligning the exponents, performing the addition or subtraction, normalizing and rounding the result, and adjusting the exponent.
The document discusses stack and subroutines in assembly language programs. It explains that stack is used to store return addresses and save register contents. Subroutines allow breaking programs into modules and use CALL and RET instructions. An example program adds two numbers stored in memory locations and returns the result.
The flag register in the 8086 CPU contains 16 bits with each bit corresponding to a flip-flop that indicates the status of instructions. There are 9 active flags that serve different purposes - 6 are status flags reflecting results and 3 are control flags that enable/disable operations. The status flags indicate things like carry, parity, zero, sign, overflow while the control flags control tracing mode, interrupts, and direction of string operations.
This document discusses arithmetic operations and conversions using the 8085 microprocessor. It includes algorithms and programs for 8-bit addition, subtraction, multiplication, and division. It also covers sorting algorithms to find the ascending and descending order of numbers, and algorithms to find the minimum and maximum numbers in a data set. Additionally, it explains programs that demonstrate the rotate instructions RLC, RRC, RAL, and RAR. Finally, it provides examples of conversions between ASCII, hexadecimal, and BCD codes.
The document contains a list of 23 microprocessor lab programs and 6 interfacing programs for an electronics and communication course. The programs cover topics like data transfer, arithmetic operations, sorting, prime number generation, string operations, matrix multiplication and more. The document provides contents, program descriptions and assembly language code for some of the programs.
The document contains a list of 23 microprocessor lab programs and 6 interfacing programs for an electronics and communication course. The programs cover topics like data transfer, arithmetic operations, sorting, string operations, matrix multiplication and more. The document provides brief descriptions of each program to be implemented on the 8085 microprocessor as part of the lab curriculum.
This document discusses various addressing modes of the 8086 microprocessor. It defines addressing modes as how operands are specified in an instruction. There are 8 main addressing modes - immediate, direct, register, register indirect, indexed, register relative, based indexed, and relative based indexed. Each mode is explained with examples of how operand values are accessed from memory or registers to perform operations. The document also discusses intrasegment and intersegment addressing modes which specify if the source and destination locations are within the same memory segment or different segments.
The document discusses assembly language programming concepts including the stack segment, stack, stack instructions, subroutines, macros, and recursive procedures. It provides examples and explanations of these concepts. It also includes sample programs and solutions related to stacks, subroutines, and other assembly language topics.
The stack is a group of memory locations used for temporary storage of data during program execution. Data is stored onto the stack in reverse order using PUSH instructions and retrieved using POP instructions. The stack pointer register (SP) points to the top of the stack. Subroutines use the stack to store the return address by pushing it onto the stack with a CALL instruction and popping it back into the program counter with a RET instruction. Conditional and restart CALL instructions transfer program flow based on flag settings or to fixed memory locations.
The document contains 10 programs written in 8085 assembly language. Program 1 exchanges two 16-bit numbers. Program 2 adds or subtracts two 8-bit numbers. Program 3 adds two 16-bit numbers. Program 4 subtracts two 16-bit numbers where X is greater than Y. Program 5 adds two variable length numbers. Program 6 performs a block transfer. Program 7 performs a block transfer in reverse order. Program 8 adds 10 decimal numbers. Program 9 displays hexadecimal numbers from 00 to FF. Program 10 performs four-digit BCD addition.
Interfacing of 8051 with 8255 Programmable Peripheral Interface.pdfSrikrishna Thota
The document discusses interfacing the 8051 microcontroller with the 8255 Programmable Peripheral Interface (PPI). It explains that the 8051 has limited I/O ports, so the 8255 is used to provide additional ports (Port A, B, C). It describes the components needed, including the 8051, 8255, decoder and logic gates. It provides the address mapping for the 8255 ports and the control logic design. An algorithm and assembly code example is given to read inputs from 8255 Port A and B, add the values, and output the result to Port C.
The document contains programs to perform addition, subtraction, multiplication, and division of two 8-bit numbers using the 8085 microprocessor. It also contains a program to find the largest number in an array. For each program, it provides the aim, algorithm, program code, input/output observations, and confirms that the program was successfully executed.
The document contains programs to perform various operations on 8-bit numbers like addition, subtraction, multiplication, division using 8085 microprocessor. It also contains programs to find the largest/smallest number in an array, and to arrange an array of numbers in ascending order. The programs demonstrate various instructions of 8085 like load, move, add, subtract, compare, jump etc to perform the given tasks.
This document contains the contents and program descriptions for various programs to be completed as part of a Microprocessor Lab course. There are 23 interfacing programs and 20 8085 microprocessor programs described, including programs to transfer data blocks with and without overlap, add/multiply/divide numbers, implement counters, check codes, and interface with keyboards, displays, and other peripherals.
1. The 8254 contains three independent 16-bit counters/timers that can be programmed to operate in different modes.
2. Each counter can be programmed to count from 1 to 65535 and has a programmable control word to select the operating mode.
3. The 8254 supports various timer modes like one-shot, continuous square wave, event counter, and software/hardware triggered one-shot for applications like timing, delay generation, and pulse width modulation.
The document discusses interrupts in the 8085 microprocessor. It defines interrupts as a mechanism to suspend normal execution and service external devices or instructions. The 8085 has hardware and software interrupts. Hardware interrupts can be maskable or non-maskable. Maskable interrupts like RST 7.5, 6.5, 5.5 and INTR can be enabled and disabled, while the non-maskable TRAP interrupt cannot. Software interrupts use RST instructions to redirect execution to subroutines.
The 80386 microprocessor provides 11 addressing modes, including register, immediate, direct, register indirect, based, index, scaled index, based index, based scaled index, based index with displacement, and based scaled index with displacement addressing modes. These addressing modes indicate how the source and destination addresses for instructions are accessed and located in memory or registers. The addressing modes allow data to be accessed using registers, immediate values, memory addresses formed from registers and offsets.
This document provides an overview of the instruction set of the 8085 microprocessor. It begins by defining what an instruction is and the classification of the 8085 instruction set. It then proceeds to describe various data transfer, arithmetic, logical, branching, and control instructions in detail through opcode, operands, examples, and before/after execution illustrations. The document aims to provide a comprehensive reference for the complete set of 246 instructions supported by the 8085 microprocessor.
This document describes the design and implementation of a 32-bit floating point adder according to the IEEE 754 standard using VHDL. It includes block diagrams of the main components: a pre-adder block to prepare the operands, an adder block to perform the addition or subtraction, and a standardization block to normalize the result. It also provides details on the steps involved, including extracting the sign, exponent and mantissa of the operands, handling special cases like zero, infinity and NaN, aligning the exponents, performing the addition or subtraction, normalizing and rounding the result, and adjusting the exponent.
The document discusses stack and subroutines in assembly language programs. It explains that stack is used to store return addresses and save register contents. Subroutines allow breaking programs into modules and use CALL and RET instructions. An example program adds two numbers stored in memory locations and returns the result.
The flag register in the 8086 CPU contains 16 bits with each bit corresponding to a flip-flop that indicates the status of instructions. There are 9 active flags that serve different purposes - 6 are status flags reflecting results and 3 are control flags that enable/disable operations. The status flags indicate things like carry, parity, zero, sign, overflow while the control flags control tracing mode, interrupts, and direction of string operations.
This document discusses arithmetic operations and conversions using the 8085 microprocessor. It includes algorithms and programs for 8-bit addition, subtraction, multiplication, and division. It also covers sorting algorithms to find the ascending and descending order of numbers, and algorithms to find the minimum and maximum numbers in a data set. Additionally, it explains programs that demonstrate the rotate instructions RLC, RRC, RAL, and RAR. Finally, it provides examples of conversions between ASCII, hexadecimal, and BCD codes.
The document contains a list of 23 microprocessor lab programs and 6 interfacing programs for an electronics and communication course. The programs cover topics like data transfer, arithmetic operations, sorting, prime number generation, string operations, matrix multiplication and more. The document provides contents, program descriptions and assembly language code for some of the programs.
The document contains a list of 23 microprocessor lab programs and 6 interfacing programs for an electronics and communication course. The programs cover topics like data transfer, arithmetic operations, sorting, string operations, matrix multiplication and more. The document provides brief descriptions of each program to be implemented on the 8085 microprocessor as part of the lab curriculum.
This document discusses many-core processor chip architectures. It describes two commercial many-core chips, the Intel Single Chip Cloud Computer with 48 cores and the Tilera Tile-Gx100 with 100 cores. It then discusses the challenges of constructing a theoretical many-core chip with thousands of cores due to issues with off-chip memory bandwidth and on-chip communication. Potential architectures are proposed using a 2D mesh network with compute tiles and routers to allow scalability. Simulation results show the network is efficient with high throughput even at large scales.
Implementing 3D SPHARM Surfaces Registration on Cell B.E. ProcessorPTIHPA
This document describes implementing 3D SPHARM surface registration on a Cell processor. It discusses SPHARM expansion and registration, calculating rotation coefficients, root mean square distance, and implementations in Matlab and on the Cell processor. The Cell implementation uses loop fusion, lookup tables, and optimizations for the Cell architecture like vectorization and data alignment. Performance analysis shows a dramatic increase in speed on the Cell due to its architecture and algorithm optimizations. Care is needed for data placement and transfer due to limited local store.
The document describes the instruction set of the 8086 microprocessor. It discusses the different types of instructions including data transfer instructions like MOV, PUSH, POP, XCHG, IN, OUT, and XLAT. It also covers addressing modes, instruction formats, and the various registers used by the 8086 microprocessor like the stack pointer and flag register. In total there are 14 different data transfer instructions described that are used to move data between registers, memory, ports, and the flag and stack pointers.
The document discusses techniques that JavaScript engines use to optimize performance, including:
- Just-in-time compilation to generate optimized native machine code from JavaScript bytecode. This includes tracing optimizations and register allocation.
- Inline caching to speed up property lookups by caching the results of previous lookups.
- Type inference to determine types statically to avoid slow dynamic checks.
- Built-in optimizations in engines like V8 such as hidden classes, precise garbage collection, and Crankshaft, its optimizing compiler.
BCH codes, part of the cyclic codes, are very powerful error correcting codes widely used in the information coding techniques. This presentation explains these codes with an example.
The document discusses the 8086 microprocessor and assembly language programming. It covers the 8086 block diagram and registers, memory models, instruction set, addressing modes, procedures, example programs, peripheral devices, and assembly code examples. It provides details on data types, arithmetic and logic instructions, comparisons and jumps, macros, procedures, interrupts, and interfacing assembly with high-level languages. The document is intended as reference material for learning 8086 assembly programming.
The document describes a many-core processor chip architecture with multiple compute nodes arranged in a two-dimensional grid connected by an on-chip network. Each compute node contains a processor core and local memory. The nodes communicate through the on-chip network using point-to-point message passing. The document discusses challenges in programming such a massively parallel many-core architecture due to the distributed on-chip memory and need for explicit data transfers between nodes.
The document describes several assembly language programs written for the 8086 microprocessor:
1. Programs for 16-bit addition, subtraction, multiplication, and division by initializing values in registers and memory locations and performing operations.
2. Programs for sorting arrays in ascending and descending order by comparing elements and exchanging values.
3. Programs for string copy and reverse by initializing source and destination addresses and moving elements.
4. A program for searching an array by loading elements, comparing to a value, and displaying results.
5. Programs for file manipulation and interfacing with a stepper motor and keyboard/display.
This PPT will help to understand about the following:
1. what is DSC ?
2. what is mp ?
3. Difference between mp and DSC ?
4. Various generation of TMS320 ?
5. Application of TMS320F2000 FAMILY
The document discusses low density parity check (LDPC) codes. It begins with a brief history of LDPC codes, invented by Gallager in 1960 but rediscovered in the 1990s. It then discusses linear block codes and how they can be represented by generator and parity check matrices. The key properties of LDPC codes are described, including their sparse parity check matrix and regular or irregular structure. Decoding of LDPC codes using tanner graphs and hard decision bit flipping algorithms is explained. Finally, some applications of LDPC codes in communication systems and data storage are provided.
The document discusses designing FIR filters using windowing techniques. It describes using a rectangular window to design a high pass FIR filter. The key steps are: 1) Obtaining the Fourier coefficients of the desired frequency response, 2) Multiplying the coefficients by a window function to reduce oscillations, 3) The windowed coefficients give the impulse response of the FIR filter. Designing a filter using a rectangular window results in significant sidelobes in the frequency response. The document then discusses using a Kaiser window to design a low pass FIR filter and analyzing the effect of different beta values on the filter characteristics.
This document discusses channel coding and linear block codes. Channel coding adds redundant bits to input data to allow error detection and correction at the receiver. Linear block codes divide the data into blocks, encode each block into a larger codeword, and use a generator matrix to map message blocks to unique codewords. The codewords can be detected and sometimes corrected using a parity check matrix. Hamming codes are a type of linear block code that can correct single bit errors. The document provides examples of encoding data using generator matrices and decoding using syndrome values and parity check matrices. It also discusses how the minimum distance of a code determines its error detection and correction capabilities.
The document discusses using static analysis techniques like pointer analysis to detect bugs involving stale pointers. It presents an approach that first converts programs to SSA form and then performs intraprocedural and interprocedural pointer analysis to track pointer aliases and detect when pointers may be used after the memory they point to has been freed or reallocated. The analysis combines dataflow and abstract interpretation to build and propagate pointer alias information within and across functions to find potential stale pointer bugs.
Evgeniy Muralev, Mark Vince, Working with the compiler, not against itSergey Platonov
The talk will look at limitations of compilers when creating fast code and how to make more effective use of both the underlying micro-architecture of modern CPU's and how algorithmic optimizations may have surprising effects on the generated code. We shall discuss several specific CPU architecture features and their pros and cons in relation to creating fast C++ code. We then expand with several algorithmic techniques, not usually well-documented, for making faster, compiler friendly, C++.
Note that we shall not discuss caching and related issues here as they are well documented elsewhere.
D I G I T A L C O M M U N I C A T I O N S J N T U M O D E L P A P E R{Wwwguest3f9c6b
This document contains questions from a digital communications exam for a B.Tech course. The questions cover topics like PCM systems, delta modulation, digital modulation techniques, error probability analysis, information theory concepts, channel capacity, block codes and conventional codes. There are 8 questions in total with sub-questions on analyzing and comparing communication systems and coding schemes.
Digital Communications Jntu Model Paper{Www.Studentyogi.Com}guest3f9c6b
This document contains exam questions for the subject Digital Communications. It has 8 questions divided into 3 sets. The questions cover various topics in digital communications including PCM, delta modulation, digital modulation techniques, bandwidth calculations, error probability analysis, channel capacity, linear block codes and conventional codes. Students are required to answer any 5 questions out of the 8 questions.
The document contains programs demonstrating string and numeric conversion routines in 8086 assembly language. It includes examples of (1) block transfer of strings from one memory location to another, (2) insertion of a string into another string at a specified location, (3) deletion of a substring from a string, and (4) conversions between BCD, hexadecimal, and ASCII numeric representations. The programs utilize common string and arithmetic operations like MOVSB, LODSB, STOSB, DIV, MUL, AND, SHR to manipulate strings and perform conversions.
Whats up at the virtualization/emulation front?chhorn
The document discusses the history and development of virtualization and emulation technologies, starting from mainframe virtualization in the 1960s with IBM System/360, and progressing through early virtualization software like Bochs and VMware, as well as hypervisor-based virtualization with Qemu, Xen, VirtualBox, and KVM. It outlines the key technologies and chronological development of virtualization from single tasks on hardware to operating systems running multiple tasks to modern hypervisor-based virtualization running multiple guest operating systems. The document provides a high-level overview of virtualization history in order to explain the technology at a basic level and simplify complex topics.
zkStudyClub - LatticeFold: A Lattice-based Folding Scheme and its Application...Alex Pruden
Folding is a recent technique for building efficient recursive SNARKs. Several elegant folding protocols have been proposed, such as Nova, Supernova, Hypernova, Protostar, and others. However, all of them rely on an additively homomorphic commitment scheme based on discrete log, and are therefore not post-quantum secure. In this work we present LatticeFold, the first lattice-based folding protocol based on the Module SIS problem. This folding protocol naturally leads to an efficient recursive lattice-based SNARK and an efficient PCD scheme. LatticeFold supports folding low-degree relations, such as R1CS, as well as high-degree relations, such as CCS. The key challenge is to construct a secure folding protocol that works with the Ajtai commitment scheme. The difficulty, is ensuring that extracted witnesses are low norm through many rounds of folding. We present a novel technique using the sumcheck protocol to ensure that extracted witnesses are always low norm no matter how many rounds of folding are used. Our evaluation of the final proof system suggests that it is as performant as Hypernova, while providing post-quantum security.
Paper Link: https://eprint.iacr.org/2024/257
[OReilly Superstream] Occupy the Space: A grassroots guide to engineering (an...Jason Yip
The typical problem in product engineering is not bad strategy, so much as “no strategy”. This leads to confusion, lack of motivation, and incoherent action. The next time you look for a strategy and find an empty space, instead of waiting for it to be filled, I will show you how to fill it in yourself. If you’re wrong, it forces a correction. If you’re right, it helps create focus. I’ll share how I’ve approached this in the past, both what works and lessons for what didn’t work so well.
From Natural Language to Structured Solr Queries using LLMsSease
This talk draws on experimentation to enable AI applications with Solr. One important use case is to use AI for better accessibility and discoverability of the data: while User eXperience techniques, lexical search improvements, and data harmonization can take organizations to a good level of accessibility, a structural (or “cognitive” gap) remains between the data user needs and the data producer constraints.
That is where AI – and most importantly, Natural Language Processing and Large Language Model techniques – could make a difference. This natural language, conversational engine could facilitate access and usage of the data leveraging the semantics of any data source.
The objective of the presentation is to propose a technical approach and a way forward to achieve this goal.
The key concept is to enable users to express their search queries in natural language, which the LLM then enriches, interprets, and translates into structured queries based on the Solr index’s metadata.
This approach leverages the LLM’s ability to understand the nuances of natural language and the structure of documents within Apache Solr.
The LLM acts as an intermediary agent, offering a transparent experience to users automatically and potentially uncovering relevant documents that conventional search methods might overlook. The presentation will include the results of this experimental work, lessons learned, best practices, and the scope of future work that should improve the approach and make it production-ready.
Connector Corner: Seamlessly power UiPath Apps, GenAI with prebuilt connectorsDianaGray10
Join us to learn how UiPath Apps can directly and easily interact with prebuilt connectors via Integration Service--including Salesforce, ServiceNow, Open GenAI, and more.
The best part is you can achieve this without building a custom workflow! Say goodbye to the hassle of using separate automations to call APIs. By seamlessly integrating within App Studio, you can now easily streamline your workflow, while gaining direct access to our Connector Catalog of popular applications.
We’ll discuss and demo the benefits of UiPath Apps and connectors including:
Creating a compelling user experience for any software, without the limitations of APIs.
Accelerating the app creation process, saving time and effort
Enjoying high-performance CRUD (create, read, update, delete) operations, for
seamless data management.
Speakers:
Russell Alfeche, Technology Leader, RPA at qBotic and UiPath MVP
Charlie Greenberg, host
"Choosing proper type of scaling", Olena SyrotaFwdays
Imagine an IoT processing system that is already quite mature and production-ready and for which client coverage is growing and scaling and performance aspects are life and death questions. The system has Redis, MongoDB, and stream processing based on ksqldb. In this talk, firstly, we will analyze scaling approaches and then select the proper ones for our system.
"What does it really mean for your system to be available, or how to define w...Fwdays
We will talk about system monitoring from a few different angles. We will start by covering the basics, then discuss SLOs, how to define them, and why understanding the business well is crucial for success in this exercise.
Freshworks Rethinks NoSQL for Rapid Scaling & Cost-EfficiencyScyllaDB
Freshworks creates AI-boosted business software that helps employees work more efficiently and effectively. Managing data across multiple RDBMS and NoSQL databases was already a challenge at their current scale. To prepare for 10X growth, they knew it was time to rethink their database strategy. Learn how they architected a solution that would simplify scaling while keeping costs under control.
Introduction of Cybersecurity with OSS at Code Europe 2024Hiroshi SHIBATA
I develop the Ruby programming language, RubyGems, and Bundler, which are package managers for Ruby. Today, I will introduce how to enhance the security of your application using open-source software (OSS) examples from Ruby and RubyGems.
The first topic is CVE (Common Vulnerabilities and Exposures). I have published CVEs many times. But what exactly is a CVE? I'll provide a basic understanding of CVEs and explain how to detect and handle vulnerabilities in OSS.
Next, let's discuss package managers. Package managers play a critical role in the OSS ecosystem. I'll explain how to manage library dependencies in your application.
I'll share insights into how the Ruby and RubyGems core team works to keep our ecosystem safe. By the end of this talk, you'll have a better understanding of how to safeguard your code.
Must Know Postgres Extension for DBA and Developer during MigrationMydbops
Mydbops Opensource Database Meetup 16
Topic: Must-Know PostgreSQL Extensions for Developers and DBAs During Migration
Speaker: Deepak Mahto, Founder of DataCloudGaze Consulting
Date & Time: 8th June | 10 AM - 1 PM IST
Venue: Bangalore International Centre, Bangalore
Abstract: Discover how PostgreSQL extensions can be your secret weapon! This talk explores how key extensions enhance database capabilities and streamline the migration process for users moving from other relational databases like Oracle.
Key Takeaways:
* Learn about crucial extensions like oracle_fdw, pgtt, and pg_audit that ease migration complexities.
* Gain valuable strategies for implementing these extensions in PostgreSQL to achieve license freedom.
* Discover how these key extensions can empower both developers and DBAs during the migration process.
* Don't miss this chance to gain practical knowledge from an industry expert and stay updated on the latest open-source database trends.
Mydbops Managed Services specializes in taking the pain out of database management while optimizing performance. Since 2015, we have been providing top-notch support and assistance for the top three open-source databases: MySQL, MongoDB, and PostgreSQL.
Our team offers a wide range of services, including assistance, support, consulting, 24/7 operations, and expertise in all relevant technologies. We help organizations improve their database's performance, scalability, efficiency, and availability.
Contact us: info@mydbops.com
Visit: https://www.mydbops.com/
Follow us on LinkedIn: https://in.linkedin.com/company/mydbops
For more details and updates, please follow up the below links.
Meetup Page : https://www.meetup.com/mydbops-databa...
Twitter: https://twitter.com/mydbopsofficial
Blogs: https://www.mydbops.com/blog/
Facebook(Meta): https://www.facebook.com/mydbops/
inQuba Webinar Mastering Customer Journey Management with Dr Graham HillLizaNolte
HERE IS YOUR WEBINAR CONTENT! 'Mastering Customer Journey Management with Dr. Graham Hill'. We hope you find the webinar recording both insightful and enjoyable.
In this webinar, we explored essential aspects of Customer Journey Management and personalization. Here’s a summary of the key insights and topics discussed:
Key Takeaways:
Understanding the Customer Journey: Dr. Hill emphasized the importance of mapping and understanding the complete customer journey to identify touchpoints and opportunities for improvement.
Personalization Strategies: We discussed how to leverage data and insights to create personalized experiences that resonate with customers.
Technology Integration: Insights were shared on how inQuba’s advanced technology can streamline customer interactions and drive operational efficiency.
Essentials of Automations: Exploring Attributes & Automation ParametersSafe Software
Building automations in FME Flow can save time, money, and help businesses scale by eliminating data silos and providing data to stakeholders in real-time. One essential component to orchestrating complex automations is the use of attributes & automation parameters (both formerly known as “keys”). In fact, it’s unlikely you’ll ever build an Automation without using these components, but what exactly are they?
Attributes & automation parameters enable the automation author to pass data values from one automation component to the next. During this webinar, our FME Flow Specialists will cover leveraging the three types of these output attributes & parameters in FME Flow: Event, Custom, and Automation. As a bonus, they’ll also be making use of the Split-Merge Block functionality.
You’ll leave this webinar with a better understanding of how to maximize the potential of automations by making use of attributes & automation parameters, with the ultimate goal of setting your enterprise integration workflows up on autopilot.
This talk will cover ScyllaDB Architecture from the cluster-level view and zoom in on data distribution and internal node architecture. In the process, we will learn the secret sauce used to get ScyllaDB's high availability and superior performance. We will also touch on the upcoming changes to ScyllaDB architecture, moving to strongly consistent metadata and tablets.
"$10 thousand per minute of downtime: architecture, queues, streaming and fin...Fwdays
Direct losses from downtime in 1 minute = $5-$10 thousand dollars. Reputation is priceless.
As part of the talk, we will consider the architectural strategies necessary for the development of highly loaded fintech solutions. We will focus on using queues and streaming to efficiently work and manage large amounts of data in real-time and to minimize latency.
We will focus special attention on the architectural patterns used in the design of the fintech system, microservices and event-driven architecture, which ensure scalability, fault tolerance, and consistency of the entire system.
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2024/06/temporal-event-neural-networks-a-more-efficient-alternative-to-the-transformer-a-presentation-from-brainchip/
Chris Jones, Director of Product Management at BrainChip , presents the “Temporal Event Neural Networks: A More Efficient Alternative to the Transformer” tutorial at the May 2024 Embedded Vision Summit.
The expansion of AI services necessitates enhanced computational capabilities on edge devices. Temporal Event Neural Networks (TENNs), developed by BrainChip, represent a novel and highly efficient state-space network. TENNs demonstrate exceptional proficiency in handling multi-dimensional streaming data, facilitating advancements in object detection, action recognition, speech enhancement and language model/sequence generation. Through the utilization of polynomial-based continuous convolutions, TENNs streamline models, expedite training processes and significantly diminish memory requirements, achieving notable reductions of up to 50x in parameters and 5,000x in energy consumption compared to prevailing methodologies like transformers.
Integration with BrainChip’s Akida neuromorphic hardware IP further enhances TENNs’ capabilities, enabling the realization of highly capable, portable and passively cooled edge devices. This presentation delves into the technical innovations underlying TENNs, presents real-world benchmarks, and elucidates how this cutting-edge approach is positioned to revolutionize edge AI across diverse applications.
"Frontline Battles with DDoS: Best practices and Lessons Learned", Igor IvaniukFwdays
At this talk we will discuss DDoS protection tools and best practices, discuss network architectures and what AWS has to offer. Also, we will look into one of the largest DDoS attacks on Ukrainian infrastructure that happened in February 2022. We'll see, what techniques helped to keep the web resources available for Ukrainians and how AWS improved DDoS protection for all customers based on Ukraine experience
"Frontline Battles with DDoS: Best practices and Lessons Learned", Igor Ivaniuk
8086 labmanual
1. Microprocessor Lab
For
IV Semester Electronics & Communication
Department of Electronics & Communication
Sri Siddhartha Institute of Technology
Maralur, Tumkur
2. CONTENTS
8085 MICROPROCESSOR LAB PROGRAMS
1. To move data block from one location to other without overlap
2. To move data block from one location to other with overlap
3. To arrange a set of 8-bit numbers in ascending order
4. Addition of binary numbers
5. To add two multibyte binary numbers
6. To add 2-digit BCD numbers
7. To subtract 16-bit binary numbers
8. To check the fourth bit of a byte
9. To generate resultant byte for given Boolean equation
10. Successive addition of two unsigned binary numbers
11. To find the product of two unsigned binary numbers
12. To divide two 16 bit numbers
13. To implement counter from 00-99
14. To implement counter from 99-00
15. To implement counter from 00-FF
16. To implement counter from FF-00
17. To check 2 out of 5 code
18. To add ‘N’ one byte binary numbers
19. To realize real time clock
20. To convert binary to BCD equivalent
21. To convert binary to ASCII equivalent
22. To convert ASCII to binary equivalent
23. To convert BCD to binary equivalent
INTERFACING PROGRAMS
24. To generate square wave of given duty cycle using DAC
25. To generate a triangular waveform using DAC
26. To generate a staircase waveform using DAC
27. To sense a keyboard
28. To implement a moving display of a given string of digits
29. To display a message on the display unit using 8279 chip
30. To simulate throw of a dice
3. Sri Siddhartha Institute of Technology
1) (a) An ALP to transfer a given block of data from source memory block to destination memory block with
out overlap
data segment
var1 dw 12h,34h,45h,67h,56h
cnt dw 5
res dw ?
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov ax,cnt
mov si,0000h
next: mov ax,var1[si]
mov res[si],ax
inc si
inc si
loop next
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 1
4. Sri Siddhartha Institute of Technology
1 (b) An ALP to transfer a given block of data from source memory block to destination memory block with
overlap
data segment
y db 3 dup(0)
x db 11h,22h,33h,44h,55h
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
lea si,x
lea di,y
mov cx,0005h
loc1: mov al,[si]
mov[di],al
inc si
inc di
dec cx
jnz loc1
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 2
5. Sri Siddhartha Institute of Technology
2) An ALP to add 16-bit bytes/words & to find the average of numbers.
data segment
N1 dw 0020h,0002h,0002h,0002h
res dw ?
cnt db 04h
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov cl,cnt
mov si,0000h
mov dx,0000h
next: mov ax,N1[si]
add dx,ax
inc si
inc si
loop next
mov ax,dx
div cnt
mov res,ax
mov ah,4Ch
int 21h
code ends
end start
Department of Electronics & Communication 3
6. Sri Siddhartha Institute of Technology
3) An ALP to multiply two 32 bit numbers
data segment
n1 dw 0AFFh,0AFFh
n2 dw 0330h,4002h
res dw ?
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov si,0000h
mov ax,n1[si]
mul n2[si]
mov res,ax
mov bx,dx
mov ax,n1[si+2]
mul n2[si]
add bx,ax
mov cx,dx
mov ax,n1[si]
mul n2[si+2]
add bx,ax
adc cx,dx
mov res+2,bx
mov ax,n1[si+2]
mul n2[si+2]
mul n2[si+2]
add cx,ax
mov res+4,cx
adc dx,0000h
mov res+6,dx
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 4
7. Sri Siddhartha Institute of Technology
4)An ALP to multiply two ASCII byte numbers
data segment
n1 db '3'
n2 db '2'
res db ?
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov al,n1
mov bl,n2
sub al,30h
sub bl,30h
mul bl
aam
add ax,3030h
mov res,al
mov res+1,ah
mov ah,4Ch
int 21h
code ends
end start
Department of Electronics & Communication 5
8. Sri Siddhartha Institute of Technology
5)(a) An ALP to find LCM of two 16 bit unsigned integers.
data segment
n1 dw 019h
n2 dw 00Fh
lcm dw 2 dup(?)
data ends
code segment
assume cs:code,ds:datastart:
Start: mov ax,data
mov ds,ax
mov ax,n1
mov bx,n2
mov dx,0000h
again: push ax
push dx
div bx
cmp dx,0000h
je exit
pop dx
pop ax
add ax,n1
jnc nincdx
inc dx
nincdx: jmp again
exit: pop lcm+2
pop lcm
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 6
9. Sri Siddhartha Institute of Technology
5)(b) An ALP to find GCF of two 16 bit unsigned integers.
data segment
n1 dw 005Ah,0078h
res dw ?
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov ax,n1
mov bx,n1+2
again: cmp ax,bx
je exit
jb big
above: mov dx,0h
div bx
cmp dx,0
je exit
mov ax,dx
jmp again
big: xchg ax,bx
jmp above
exit: mov res,bx
mov ah,4Ch
int 21h
code ends
end start
Department of Electronics & Communication 7
10. Sri Siddhartha Institute of Technology
6)(a) An ALP to sort a given set of 16 bit unsigned integers into ascending order using insertion sort.
Program to sort a given a 16bit unsigned integers into ascending order using insertion sort
data segment
a dw 78h,34h,12h,56h
si_ze dw ($-a)/2
data ends
code segment
assume cs:code,ds:data
start : mov ax,data
mov ds,ax
mov cx,2
outloop: mov dx,cx
dec dx
mov si,dx
add si,si
mov ax,a[si]
inloop : cmp a[si-2],ax
jbe inexit
mov di,a[si-2]
mov a[si],di
dec si
dec si
dec dx
jnz inloop
inexit : mov a[si],ax
inc cx
cmp cx,si_ze
jbe outloop
int 21h
code ends
end start
Department of Electronics & Communication 8
11. Sri Siddhartha Institute of Technology
6)(b) An ALP to sort a given set of 16 bit unsigned integers into ascending order using bubble sort.
data segment
a db 34h,78h,12h,56h
size dw $-a
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov bx,size
dec bx
outloop: mov cx,bx
mov si,0
inloop: mov al,a[si]
inc si
cmp al,a[si]
jb nochang
xchg al,a[si]
mov a[si-1].al
nochang: loop inloop
dec bx
jnz outloop
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 9
12. Sri Siddhartha Institute of Technology
7) An ALP to generate 10 fibonacci numbers.(Read initial values via key board)
data segment
n db 01fh
fib db 15 dup(?)
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov bx,0
term : mov dl,0
push bx
call fibo
pop bx
cmp dx,n
ja exit
mov fib[bx],dx
inc bx
jmp term
exit : mov ah,4ch
int 3
fibo : cmp bx,0
je exit1
cmp bx,1
je exit2
dec bl
push bx
call fibo
pop bx
dec bx
call fibo
ret
exit1: ret
exit2: inc dl
ret
align 16
code ends
end start
Department of Electronics & Communication 10
13. Sri Siddhartha Institute of Technology
8) An ALP to generate prime numbers from 1 to 50 BCD.
data segment
x db 2,14 dup(?)
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov dl,x
lea si,x+1
mov ch,14
loc1: mov dh,02
inc dl
loc2: mov ah,0
mov al,dl
div dh
cmp ah,0
je loc1
inc dh
cmp dh,dl
jb loc2
mov al,1
mul dl
aam
mov cl,04
rol al,cl
ror ax,cl
mov[si],al
inc si
dec ch
jnz loc1
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 11
14. Sri Siddhartha Institute of Technology
9)An ALP to transfer given source string to destination string using string instructions.
Data segment
d1 db "welcome","$"
d2 db 10dup(0)
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov es,ax
mov cx,07h
cld
mov si,offset d1
mov di,offset d2
rep movsb
mov cx,07h
std
mov si,offset d1+6
mov di,offset d2+14
rep movsb
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 12
15. Sri Siddhartha Institute of Technology
10)An ALP to perform the following operations.
(a) Reverse a string.
data segment
m1 db 10,13,'enter the string:$'
m2 db 10,13,'reverse of a string:$'
buff db 80
db 0
db 80 dup(0)
counter1 dw 0
counter2 dw 0
data ends
code segment
assume cs: code, ds:data
start: mov ax,data
mov ds,ax
mov ah,09h
mov dx,offset m1
int 21h
mov ah,0ah
lea dx,buff
int 21h
mov ah,09h
mov dx,offset m2
int 21h
lea bx,buff
inc bx
mov ch,00
mov cl,buff+1
mov di,cx
back: mov dl,[bx+di]
mov ah,02h
int 21h
dec di
jnz back
exit: mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 13
16. Sri Siddhartha Institute of Technology
(b)Deleting a word from a string.
data segment
x db 'aa','bb', 'cc','dd','ee','ff'
z dw (z-x)/2
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov es,ax
lea di,x
mov cx,z
cld
mov ax,'cc' ;word to be deleted
repne scasw
cmp cx,0
je loc2
mov ax,[di]
loc1: mov [di-2],ax
inc di
inc di
dec cx
jnz loc1
mov byte ptr[di-2],'$'
loc2: lea dx,x
mov ah,09h
int 21h
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 14
17. Sri Siddhartha Institute of Technology
c)Searching a word from a string.
data segment
n1 db 12h,14h,78h,67h,34h
key db 23h
cnt db 5
m1 db 'the key found in'
res db 'the position ',13h,10h,'$'
m2 db 'not found',13h,10h,'$'
data ends
code segment
assume cs: code,ds:data
start: mov ax,data
mov ds,ax
mov si,00h
mov cx,cnt
next: mov al,n1[si]
cmp al,key
jz suc
inc si
loop next
jmp fall
suc: mov ax,si
add al,01h
add al,'0'
mov res,al
lea dx,m1
jmp exit
fall: lea dx,m2
jmp exit
exit: mov ah,09h
int 21h
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 15
18. Sri Siddhartha Institute of Technology
(d) To check whether a string is palindrome or not.
data segment
inst db 20 dup(0)
mes1 db 0Ah,0Dh,"insert the string:$"
mes2 db 0Ah,0Dh,"it is a palindrome:$"
mes3 db 0Ah,0Dh,"it is not a palindrome:$"
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov ah,09h
lea dx,mes1
int 21
mov bx,00h
up: mov ah,01h
int 21h
cmp al,0Dh
jz down
mov[inst+bx],al
inc bx
jmp up
down: mov di,00h
dec bx
check: mov al,[inst+bx]
cmp al,[inst+di]
jne fail
inc di
dec bx
jnz check
jmp finish
fail: mov ah,09h
lea dx,mes3
int 21h
jmp term
finish: mov ah,09h
lea dx,mes2
int 21h
term: mov ah,4Ch
int 21h
code ends
end start
Department of Electronics & Communication 16
19. Sri Siddhartha Institute of Technology
11) An ALP to multiply two matrices .
data segment
ar1 db 1h,2h,-3h
ar2 db 4h,5h,6h
ar3 db 2h,-1h,3h
bc1 db 2h,4h,-4h
bc2 db 3h,-2h,5h
bc3 db 1h,5h,2h
c db 9 dup (?)
l2 db (?)
l1 db (?)
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov es,ax
mov bp,0h
mov l2,3h
lea si,ar1
repeat2: lea di,bc1
mov l1,3h
repeat1: mov cx,3h
mov bx,0h
mov dl,0h
again: mov al,[si][bx]
imul byte ptr[di][bx]
add dl,al
inc bx
loop again
mov ds:c[bp],dl
inc bp
add di,3h
dec l1
jne repeat1
add si,3h
dec l2
jne repeat2
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 17
20. Sri Siddhartha Institute of Technology
12)(a) An ALP to find trace of a matrix.
data segment
matrix db 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh, 0ffh ;3*3
row dw 0003h ;no. of rows
col dw 0003h ;no. of cols
trace dw ?
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov si,00h
mov bx,00h
mov ax,row
cmp ax,col
jnz fail
mov ax,00h
mov cx,row
again: add al,matrix[si][bx]
jnc skip
inc ah
skip: inc si
add bx,col
loop again
mov trace,ax
jmp ovr
fail: mov trace,00h
ovr: mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 18
21. Sri Siddhartha Institute of Technology
12)(b) An ALP to find the norms of the matrix.
Program to find trace of the matrix
data segment
matrix db 0ffh,0ffh,0ffh,0ffh,0ffh,0ffh,0ffh,0ffh,0ffh ;3x3row dw 0003h ;no. of rows
col dw 0003h ;no. of cols
norm dw 2 dup (0000h)
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov si,00h
mov bx,00h
mov ax,row
cmp ax,col
jnz fail
mov cx,row
again: mov ax,norm
mov al,matrix[si][bx]
mul matrix[si][bx]
mov ax,norm
jnc skip
add norm+2,01h
inc ah
skip: mov norm,ax
inc si
add bx,0003h
loop again
jmp ovr
fail: mov norm,00h
ovr: mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 19
22. Sri Siddhartha Institute of Technology
13)An ALP to search that implements binary search algorithm.
data segment
x dw 11h,22h,33h,44h,55h,66h,77h
z dw (z-x)
key dw 66h
y dw ?
data ends
code segment
assume cs:code,ds:data
start: mov ax,data
mov ds,ax
mov cx,key
mov dx,z
dec bx
mov bx,0
loc3: mov si,bx
add si,1
and si,0fffeh
cmp cx,x[si]
je loc1
jb loc2
add si,2
mov bx,si
loc5: cmp bx,dx
jna loc3
mov y,0
loc4: mov ah,4ch
int 21h
loc1: shr si,1
inc si
mov y,si
jmp loc1
loc2: sub si,2
mov dx,si
jmp loc5
mov ah,4ch
int 21h
code ends
end start
Department of Electronics & Communication 20
23. Sri Siddhartha Institute of Technology
Part-II 8051 8-bit Microcontroller
1. Program to transfer a block from source to destination
ADDRESS LABEL MNEMONIC
8000 MOV DPTR,#9000H
8003 MOV R0,#04H
8005 MOV R1,#90H
8007 MOV R2,#91H
8009 BACK MOVX A,@DPTR
800A MOV 83H,R2
800C MOVX @DPTR,A
800D MOV 83H,R1
800F INC DPTR
8010 DJNZ R0,8009(BACK)
8012 LCALL 0003
Department of Electronics & Communication 21
24. Sri Siddhartha Institute of Technology
2. Program to exchange data between two blocks
Starting address of block1, data memory 9000& starting address of block2, data memory 9100.
ADDRESS LABEL MNEMONIC
8000 MOV DPTR, #9000H
8003 MOV R0, #04H
8005 MOV R1, #90H
8007 MOV R2, #91H
8009 MOVX A, @DPTR
800A MOV R3, A
800B MOV 83H,R2
800D MOVX A, @DPTR
800E MOV 83H,R1
8010 MOVX @DPTR, A
8011 MOV A, R3
8012 MOV 83H,R2
8014 MOVX @DPTR, A
8015 MOV 83H,R1
8017 INC DPTR
8018 DJNZ R0, 8009
801A LCALL 0003
Department of Electronics & Communication 22
25. Sri Siddhartha Institute of Technology
3.Program to find average of n numbers.
ADDRESS LABEL MNEMONIC
8000 MOV DPTR,#9000H
8003 MOV R0,#O4H
8005 MOV R1,#00H
8007 MOV R2,#00H
8009 CLR C
800A MOV R4,#04H
800C BACK MOVX A,DPTR
800D MOV R3,A
800E INC DPTR
800F MOV A,R1
8010 ADD A,R3
8011 JNC 8014H(AHEAD)
8013 IND R2
8014 AHEAD MOV R1,A
8015 DJNZ R0,800CH
8017 MOV R5,#00H
8019 CLR C
801A MOV A,R1
801B AGAIN SUBB A,R4
801C INC R5
801D JC 8021H
801F SJMP 801BH
8021 NEXT CJNE R2,#00H,802CH
8024 DEC R5
8025 ADD A,R4
8026 MOVX @DPTR,A
8027 MOV A,R5
8028 INC DPTR
8029 MOVX @DPTR,A
802A SJMP 802FH(END)
802C LOC DEC R2
802D SJMP 801BH
802F END LCALL 0003
Department of Electronics & Communication 23
26. Sri Siddhartha Institute of Technology
4. Program to multiply a 16 bit number with an 8 bit number
8 bit stored at data memory 9000 & 16 bit stored at data memory 9001 & 9002, result stored at data memory 9003, 9004 &
9005.
ADDRESS LABEL MNEMONIC
8000 MOV DPTR,#9000
8003 MOVX A,@DPTR
8004 MOV RO,A
8005 INC DPTR
8006 MOVX A,DPTR
8007 MOV R1,A
8008 INC DPTR
8009 MOVX A,DPTR
800B MOV F0,A
800C MOV A,RO
800D MUL AB
800E MOV R3,A
8010 MOV R4,F0
8012 MOV F0,R1
8013 MOV A,R0
8014 MUL AB
8015 MOV R5,A
8017 MOV R6,F0
8018 INC DPTR
8019 MOV A,R3
801A MOVX @DPTR,A
801B MOV A,R4
801C CLR C
801D INC DPTR
801E ADD A,R5
801F MOVX @DPTR,A
8021 MOV A,#00
8022 ADDC A,R6
8023 INC DPTR
8024 MOVX @DPTR,A
8026 LCALL 0003
.
Department of Electronics & Communication 24
27. Sri Siddhartha Institute of Technology
5. Program to generate 10 Fibonacci numbers.
Stored in data memory address 9000 & 9001
ADDRESS LABEL MNEMONIC
8000 MOV DPTR,#9000
8003 MOV R3,#08
8005 MOVX A,@DPTR
8006 MOV R0,A
8007 INC DPTR
8008 MOVX A,@DPTR
8009 BACK XCH A,R0
800A ADD A,R0
800B INC DPTR
800C MOVX @DPTR,A
800D DJNZ R3,BACK(8009)
800F LCALL 0003
Department of Electronics & Communication 25
28. Sri Siddhartha Institute of Technology
. Program to find GCD & LCM of two 8-bit numbers.
Two 8-bit numbers are stored at location 9000&9001, GCD at location 9002 & LCM At location 9003
ADDRESS LABEL MNEUMONIC
8000 MOV DPTR,#9000H
8003 MOVX A,@DPTR
8004 MOV R0,A
8005 NOP
8006 INC DPTR
8007 MOVX A,@DPTR
8008 CJNE A,000H,NEXT(800D
800B SJMP AHEAD(8014)
800D JNC GO(8010)
800F XCH A,R1
8010 CLR C
8011 SUBB A,R0
8012 SJMP BACK(8008)
8014 INC DPTR
8015 MOVX @DPTR,A
8016 INC DPTR
8017 MOV 0F0H,A
8000 MOV 82H,#OOH
8000 MOVX A,@DPTR
8000 DIV AB
8000 MOV OFOH,A
8000 INC DPTR
8000 MOVX A,@DPTR
8000 MUL AB
8000 MOV 82H,#03H
8000 MOVX @DPTR,A
LCALL 0003
Department of Electronics & Communication 26
29. Sri Siddhartha Institute of Technology
7(a) Program to add multibyte numbers
ADDRESS LABEL MNEMONIC
8000 MOV DPTR,#9000H
8003 MOV R1,#04H
8005 MOV R2,#90H
8007 MOV R3,#91H
8009 MOV R4,#92H
800B CLR C
800C MOV 83H,R2
800E MOVX A,@DPTR
800F MOV R5,A
8010 MOV 83H,R3
8012 MOVX A,@DPTR
8013 ADDC A,R5
8014 MOV 83H,R4
8016 MOVX @DPTR,A
8017 INC DPTR
8018 DJNZ R1,800CH
801A JNC 801FH
801C MOV A,#01H
801E MOVX @DPTR,A
801F LCALL 0003
Department of Electronics & Communication 27
30. Sri Siddhartha Institute of Technology
7(b) program to subtract multibyte numbers
ADDRESS LABEL MNEMONIC
8000 MOV DPTR,#9000H
8003 MOV R1,#04H
8005 MOV R2,#90H
8007 MOV R3,#91H
8009 MOV R4,#92H
800B CLR C
800C MOV 83H,R2
800E MOVX A,@DPTR
800F MOV R5,A
8010 MOV 83H,R3
8012 MOVX A,@DPTR
8013 SUBB A,R5
8014 MOV 83H,R4
8016 MOVX @DPTR,A
8017 INC DPTR
8018 DJNZ R1,800CH
801A LCALL 0003H
801C MOV A,#01H
801E MOVX @DPTR,A
801F LCALL 0003
Department of Electronics & Communication 28
31. Sri Siddhartha Institute of Technology
8.Program to search the key element in the block of data and displays it’s position and it’s position number if
it is found, else display not found.
ADDRESS LABEL MNEOMONIC
8000 MOV 0DOH,#20H
8003 MOV DPTR,#9000H
8006 MOV R2,00H
8008 MOV R1,#04H
800A MOVX A,@DPTR
800B MOV R0,A
800C INC DPTR
800D INC R2
800E MOVX A,@DPTR
800F CJNE A,00H,8014H
8012 SJMP 801BH
8014 DJNZ R1,800CH
8016 MOV DPTR,#9500H
8019 SJMP 8025H
801B MOV A,R2
801C ADD A,#30H
801E MOV DPTR,#940CH
8021 MOVX @DPTR,A
8022 MOV DPTR,#9400H
8025 LCALL 164BH
8028 LCALL 0003
Department of Electronics & Communication 29
32. Sri Siddhartha Institute of Technology
9. Program to sort the number in ascending order using bubble sort.
ADDRESS LABEL MNEMONIC
8000 MOV DPTR,#9000
8003 MOV R1,#04H
8005 AGAIN PUSH 82H
8007 MOV A,R1
8008 MOV R4,A
8009 MOV R2,82H
800B BACK MOVX A,@DPTR
800C MOV R3,A
800D INC DPTR
800E INC R2
800F MOVX A,DPTR
8010 CJNE A,03H,NEXT(8015)
8013 SJMP AHEAD(8020)
8015 NEXT JNC AHEAD
8017 DEC R2
8018 MOV 82H,R2
801A MOVX @DPTR,A
801B MOV A,R3
801C INC R2
801D MOV 82H,R2
801F MOVX @DPTR,A
8020 AHEAD DJNZ R4,BACK(800B)
8022 POP 82H
8024 NOP
8025 DJNZ R1,AGAIN(8005)
8027 LCALL 0003
Department of Electronics & Communication 30
33. Sri Siddhartha Institute of Technology
VISVESHWARAIAH TECHNOLOGICAL UNIVERSITY, BELGAUM
Branch: EC Semester: VI
Subject code: EC6L2
Subject title: Advanced microprocessor & Micro controller lab
QUESTION BANK
Instructions:
1.Experiments on micro controller can be carried out using any 8-bit/16-bit micro controller kit.
2.A student should be given only one question either from part-1 or from part-II for the examination.
3.For each batch in examination, around 60% of the questions should be from part-I and around 40% of the questions should be from part-II.
4.No change of experiment/question is permitted in the examination.
PART-I
1.Write an ALP to transfer a given block of data (byte/word) from source memory block to destination memory block with or without overlapping.
2. Write an ALP to transfer given source string to destination using string instructions.
3.Write an ALP to perform the following string operations:
a) Reverse a string, search/delete a word from a string
b) Check if the given string is palindrome or not.
4.Write an ALP to add 16 bytes/words and find the average and display.
5.write an ALP to multiply two 32 bit numbers and display.
6.Write an ALP to multiply two ASCII byte numbers and display.
7.Develop and execute an ALP to find GCF/LCM of two 16-bit unsigned integers.
8.Develop and execute an ALP to sort a given set of 16-bit unsigned integers into ascending order using insertion/bubble sort algorithm.
9.Write an ALP to generate 10 fibonacci numbers, Read initial values via keyboard.
10.Write an Alp to generate prime numbers between 1 to 50 BCD.
11.Write an ALP to multiply two matrices &display.
12.Write an ALP to find
a) Sum of principal diagonal elements (trace of a matrix)
b) Norms of the matrix (sum of the squares of the principal diagonal elements)
13.Develop and execute an ALP that implements binary search algorithm. Assume that the data consist of sorted 16-bit integers. Search key is also a 16-bit
unsigned integer.
14.Interface a logic controller via 8255 using I/O cards and perform the following operations.
Read all the 8 inputs from the logic controller. Complement and display on the outputs.
PART-II
15.Write an Alp to transfer a block of data from a given source to destination using 8051/equivalent.
16.Writ an ALP to find average of 10 data bytes in a memory using 8051/equivalent.
17.Write an ALP to multiply 16bit by 8-bit data using micro controller.
18 Write an ALP to generate 10 fibonacci numbers using 8051/equivalent.
19.Interface a printer to 8051/equivalent to operate in
a) Handshake mode
b) Interrupt driven mode
20.Develop and execute an ALP to find GCF/LCM of two 8-bit numbers using 8051/equivalent.
21.Write an ALP to add/subtract two multibyte numbers using micro controller.
22.Write an ALP to search a given key element from an array of integers using 8051/equivalent.
23.Write an ALP to sort an array using bubble sort. Display the sorted array.
24.Write an ALP to interchange two blocks of data residing at memory using 8051/equivalent.
Department of Electronics & Communication 31
34. Operation Code-Sheet
Mnemonic Hex Mnemonic Hex Mnemonic Hex Mnemonic Hex
ACI 8-bit CE DCX SP 3B MOV D, H 54 RAR 1F
ADC A 8F DI F3 MOV D, L 55 RC D8
ADC B 88 EI FB MOV D, M 56 RET C9
ADC C 89 HLT 76 MOV E, A 5F RIM C2
ADC D 8A IN 8-bit DB MOV E, B 58 RLC 07
ADC E 8B INR A 3C MOV E, C 59 RM F8
ADC H 8C INR B 04 MOV E, D 5A RNC D0
ADC L 8D INR C 0C MOV E, E 5B RNZ C0
ADC M 8E INR D 14 MOV E, H 5C RP F0
ADD A 87 INR E 1C MOV E, L 5D RPE E8
ADD B 80 INR H 24 MOV E, M 5E RPO E0
ADD C 81 INR L 2C MOV H, A 67 RRC 0F
ADD D 82 INR M 34 MOV H, B 60 RST 0 C7
ADD E 83 INX B 03 MOV H, C 61 RST 1 CF
ADD H 84 INX D 13 MOV H, D 62 RST 2 D7
ADD L 85 INX H 23 MOV H, E 63 RST 3 DF
ADD M 86 INX SP 33 MOV H, H 64 RST 4 E7
ADI 8-bit C6 JC 16-bit DA MOV H, L 65 RST 5 EF
ANA A A7 JM 16-bit FA MOV H, M 66 RST 6 F7
ANA B A0 JMP 16-bit C3 MOV L, A 6F RST 7 FF
ANA C A1 JNC 16-bit D2 MOV L, B 68 RZ C8
ANA D A2 JNZ 16-bit C2 MOV L, C 69 SBB A 9F
ANA E A3 JP 16-bit F2 MOV L, D 6A SBB B 98
ANA H A4 JPE 16-bit EA MOV L, E 6B SBB C 99
ANA L A5 JPO 16-bit E2 MOV L, H 6C SBB D 9A
ANA M A6 JZ 16-bit CA MOV L, L 6D SBB E 9B
ANI 8-bit E6 LDA 16-bit 3A MOV L, M 6E SBB H 9C
CALL 16-bit CD LDAX B 0A MOV M, A 77 SBB L 9D
CC 16-bit DC LDAX D 1A MOV M, B 70 SBB M 9E
CM 16-bit FC LHLD 16-bit 2A MOV M, C 71 SBI 8-bit DE
CMA 2F LXI B, 16-bit 01 MOV M, D 72 SHLD 16-bit 22
CMC 3F LXI D, 16-bit 11 MOV M, E 73 SIM 30
CMP A BF LXI H, 16-bit 21 MOV M, H 74 SPHL F9
CMP B B8 LXI SP, 16-bit 31 MOV M, L 75 STA 16-bit 32
CMP C B9 MOV A, A 7F MVI A, 8-bit 3E STAX B 02
CMP D BA MOV A, B 78 MVI B, 8-bit 06 STAX D 12
CMP E BB MOV A, C 79 MVI C, 8-bit 0E STC 37
CMP H BC MOV A, D 7A MVI D, 8-bit 16 SUB A 97
CMP L BD MOV A, E 7B MVI E, 8-bit 1E SUB B 90
CMP M BE MOV A, H 7C MVI H, 8-bit 26 SUB C 91
CNC 16-bit D4 MOV A, L 7D MVI L, 8-bit 2E SUB D 92
CNZ 16-bit C4 MOV A, M 7E MVI M, 8-bit 36 SUB E 93
CP 16-bit F4 MOV B, A 47 NOP 00 SUB H 94
CPE 16-bit EC MOV B, B 40 ORA A B7 SUB L 95
CPI 8-bit FE MOV B, C 41 ORA B B0 SUB M 96
CPO 16-bit E4 MOV B, D 42 ORA C B1 SUI 8-bit D6
CZ 16-bit CC MOV B, E 43 ORA D B2 XCHG EB
DAA 27 MOV B, H 44 ORA E B3 XRA A AF
DAD B 09 MOV B, L 45 ORA H B4 XRA B A8
DAD D 19 MOV B, M 46 ORA L B5 XRA C A9
DAD H 29 MOV C, A 4F ORA M B6 XRA D AA
DAD SP 39 MOV C, B 48 ORI 8-bit F6 XRA E AB
DCR A 3D MOV C, C 49 OUT 8-bit D3 XRA H AC
DCR B 05 MOV C, D 4A PCHL E9 XRA L AD
DCR C 0D MOV C, E 4B POP B C1 XRA M AE
DCR D 15 MOV C, H 4C POP D D1 XRI 8-bit EE
DCR E 1D MOV C, L 4D POP H E1 XTHL E3
DCR H 25 MOV C, M 4E POP PSW F1 UPDAD 06BF
DCR L 2D MOV D, A 57 PUSH B C5 UPDDT 06D6
DCR M 35 MOV D, B 50 PUSH D D5
DCX B 0B MOV D, C 51 PUSH H E5
DCX D 1B MOV D, D 52 PUSH PSW F5
DCX H 2B MOV D, E 53 RAL 17
Department of E & C SSIT