Tools for the Reality Technology (實境技術工具介紹)Jian-Kai Wang
本次分享的實境技術主題,將探討虛擬實境(VR)與擴增實境概念(AR)與實現的工具,並說明專屬與非專屬開發平台及開發工具串聯的分工,可以快速掌握實境技術的趨勢與開發方式。
This topic shares you with reality technology, including virtual reality (VR) and augmented reality (AR). This topic also includes the developed tools used in a specific or non-specific platform. Through this topic, you can catch the trend of reality technology.
Tools for the Reality Technology (實境技術工具介紹)Jian-Kai Wang
本次分享的實境技術主題,將探討虛擬實境(VR)與擴增實境概念(AR)與實現的工具,並說明專屬與非專屬開發平台及開發工具串聯的分工,可以快速掌握實境技術的趨勢與開發方式。
This topic shares you with reality technology, including virtual reality (VR) and augmented reality (AR). This topic also includes the developed tools used in a specific or non-specific platform. Through this topic, you can catch the trend of reality technology.
3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC).
3D IC Presented by Tripti Kumari, School of Engineering, CUSATthevijayps
A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit.
In the 3-D design architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.
In a generic 3D IC structure, each die is stacked on top of another and communicated by Through-Silicon Vias (TSVs).
Architectural issues
Traditional shared buses do not scale well – bandwidth saturation
Chip IO is pad limited
Physical issues
On-chip Interconnects become increasingly slower w.r.t. logic
IOs are increasingly expensive
Consequences
Performance losses
Power/Energy cost
Design closure issues or infeasibility
Reduced wire length
Total wire length
Larger circuits produce more improvement
Lower power per transistor
Decreased interconnect delay
Higher transistor packing densities
Smaller chip areas
There are four ways to build a 3D IC:
Monolithic
Wafer-on-Wafer
Die-on-Wafer
Die On Die
At runtime, thermal variations will introduce additional time-varying clock skew, further increasing design uncertainty
2 - Thermal Issues In 3-D ICs
Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density
Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and design options.
3 - Reliability Issues In 3-D ICs
Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance
Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.
TSV check on reset
Control use dedicated Vias in order to establish which vias are corrupted.
If 1, 2 and 3 TSVs are OK, the control set the enable signal set_to and set_from: broken path are skipped!
Pads routing shift as show in the figure
Need to define The handling protocol during the TSVs check
3D IC design is a relief to interconnect driven IC design.
Still many manufacturing and technological difficulties
Physical Design needs to consider the multiple layers of Silicon available.
Optimization of both temperature and wirelength
Placement and routing algorithms need to be modified
[1] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001.
[2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep- submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC).
3D IC Presented by Tripti Kumari, School of Engineering, CUSATthevijayps
A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit.
In the 3-D design architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.
In a generic 3D IC structure, each die is stacked on top of another and communicated by Through-Silicon Vias (TSVs).
Architectural issues
Traditional shared buses do not scale well – bandwidth saturation
Chip IO is pad limited
Physical issues
On-chip Interconnects become increasingly slower w.r.t. logic
IOs are increasingly expensive
Consequences
Performance losses
Power/Energy cost
Design closure issues or infeasibility
Reduced wire length
Total wire length
Larger circuits produce more improvement
Lower power per transistor
Decreased interconnect delay
Higher transistor packing densities
Smaller chip areas
There are four ways to build a 3D IC:
Monolithic
Wafer-on-Wafer
Die-on-Wafer
Die On Die
At runtime, thermal variations will introduce additional time-varying clock skew, further increasing design uncertainty
2 - Thermal Issues In 3-D ICs
Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density
Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and design options.
3 - Reliability Issues In 3-D ICs
Electro thermal and Thermo-mechanical effects between various active layers can influence electro-migration and chip performance
Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.
TSV check on reset
Control use dedicated Vias in order to establish which vias are corrupted.
If 1, 2 and 3 TSVs are OK, the control set the enable signal set_to and set_from: broken path are skipped!
Pads routing shift as show in the figure
Need to define The handling protocol during the TSVs check
3D IC design is a relief to interconnect driven IC design.
Still many manufacturing and technological difficulties
Physical Design needs to consider the multiple layers of Silicon available.
Optimization of both temperature and wirelength
Placement and routing algorithms need to be modified
[1] J. Davis, et al., "Interconnect limits on gigascale integration (GSI) in the 21st century," Proceedings of the IEEE , vol.89, no.3, pp.305-324, Mar 2001.
[2] Banerjee, K.; Souri, S.J.; Kapur, P.; Saraswat, K.C.; , "3-D ICs: a novel chip design for improving deep- submicrometer interconnect performance and systems-on-chip integration," Proceedings of the IEEE , vol.89, no.5, pp.602-633, May 2001.
3. 3D Display Technology
Seeing in depth
Not only X and Y axis, but also Z
Stereoscope
Polarized Display
Auto-stereoscope
4. 立體電影
•Anaglyph techniques
–Color separation technique
–Use two complementary colors
to display the left and right
views respectively
–Use red and green glasses to
observe it
–Adv.: simplicity and
economical
5. 3D Content Generation
3D camera
高解析度數位相機,搭配特殊設計的彩色結構光源投射裝置
結合而成,再配合數學運算,可輕易在瞬間擷取實物外觀的
立體幾何形狀,進而建立該物體的彩色立體數位化模型。
虛擬數位博物館典藏品的數位化、人體量測、醫療、 3D 遊
戲動畫
6. 2D To 3D Conversion
Exploration Experiment
EE1 Omni-directional Video
EE2 Free-Viewpoint Video
EE3 Interactive Stereo Video
EE4 Depth/Disparity of 3DTV
Omni-directional
(Panoramic) Video
Free-Viewpoint Video