This document describes the flash programming process for EM35x chips using flashloader firmware. It discusses pin connections, memory organization, creating a programming image, the programming overview and details, gang programming, serialization, and ARM CPU manipulation details used for programming. Programming involves powering up the chip, capturing the CPU, installing and running the flashloader firmware, erasing and programming the flash memory, and verifying the final image.
BlackHat 2009 - Hacking Zigbee Chips (slides)Michael Smith
This document discusses a 16-bit rootkit and second generation Zigbee chips. It describes how the rootkit works by proxying a microcontroller's interrupt vector table to gain control of incoming packets. It also examines vulnerabilities in early Zigbee chips like the EM250 and CC2430 that exposed cryptographic keys due to debug interfaces and memory layout issues. Later generations of chips aim to address these security flaws.
The document describes the SCFIFO and DCFIFO megafunctions provided by Altera. The SCFIFO and DCFIFO megafunctions are parameterized FIFO functions that can be configured through parameters to support single-clock or dual-clock FIFO applications with different port widths and depths. The document provides details on the ports, parameters, timing requirements, and usage of the SCFIFO and DCFIFO megafunctions.
The document provides information about the FlashcatUSB device, which is a versatile multi-protocol Flash memory programmer. It can be used to program flash memory using JTAG, SPI, and NAND interfaces. The document discusses software requirements, lists supported flash devices, explains how to install drivers and set up the device, and provides information on using different modes for flash programming. It also provides an overview of the scripting engine that allows customizing tasks through script files.
This document provides instructions for restoring an APC device's SPI EEPROM using an external programmer like the FlashcatUSB. It involves:
1. Preparing the FlashcatUSB programmer and downloading necessary files from APC and Microsoft websites.
2. Connecting the FlashcatUSB to the APC and running FlashcatUSB software to write the firmware BIN file to the APC's SPI EEPROM.
3. Reinstalling the system firmware from a microSD card and resetting the LAN MAC address using a console cable connected to the APC's debug port.
This document describes the PR5 line following robot project from Cytron Technologies. The robot uses an PIC16F877A microcontroller and infrared sensors to follow a black line on a white surface. It also includes instructions on assembling the robot hardware using motors, wheels, batteries and other components. The software works by using signals from the three IR sensors to determine if the robot needs to move straight or turn to stay on the line.
This document provides an overview and details of ASUS notebook motherboard power circuits and components. It includes diagrams of the power systems used in Sonoma, Napa, Santa Rosa and Montevina platforms. Sample diagrams are shown for the M9V and V6J motherboards. Key integrated circuits used in the power systems like the LTC3728, TPS5130, MAX1987, TPS51020 and ISL6227 switching regulators are described in detail including specifications, pinouts and functions. Troubleshooting tips are provided in a Q&A section.
DefCon 2012 - Sub-1 GHz Radio Frequency SecurityMichael Smith
This document provides an overview of sub-GHz radio frequencies and frequency hopping spread spectrum (FHSS) communications. It discusses FCC regulations for industrial, scientific, and medical (ISM) bands, popular frequencies used, common modulations, and technical details of radio configuration registers for the Chipcon CC1111 radio chip. It also summarizes the goals and capabilities of the RfCat toolkit for analyzing and interacting with sub-GHz radio protocols.
BlackHat 2009 - Hacking Zigbee Chips (slides)Michael Smith
This document discusses a 16-bit rootkit and second generation Zigbee chips. It describes how the rootkit works by proxying a microcontroller's interrupt vector table to gain control of incoming packets. It also examines vulnerabilities in early Zigbee chips like the EM250 and CC2430 that exposed cryptographic keys due to debug interfaces and memory layout issues. Later generations of chips aim to address these security flaws.
The document describes the SCFIFO and DCFIFO megafunctions provided by Altera. The SCFIFO and DCFIFO megafunctions are parameterized FIFO functions that can be configured through parameters to support single-clock or dual-clock FIFO applications with different port widths and depths. The document provides details on the ports, parameters, timing requirements, and usage of the SCFIFO and DCFIFO megafunctions.
The document provides information about the FlashcatUSB device, which is a versatile multi-protocol Flash memory programmer. It can be used to program flash memory using JTAG, SPI, and NAND interfaces. The document discusses software requirements, lists supported flash devices, explains how to install drivers and set up the device, and provides information on using different modes for flash programming. It also provides an overview of the scripting engine that allows customizing tasks through script files.
This document provides instructions for restoring an APC device's SPI EEPROM using an external programmer like the FlashcatUSB. It involves:
1. Preparing the FlashcatUSB programmer and downloading necessary files from APC and Microsoft websites.
2. Connecting the FlashcatUSB to the APC and running FlashcatUSB software to write the firmware BIN file to the APC's SPI EEPROM.
3. Reinstalling the system firmware from a microSD card and resetting the LAN MAC address using a console cable connected to the APC's debug port.
This document describes the PR5 line following robot project from Cytron Technologies. The robot uses an PIC16F877A microcontroller and infrared sensors to follow a black line on a white surface. It also includes instructions on assembling the robot hardware using motors, wheels, batteries and other components. The software works by using signals from the three IR sensors to determine if the robot needs to move straight or turn to stay on the line.
This document provides an overview and details of ASUS notebook motherboard power circuits and components. It includes diagrams of the power systems used in Sonoma, Napa, Santa Rosa and Montevina platforms. Sample diagrams are shown for the M9V and V6J motherboards. Key integrated circuits used in the power systems like the LTC3728, TPS5130, MAX1987, TPS51020 and ISL6227 switching regulators are described in detail including specifications, pinouts and functions. Troubleshooting tips are provided in a Q&A section.
DefCon 2012 - Sub-1 GHz Radio Frequency SecurityMichael Smith
This document provides an overview of sub-GHz radio frequencies and frequency hopping spread spectrum (FHSS) communications. It discusses FCC regulations for industrial, scientific, and medical (ISM) bands, popular frequencies used, common modulations, and technical details of radio configuration registers for the Chipcon CC1111 radio chip. It also summarizes the goals and capabilities of the RfCat toolkit for analyzing and interacting with sub-GHz radio protocols.
The document provides information about Intersoft Institute, an Indian training institute that offers IT and computer repair courses. It lists Intersoft's contact information and history since 1998, including starting mobile and laptop repair training programs. It then describes Intersoft's various computer repair, mobile repair, and other IT courses at both the basic and advanced levels, including modules on laptop hardware, motherboard chip-level repair, and BGA chip replacement. The document aims to provide students with an overview of Intersoft's course offerings and topics covered.
This document provides installation instructions for installing a SV-200MA Surveillance Board in VM-2120 or VM-2240 amplifiers. The SV-200MA adds monitoring, zone control, and backup amplifier functions. It consists of an SV-200M board and SV extension board. The 10 step installation process includes setting jumpers, connecting cables between the boards, mounting the surveillance board, and replacing the amplifier cover.
The document provides an overview and reference manual for the Basys 3 FPGA board from Digilent. Key points:
- The Basys 3 board features an Artix-7 FPGA, 16 user switches and LEDs, pushbuttons, 7-segment display, VGA output, USB and JTAG ports for programming.
- The FPGA can be programmed via the onboard JTAG circuitry using a USB cable, from a file on a SPI flash memory chip, or from a USB memory stick connected to the board.
- The board includes power supplies to support the FPGA and peripherals, which can be powered via USB or an external power source up to 5.5V.
The document discusses three different NSK products:
1. The 8051 Programmer connects via serial or parallel port and programs 8051 microcontrollers. It programs code, lock bits, erases, and verifies.
2. The PIC Programmer programs PIC microcontrollers via serial port and supports various PIC devices. It programs code, lock bits, erases, and verifies.
3. The USB PIC Programmer programs PICs via USB port with auto-programming mode. It programs code, lock bits, erases, verifies, and supports various PIC devices.
This document describes the AT89C2051 microcontroller. Key details include:
- It has 2K bytes of reprogrammable flash memory, 128 bytes of RAM, 15 I/O lines, and various timer/counter and communication features.
- Programming the flash memory involves applying the correct signals to ports to write bytes, erase the entire array, or read back data for verification.
- It has low power idle and power down modes for reduced power consumption and various interrupt sources and register addresses.
- The microcontroller is part of Atmel's MCS-51 family and is programmed using the MCS-51 instruction set with some restrictions due to its memory limits.
This document summarizes the expansion of a MicroBlaze system design to include additional peripherals:
- A VGA output peripheral is added to display text on a PC monitor with a resolution of 32 lines of 64 characters each, stored in 2kB of video memory.
- A LCD output peripheral is included for small on-board text display with a resolution of 2 lines of 16 characters each, stored in its own display buffer.
- A memory controller connects external 16-bit memory, including SRAM from 0x00800000-0x0087ffff and flash memory, to allow running code and storing data outside the FPGA's internal memory.
- Additional features allow running code and storing data
1. The ADEMCO 5828 and 5828V are wireless, bidirectional fixed-word keypads that can be used with LYNX and VISTA series residential alarm panels along with compatible transceivers.
2. The keypads operate on battery power when keys are pressed or AC power when connected to an adapter, displaying system status changes.
3. The 5828V adds voice announcements, a message center, and built-in microphone/speaker.
The document provides an introduction to the NanoBoard-3000 FPGA development board, outlining its key features such as the host and user FPGAs, memory resources, audio and video capabilities, and modular enclosure options. Details are given about the board's architecture, including its dual boot system, plug-in peripheral board support, and interfaces to connect to a PC and output video and audio. Resources and ordering information are provided for learning more about the NanoBoard-3000 development platform.
This document describes an assembler program that translates assembly language source code into machine-readable object code. The assembler outputs include an object file containing the translated object code, a program listing showing the source code and generated object code, and a symbol cross-reference listing. It also provides an overview of the 8080/8085 microprocessor architecture including memory, registers, flags, stack, I/O ports, and instruction set.
The document describes an 8-megabit serial flash memory chip. It has fast read/write speeds and low power consumption. The chip supports serial peripheral interface (SPI) communication and can individually erase sectors of 4KB or blocks of 64KB. It provides features such as write protection, read identification codes and status registers.
Wcdma Rno Handover Algorithm Analysis And Parameter Configurtaion Guidance 20...guest42b2673
The document analyzes WCDMA handover algorithms and parameters. It describes different types of handover measurements, including intra-frequency, inter-frequency, and inter-system measurements. It then explains soft handover, hard handover, and other handover algorithms. Finally, it provides guidance on setting various handover parameter values to optimize network performance based on factors like user movement speed.
Data Recovery Course
After years of doing data recovery for our inhouse service centre CHIPMENTOR, we have decided to start this data recovery course for all . Like our other courses , CHIPTRONIKS has designed an easy to learn data recovery course which will not only multiply the revenue of repairing engineers around the world but will also help them in meeting Customers requirement.
Our Data Recovery Course is hands-on practical course with focus on practical problems faced. Many companies tries to hide the way data is recovered, and like our other training , we believe we can make this country more advanced only if we share more ideas and knowledge. So we will unearth all the myths and the various tools used in data recovery business. Due to our innovatice training ,we have helped build strong laptop repairing community in India .
The document provides information about PROFIBUS-DP bus mapping for Siemens SIPROTEC protection devices 7SJ61-7SJ63, 7SJ65 and 6MD63, including:
- Four standard mappings (2-1 to 2-4) that define the data in PROFIBUS-DP messages between the devices and a master.
- Configuration data required for the standard mappings, including object numbers for commands, statuses and measured values.
- Notes on using SIPROTEC objects like commands, control mode, setting groups and errors.
- Details of messages in input and output directions, focusing on annunciations, measurements and metered values communicated via each standard mapping.
CHIPTRONIKS the best laptop repairing institute in Delhi with professional service center. We provide short term laptop, mobile tablet pc repairing course in Delhi at affordable price. Contact us for laptop repairing course.mobile repairing course'/> <meta>laptop repairing institute in Delhi,laptop repairing course in Delhi,laptop repairing institute,laptop repairing course,chip level laptop repairing institute in Delhi,chip level laptop repairing course in Delhi,mobile repairing institute in Delhi,mobile repairing course in Delhi,laptop repairing institute in India,tablet pc repairing institute in Delhi,aptop repairing institute in India,laptop institute India
CHIPTRONIKS the best laptop repairing institute in Delhi with professional service center. We provide short term laptop, mobile tablet pc repairing course in Delhi at affordable price. Contact us for laptop repairing course.mobile repairing course'/> <meta>laptop repairing institute in Delhi,laptop repairing course in Delhi,laptop repairing institute,laptop repairing course,chip level laptop repairing institute in Delhi,chip level laptop repairing course in Delhi,mobile repairing institute in Delhi,mobile repairing course in Delhi,laptop repairing institute in India,tablet pc repairing institute in Delhi,aptop repairing institute in India,laptop institute India
This document provides specifications for the connectors used on the LN_MULTIPILOT32 device, including pin assignments and meanings for LEDs, PWM and analog inputs and outputs, I2C interfaces, SPI interfaces, and more. Pin assignments are given for connectors related to functions like motor control, sensor inputs, analog measurement, and communications interfaces. The document is a revision from June 2011 and was authored by Diego Ambroggi.
The document provides an overview of the Nexys2 circuit board, which is a complete development platform based on a Xilinx Spartan 3E FPGA. The board includes a USB port for power and programming, 16MB of RAM and ROM, input/output devices, and expansion connectors. It can be programmed via the USB port using free software to load a bitstream into the FPGA or Platform Flash memory. The board also includes power supplies, clocks, and input/output devices to implement digital designs without additional components.
Este documento proporciona una introducción a WordPress, incluyendo cómo crear sitios web profesionales de forma gratuita y en continua evolución. Explica los elementos básicos necesarios como hosting, base de datos, e instalación en 5 minutos. También cubre temas personalizados, plugins y formas de añadir funcionalidad.
The document provides information about Intersoft Institute, an Indian training institute that offers IT and computer repair courses. It lists Intersoft's contact information and history since 1998, including starting mobile and laptop repair training programs. It then describes Intersoft's various computer repair, mobile repair, and other IT courses at both the basic and advanced levels, including modules on laptop hardware, motherboard chip-level repair, and BGA chip replacement. The document aims to provide students with an overview of Intersoft's course offerings and topics covered.
This document provides installation instructions for installing a SV-200MA Surveillance Board in VM-2120 or VM-2240 amplifiers. The SV-200MA adds monitoring, zone control, and backup amplifier functions. It consists of an SV-200M board and SV extension board. The 10 step installation process includes setting jumpers, connecting cables between the boards, mounting the surveillance board, and replacing the amplifier cover.
The document provides an overview and reference manual for the Basys 3 FPGA board from Digilent. Key points:
- The Basys 3 board features an Artix-7 FPGA, 16 user switches and LEDs, pushbuttons, 7-segment display, VGA output, USB and JTAG ports for programming.
- The FPGA can be programmed via the onboard JTAG circuitry using a USB cable, from a file on a SPI flash memory chip, or from a USB memory stick connected to the board.
- The board includes power supplies to support the FPGA and peripherals, which can be powered via USB or an external power source up to 5.5V.
The document discusses three different NSK products:
1. The 8051 Programmer connects via serial or parallel port and programs 8051 microcontrollers. It programs code, lock bits, erases, and verifies.
2. The PIC Programmer programs PIC microcontrollers via serial port and supports various PIC devices. It programs code, lock bits, erases, and verifies.
3. The USB PIC Programmer programs PICs via USB port with auto-programming mode. It programs code, lock bits, erases, verifies, and supports various PIC devices.
This document describes the AT89C2051 microcontroller. Key details include:
- It has 2K bytes of reprogrammable flash memory, 128 bytes of RAM, 15 I/O lines, and various timer/counter and communication features.
- Programming the flash memory involves applying the correct signals to ports to write bytes, erase the entire array, or read back data for verification.
- It has low power idle and power down modes for reduced power consumption and various interrupt sources and register addresses.
- The microcontroller is part of Atmel's MCS-51 family and is programmed using the MCS-51 instruction set with some restrictions due to its memory limits.
This document summarizes the expansion of a MicroBlaze system design to include additional peripherals:
- A VGA output peripheral is added to display text on a PC monitor with a resolution of 32 lines of 64 characters each, stored in 2kB of video memory.
- A LCD output peripheral is included for small on-board text display with a resolution of 2 lines of 16 characters each, stored in its own display buffer.
- A memory controller connects external 16-bit memory, including SRAM from 0x00800000-0x0087ffff and flash memory, to allow running code and storing data outside the FPGA's internal memory.
- Additional features allow running code and storing data
1. The ADEMCO 5828 and 5828V are wireless, bidirectional fixed-word keypads that can be used with LYNX and VISTA series residential alarm panels along with compatible transceivers.
2. The keypads operate on battery power when keys are pressed or AC power when connected to an adapter, displaying system status changes.
3. The 5828V adds voice announcements, a message center, and built-in microphone/speaker.
The document provides an introduction to the NanoBoard-3000 FPGA development board, outlining its key features such as the host and user FPGAs, memory resources, audio and video capabilities, and modular enclosure options. Details are given about the board's architecture, including its dual boot system, plug-in peripheral board support, and interfaces to connect to a PC and output video and audio. Resources and ordering information are provided for learning more about the NanoBoard-3000 development platform.
This document describes an assembler program that translates assembly language source code into machine-readable object code. The assembler outputs include an object file containing the translated object code, a program listing showing the source code and generated object code, and a symbol cross-reference listing. It also provides an overview of the 8080/8085 microprocessor architecture including memory, registers, flags, stack, I/O ports, and instruction set.
The document describes an 8-megabit serial flash memory chip. It has fast read/write speeds and low power consumption. The chip supports serial peripheral interface (SPI) communication and can individually erase sectors of 4KB or blocks of 64KB. It provides features such as write protection, read identification codes and status registers.
Wcdma Rno Handover Algorithm Analysis And Parameter Configurtaion Guidance 20...guest42b2673
The document analyzes WCDMA handover algorithms and parameters. It describes different types of handover measurements, including intra-frequency, inter-frequency, and inter-system measurements. It then explains soft handover, hard handover, and other handover algorithms. Finally, it provides guidance on setting various handover parameter values to optimize network performance based on factors like user movement speed.
Data Recovery Course
After years of doing data recovery for our inhouse service centre CHIPMENTOR, we have decided to start this data recovery course for all . Like our other courses , CHIPTRONIKS has designed an easy to learn data recovery course which will not only multiply the revenue of repairing engineers around the world but will also help them in meeting Customers requirement.
Our Data Recovery Course is hands-on practical course with focus on practical problems faced. Many companies tries to hide the way data is recovered, and like our other training , we believe we can make this country more advanced only if we share more ideas and knowledge. So we will unearth all the myths and the various tools used in data recovery business. Due to our innovatice training ,we have helped build strong laptop repairing community in India .
The document provides information about PROFIBUS-DP bus mapping for Siemens SIPROTEC protection devices 7SJ61-7SJ63, 7SJ65 and 6MD63, including:
- Four standard mappings (2-1 to 2-4) that define the data in PROFIBUS-DP messages between the devices and a master.
- Configuration data required for the standard mappings, including object numbers for commands, statuses and measured values.
- Notes on using SIPROTEC objects like commands, control mode, setting groups and errors.
- Details of messages in input and output directions, focusing on annunciations, measurements and metered values communicated via each standard mapping.
CHIPTRONIKS the best laptop repairing institute in Delhi with professional service center. We provide short term laptop, mobile tablet pc repairing course in Delhi at affordable price. Contact us for laptop repairing course.mobile repairing course'/> <meta>laptop repairing institute in Delhi,laptop repairing course in Delhi,laptop repairing institute,laptop repairing course,chip level laptop repairing institute in Delhi,chip level laptop repairing course in Delhi,mobile repairing institute in Delhi,mobile repairing course in Delhi,laptop repairing institute in India,tablet pc repairing institute in Delhi,aptop repairing institute in India,laptop institute India
CHIPTRONIKS the best laptop repairing institute in Delhi with professional service center. We provide short term laptop, mobile tablet pc repairing course in Delhi at affordable price. Contact us for laptop repairing course.mobile repairing course'/> <meta>laptop repairing institute in Delhi,laptop repairing course in Delhi,laptop repairing institute,laptop repairing course,chip level laptop repairing institute in Delhi,chip level laptop repairing course in Delhi,mobile repairing institute in Delhi,mobile repairing course in Delhi,laptop repairing institute in India,tablet pc repairing institute in Delhi,aptop repairing institute in India,laptop institute India
This document provides specifications for the connectors used on the LN_MULTIPILOT32 device, including pin assignments and meanings for LEDs, PWM and analog inputs and outputs, I2C interfaces, SPI interfaces, and more. Pin assignments are given for connectors related to functions like motor control, sensor inputs, analog measurement, and communications interfaces. The document is a revision from June 2011 and was authored by Diego Ambroggi.
The document provides an overview of the Nexys2 circuit board, which is a complete development platform based on a Xilinx Spartan 3E FPGA. The board includes a USB port for power and programming, 16MB of RAM and ROM, input/output devices, and expansion connectors. It can be programmed via the USB port using free software to load a bitstream into the FPGA or Platform Flash memory. The board also includes power supplies, clocks, and input/output devices to implement digital designs without additional components.
Este documento proporciona una introducción a WordPress, incluyendo cómo crear sitios web profesionales de forma gratuita y en continua evolución. Explica los elementos básicos necesarios como hosting, base de datos, e instalación en 5 minutos. También cubre temas personalizados, plugins y formas de añadir funcionalidad.
The document provides a detailed 9-day itinerary for a spiritual journey visiting 5 Takhts or holy Sikh shrines in India. Key stops include Takht Sri Patna Sahib, Anandpur Sahib, Amritsar, Bhatinda, and Nanded. The journey involves train travel between destinations and sightseeing in Delhi, Agra, Ellora Caves, and Mumbai. Cultural activities include visiting gurdwaras, attending prayer ceremonies and light shows, and enjoying langar meals at the Takhts.
The document provides highlights from a 2012 report on benchmarking single family offices (SFOs). It summarizes the findings of a 2011 survey of 106 SFOs from 24 countries conducted by the Wharton Global Family Alliance in partnership with IESE Business School. Some key findings include:
- Half of the SFOs surveyed were located in Europe, 41% in the Americas, and 8.5% in the rest of the world.
- Over 40% of the families served had over $1 billion in assets under management.
- More than half of the families were involved in operating businesses in addition to assets managed by their SFO.
- SFOs serving billionaires employed more staff on average
El documento describe cómo utilizar hojas de estilo CSS (Cascading Style Sheets) para redefinir el estilo de etiquetas HTML, incluyendo el uso de selectores de clase, identificadores y atributos STYLE. También explica conceptos como el modelo de caja, capas, posicionamiento y herramientas como Firebug para depurar hojas de estilo.
This document analyzes several magazine contents pages. It finds that effective contents pages establish the brand identity through logos. They attract audiences through multiple images of artists from different genres. Features are usually listed on the side with page numbers to help readers find content they like. Headlines stand out through size, color and font to catch readers' attention.
The document describes the flash programming process for EM35x chips used in production. It involves using flashloader firmware installed in RAM to program the flash memory. The key steps are:
1) Power up and halt the CPU to gain control.
2) Install and execute the flashloader firmware from a hex file using the serial wire interface.
3) The flashloader performs operations like erasing flash blocks and programming data from the hex file.
4) Final verification is done to ensure the programming was successful. Gang programming and serialization is also supported through the flashloader.
Hyponatremia in cirrhosis of liver indore pedicon 2014 Rajesh Kulkarni
This document discusses hyponatremia, or low sodium levels, in patients with cirrhosis of the liver. It defines hyponatremia as a serum sodium level below 130 mEq/L and identifies two types: hypovolemic, caused by fluid loss, and hypervolemic, caused by impaired renal fluid excretion leading to water retention. The management of hypervolemic hyponatremia involves increasing renal fluid excretion through dietary salt restriction, fluid restriction, and diuretic medications like spironolactone and furosemide. However, overuse of diuretics can cause complications like renal impairment and should be stopped if the sodium level drops too low or the cre
New BCG report on Global Wealth trends
Source:
https://www.bcgperspectives.com/content/articles/financial_institutions_business_unit_strategy_global_wealth_2014_riding_wave_growth
Nutritional refeeding syndrome kwashiorkar and marasmus indore pedicon 2014Rajesh Kulkarni
This document provides information on the management of severe acute malnutrition (SAM) in children, including refeeding syndrome. It describes a case of an 18-month-old boy admitted with SAM who deteriorated on the third day of treatment. It then discusses refeeding syndrome, its pathophysiology, clinical manifestations, and electrolyte deficiencies. Guidelines are provided for monitoring patients and correcting electrolyte abnormalities during nutritional rehabilitation. The document outlines protocols for the stabilization and rehabilitation phases of SAM treatment, including feeding amounts and micronutrient supplementation.
Hypokalemia and hyperkalemia indore pedicon 2014 finalRajesh Kulkarni
This document discusses two case studies of pediatric patients presenting with electrolyte abnormalities. Case 1 involves a 2-year-old boy named Rahul who was brought to the emergency department with diarrhea and dehydration. His lab work showed sodium of 131 mEq/L and potassium of 2 mEq/L, indicating hypokalemia. Case 2 involves a 7-year-old girl named Vinita who was admitted to the PICU for severe diabetic ketoacidosis. Her initial potassium was 4.4 mEq/L but the resident was concerned about potential hyperkalemia with further potassium supplementation. The document then reviews the causes, clinical manifestations, diagnosis, and management of hypo- and hyperkalemia in
This document discusses India's contributions to the treatment of diarrhea through oral rehydration therapy (ORT). It summarizes that ancient Indian physicians first described treating diarrhea with oral fluids over 2500 years ago. In the 1800s, IV fluids were used to treat cholera but ORT became standard by the 1900s. In the late 1950s-1970s, Indian doctors demonstrated that ORT with oral rehydration salts (ORS) could treat cholera with very low mortality rates. Subsequent research in India and elsewhere uncovered the sodium-glucose transport mechanism in the intestine that makes ORT effective. This led to recognition of ORT as a major medical advancement. The document discusses formulations of ORS and clinical cases demonstrating management of
The document discusses peripheral devices and the programmable peripheral interface (PPI) chip 8255A. It provides 3 key points:
1) The 8255A is a versatile chip used for parallel data transfer between a microprocessor and peripheral devices. It has 3 programmable I/O ports (Port A, B, and C) that can be independently programmed as input or output ports.
2) The 8255A can be programmed to operate in different modes like Mode 0 (simple I/O), Mode 1 (strobed mode), and Mode 2 (bidirectional bus mode) to interface with different types of I/O devices.
3) An 8-bit control register is used
The document provides specifications for the ESP32-PICO-D4 module, including an overview of its key components and features. It contains pin definitions, electrical characteristics, schematics and other technical details. Revision histories and important documentation are also referenced. The module integrates WiFi, Bluetooth, flash memory and other peripherals into a small package requiring minimal board space.
This document provides an overview of the PIC12C508 and PIC12C509 microcontrollers. It describes the key architectural features, including the Harvard architecture with separate program and data buses, 12-bit wide instructions, 8-bit ALU, and 33 single-cycle instructions. It also outlines the memory organization and peripherals, which include a real-time clock, watchdog timer, sleep mode, and programmable code protection. The document provides specifications for the memory sizes, operating voltage range, oscillator options, and packaging of the two microcontroller models.
HI-3220 ARINC 429 DATA MANAGEMENT ENGINE
16 x RECEIVERS, 8 x TRANSMITTERS, ADK-3220. Application Development Kit Users Guide and High Density 16Rx / 8Tx or 8Rx / 4Tx ARINC 429 HI-3220 datasheet.
This document provides an introduction to PIC microcontrollers. It discusses that PIC stands for "Programmable Intelligent Computer" and that a PIC microcontroller is a processor with built-in memory and RAM that can be used to control projects. It then lists some of the useful built-in modules of PIC microcontrollers like EEPROM, timers, and analog comparators. The document also discusses why PIC microcontrollers are popular, which includes their low cost, wide availability, and small size. It then provides details on the pins of the common PIC 16F84 microcontroller and describes its registers and peripherals. Finally, it gives a simple code example using ports on the PIC 16F84
This document provides information about the LMB162ABC LCD module from Shenzhen TOPWAY Technology Co., Ltd. including specifications, pinout functions, electrical characteristics, and display commands. The module uses a 16x2 character STN display with yellow-green LED backlight. It has basic functions for controlling display, cursor, and character generation.
The document discusses the PIC16F877 microcontroller. It provides details about its memory, packaging options, I/O pins and their special functions. Examples are given to illustrate using the microcontroller for an LED flasher, lockout system, musical tone generator, stepper motor controller and PWM motor speed control using interrupts. The examples cover digital I/O, timers, interrupts, ADC and USART communication.
IRJET- A Review Paper on Development of General Purpose Controller BoardIRJET Journal
This document provides a review of the development of a general purpose controller board. It describes the design and implementation of the controller board, which includes a microcontroller, analog sensors, communication capabilities, and a display. The controller board allows different applications by enabling communication between the microcontroller and connected devices. It provides a portable system for controlling, displaying, and manipulating inputs. The availability of various peripherals reduces complexity and cost. The controller board is programmed to perform tasks by running a set of instructions coded in the microcontroller. It provides a platform for real-time monitoring systems using sensors like a temperature sensor.
The document outlines the basic requirements for creating or changing a PLC program, including a PLC, programming device, programming software, and connector cable. It then provides details about the Siemens S7-200 PLC, including the different CPU models, features, and specifications. The S7-200 has a variety of CPUs and I/O options to provide a cost-effective automation solution. Programming is done using Siemens STEP 7 software on a programming device, which is then connected to the PLC via a cable.
FPGA Board (Xilinx Arty A7 -35 T) User Guide.pdfssuser6a66ac2
This document provides an overview and reference manual for the Arty FPGA board from Digilent. The Arty board features an Artix-7 FPGA from Xilinx that can be configured as a soft processing system using the MicroBlaze soft processor core. The board provides peripherals like DDR3 memory, flash memory, Ethernet, USB, LEDs, buttons, and expansion connectors. It also describes how the Arty can be programmed by designing soft processor systems in Vivado and writing C code in XSDK, or by using traditional FPGA design flows with HDL. The power system for the board is also outlined.
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K
bytes of In-System Programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the industry-
standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.
By combining a versatile 8-bit CPU with In-System Programmable Flash on
a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a
five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM contents
but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
8-bit
Microcontroller
with 4K Bytes
In-System
Programmable
Flash
AT89S51
2487D
The document describes the features of the ATmega328P microcontroller, including its AVR architecture, CPU, memory, I/O ports, analog-to-digital converter, timers, serial interfaces, and power saving modes. It has 32K bytes of flash memory, 1K bytes of EEPROM, 2K bytes of SRAM, and operates between 2.7-5.5 volts with speeds up to 16MHz. It provides various digital and analog features for interfacing with sensors and actuators.
The document describes the features of an AVR 8-bit microcontroller, including its RISC architecture, memory capabilities, I/O ports, timers, USB and peripheral features. It has 8/16/32KB of flash memory, 512/512/1024 bytes of EEPROM and SRAM, and 22 programmable I/O lines. It includes analog and digital features such as timers, USART, SPI and a USB controller.
This document describes a microcontroller-based password protected home appliance system. It contains an introduction, block diagram, flowchart, component descriptions, circuit diagram, and descriptions of hardware and software implementations. The system uses an ATmega8 microcontroller to control access to home appliances via a keypad password entry system. It allows authorized users to access appliances when the entered password matches the one stored in memory. The document also discusses objectives, components, programming, and conclusions regarding lessons learned and potential future modifications.
The document summarizes the benefits of adding a relay barrier between an in-system programmer and target system. A relay barrier increases flexibility by isolating the programmer lines during parametric and functional testing, only connecting them during programming. The document provides details on implementing a relay barrier with RNS's WriteNow in-system programmers, including connecting the barrier, powering options, and relay selection guidelines.
This document provides an overview of an embedded systems presentation. It discusses embedded training programs, products and services from EMBEX including training kits, development boards, and firmware development. It then covers topics related to embedded systems including microcontrollers, features of microcontrollers, software tools like Keil and Proteus, and example interfacing projects with LEDs, motors, and sensors. It concludes with discussing the presenter's line following robot project implemented using an 8051 microcontroller, IR sensors, motor drivers, and software simulation in Proteus.
The TramelBlaze Chip Specification document describes a system-on-chip (SOC) featuring a 16-bit processor, universal asynchronous receiver/transmitter (UART), and 8 pulse-width modulation (PWM) blocks. The SOC is designed to provide simple embedded control and includes blocks for the processor, UART, PWM controller, and reset synchronization. Verification confirmed basic UART transmission and PWM functionality as specified.
This document provides a summary of the features and specifications of the ATmega169P 8-bit microcontroller. It includes descriptions of the microcontroller's architecture, memory, I/O ports, peripherals, and electrical specifications. Key features include 16Kbytes of flash memory, 1Kbyte of SRAM, 512 bytes of EEPROM, 8-bit timers, PWM, ADC, SPI, and low-power sleep modes. The microcontroller is suitable for embedded applications requiring medium performance and low power consumption.
Similar to 120-5065-000_Production_Programming_of_EM35x_Chips (20)
Procrastination is a common challenge that many individuals face when it comes to completing tasks and achieving goals. It can hinder productivity and lead to feelings of stress and frustration.
However, with the right strategies and mindset, it is possible to overcome procrastination and increase productivity.
In this article, we will explore the causes of procrastination, how to recognize the signs of procrastination in oneself, and effective strategies for overcoming procrastination and boosting productivity.
Aggression - Applied Social Psychology - Psychology SuperNotesPsychoTech Services
A proprietary approach developed by bringing together the best of learning theories from Psychology, design principles from the world of visualization, and pedagogical methods from over a decade of training experience, that enables you to: Learn better, faster!
As we navigate through the ebbs and flows of life, it is natural to experience moments of low motivation and dwindling passion for our goals.
However, it is important to remember that this is a common hurdle that can be overcome with the right strategies in place.
In this guide, we will explore ways to rekindle the fire within you and stay motivated towards your aspirations.
ProSocial Behaviour - Applied Social Psychology - Psychology SuperNotesPsychoTech Services
A proprietary approach developed by bringing together the best of learning theories from Psychology, design principles from the world of visualization, and pedagogical methods from over a decade of training experience, that enables you to: Learn better, faster!
You may be stressed about revealing your cancer diagnosis to your child or children.
Children love stories and these often provide parents with a means of broaching tricky subjects and so the ‘The Secret Warrior’ book was especially written for CANSA TLC, by creative writer and social worker, Sally Ann Carter.
Find out more:
https://cansa.org.za/resources-to-help-share-a-parent-or-loved-ones-cancer-diagnosis-with-a-child/
Understanding of Self - Applied Social Psychology - Psychology SuperNotesPsychoTech Services
A proprietary approach developed by bringing together the best of learning theories from Psychology, design principles from the world of visualization, and pedagogical methods from over a decade of training experience, that enables you to: Learn better, faster!
1. Application Note
5065
2 July 2010
Production Programming of
120-5065-000A
EM35x Chips
This document describes the flash programming interface of EM35x chips, and is intended for
production programming of chips on a manufacturing line. The description assumes all chips
being programmed are new from the distributor and have never been programmed before,
but may still contain test code in the MFB. The process described in this document is
intended to program a final, fixed image and is not intended for use during application
development. This document also assumes the connection between the chip being
programmed and the programmer is reliable and error free.
Contents
Introduction .................................................................................................. 3
Pin Connections ............................................................................................. 3
Serial Wire and JTAG Interface ........................................................................... 5
Memory Organization ....................................................................................... 6
Flash ........................................................................................................ 6
RAM ......................................................................................................... 7
Description and Creation of Programming Image ...................................................... 7
File Format ................................................................................................ 7
Creation of a Programming Image ..................................................................... 8
Programming Overview ..................................................................................... 8
Programming Details ........................................................................................ 8
Power up and CPU Capture ............................................................................. 8
Install and Execute Flashloader Firmware ............................................................ 9
Disable Read/Write Protection ......................................................................... 9
Mass Erase MFB .......................................................................................... 10
Program MFB ............................................................................................. 10
Program CIB .............................................................................................. 10
Final Verification ........................................................................................ 10
Ember Corporation
Gang Programming ......................................................................................... 10
47 Farnsworth Street
Boston, MA 02210 Serialization ................................................................................................. 10
+1 (617) 951-0200
www.ember.com
2. ARM® CortexTM-M3 CPU Manipulation Details .......................................................... 11
Halting Core Reset ...................................................................................... 11
Stack Pointer Write ..................................................................................... 11
Program Counter Write ................................................................................. 11
Single Step ................................................................................................ 11
Run......................................................................................................... 11
Flashloader Firmware Timing ............................................................................ 11
Flashloader Firmware and Interface .................................................................... 12
3. Page 3
Introduction Production programming of flash on EM35x chips is accomplished using flashloader firmware.
The programmer communicates with the chip using the Serial Wire and JTAG Interface (SWJ).
The SWJ allows the programmer to read from any address and write to any RAM or register
address. The SWJ is used to install, execute, and communicate with the flashloader firmware
in RAM. The flashloader performs all of the flash manipulation operations using a simple set
of commands that operate on shared memory buffers. This application note focuses on the
use of the flashloader firmware to manipulate flash contents, how the flashloader should be
used in a production programming environment, and the issues surrounding flashloader use
including program image, gang programming, and serialization.
Pin Connections Table 1 lists all of the EM35x pins, their names, and their descriptions as they apply to
production programming. Refer to the EM35x Datasheet (120-035X-000) for further
information on the chip’s pins and all of their functionality.
Part orientation errors may be detected by monitoring VREG_OUT after the part is
released from reset during the Power up and CPU Capture step. Once nRESET is
released, the 1.8 V plane sourced by VREG_OUT on Pin 15 of the EM35x should
stabilize between 1.7 and 1.9 volts. If the voltage measured is outside of this range,
a wrong orientation error should be indicated.
Production Programming of EM35x Chips 120-5065-000A
4. Page 4
Table 1. Programming Pin Usage
EM35x Name Description
Pin
1 VDD_24MHZ 1.8 V supply
2 VDD_VCO 1.8 V supply
3 RF_P Not required for programming
4 RF_N Not required for programming
5 VDD_RF 1.8 V supply
6 RF_TX_ALT_P Not required for programming
7 RF_TX_ALT_N Not required for programming
8 VDD_IF 1.8 V supply
9 NC Do not connect
10 VDD_PADSA 1.8 V supply
11 PC5 Not required for programming
12 nRESET Active low chip reset (internal pull-up)
13 PC6 Not required for programming
14 PC7 Not required for programming
15 VREG_OUT Regulator output (1.8 V)
16 VDD_PADS 2.1-3.6 V pads supply
17 VDD_CORE 1.25 V digital core supply decoupling
18 PA7 Not required for programming
19 PB3 Not required for programming
20 PB4 Not required for programming
21 PA0 Not required for programming
22 PA1 Not required for programming
23 VDD_PADS 2.1-3.6 V pads supply
24 PA2 Not required for programming
25 PA3 Not required for programming
26 PA4 Not required for programming
27 PA5 Not required for programming
28 VDD_PADS 2.1-3.6 V pads supply
29 PA6 Not required for programming
30 PB1 Not required for programming
31 PB2 Not required for programming
32 SWCLK Serial Wire clock input/output with debugger
Selected when in Serial Wire mode (see JTMS description, Pin
35)
JTCK JTAG clock input from debugger
Selected when in JTAG mode (default mode, see JTMS
description, Pin 35)
Internal pull-down is enabled
33 JTDO JTAG data out to debugger
Selected when in JTAG mode (default mode, see JTMS
description, Pin 35)
Production Programming of EM35x Chips 120-5065-000A
5. Page 5
EM35x Name Description
Pin
34 JTDI JTAG data in from debugger
Selected when in JTAG mode (default mode, see JTMS
description, Pin 35)
Internal pull-up is enabled
35 JTMS JTAG mode select from debugger
Selected when in JTAG mode (default mode)
JTAG mode is enabled after power-up or by forcing nRESET
low
Select Serial Wire mode using the ARM-defined protocol
through a debugger
Internal pull-up is enabled
SWDIO Serial Wire bidirectional data to/from debugger
Enable Serial Wire mode (see JTMS description)
Select Serial Wire mode using the ARM-defined protocol
through a debugger
Internal pull-up is enabled
36 PB0 Not required for programming
37 VDD_PADS 2.1-3.6 V pads supply
38 PC1 Not required for programming
39 VDD_MEM 1.8 V supply
40 JRST JTAG reset input from debugger
Selected when in JTAG mode (default mode, see JTMS
description)
Internal pull-up is enabled
41 PB7 Not required for programming
42 PB6 Not required for programming
43 PB5 Not required for programming
44 VDD_CORE 1.25 V digital core supply decoupling
45 VDD_PRE 1.8 V supply
46 VDD_SYNTH 1.8 V supply
47 OSCB 24 MHz crystal oscillator or left open when using external
clock input on OSCA
48 OSCA 24 MHz crystal oscillator or external clock input. External
clock input is a 1.8 V square wave.
49 GND Ground supply pad in the bottom center of the package forms
Pin 49. See Ember’s various EM35x Reference Design
documentation for PCB considerations.
Serial Wire and The EM35x includes a standard Serial Wire and JTAG (SWJ) Interface. Serial Wire is an ARM®
JTAG Interface standard, bi-directional, two-wire protocol designed to replace JTAG, and provides all the
normal JTAG debug and test functionality. JTAG is a standard five-wire protocol providing
debug and test functionality. In addition, the two Serial Wire signals (SWDIO and SWCLK) are
overlaid on two of the JTAG signals (JTMS and JTCK). This keeps the design compact and
allows tools to switch between Serial Wire and JTAG as needed, without changing pin
connections. Therefore, a programmer interfacing with the EM35x may choose Serial Wire or
JTAG as desired.
Production Programming of EM35x Chips 120-5065-000A
6. Page 6
The key functionality that the SWJ provides is the ability to read and write 8, 16, and 32 bit
quantities to absolute memory addresses in the chip. The programmer uses standard memory
reads and writes to access a small selection of memory-mapped registers, as well as to load
and interact with the RAM-based flashloader. All memory reads and writes used during
production programming are 32 bit.
The details of the Serial Wire and JTAG protocols, as well as the debug port and access port
in the EM35x that implement the SWJ, are beyond the scope of this document. Since Serial
Wire and JTAG are standard protocols, they are described in other ARM® documents. For
further information on the SWJ, refer to the ARM® CoreSightTM Components Technical
Reference Manual (DDI 0314C). This document is available from ARM’s Infocenter website,
http://infocenter.arm.com, and Ember support.
Note: The maximum clock speed of the SWJ, as seen on the SWCLK/JTCK pin, is
2.5 MHz.
Memory This discussion on the EM35x flash and RAM organization is derived from the EM35x Datasheet
Organization (120-035X-000) and highlights specific aspects of the flash especially relevant to production
programming. Refer to the EM35x Datasheet (120-035X-000) for complete details of the flash
and RAM, including memory layout diagrams.
Flash
The EM35x flash memory is divided into three separate blocks:
• Main Flash Block (MFB) – The MFB is the largest block of flash and holds the executable
image being programmed into the device. The MFB begins at address 0x08000000. The
MFB on EM351 chips is 128 kB large; therefore the top of the MFB on EM351 chips is
0x0801FFFF. The MFB on EM357 chips is 192kB large; therefore the top of the MFB on
EM357 chips is 0x0802FFFF.
• Fixed Information Block (FIB) – The FIB stores manufacturing data that is fixed by Ember
during chip production and is not writable.
• Customer Information Block (CIB) – The CIB stores customer data that is not executable,
including manufacturing tokens. The first eight half-words of the CIB are dedicated to
special storage called option bytes. Option bytes are tied directly to certain chip
behavior including read protection and write protection of flash. The CIB is identical on
EM351 and EM357 chips and is 2 kB large. The bottom of the CIB is address 0x08040800
and the top is 0x08040FFF.
The flashloader executing on chip will validate the addresses being programmed and indicate
an invalid address error if the programmer attempts to modify invalid addresses. All
addresses are referred to as full 32 bit absolute addresses. The smallest writable unit of flash
is a half-word, 16 bits, and the smallest erasable unit of flash is a page, 2 kB. The erased
state of flash is 0xFFFF. Flash can be read in 8, 16, and 32 bit quantities.
While it is possible to erase the MFB one page at a time and therefore erase only a subset of
the MFB, it is recommended that production programming always starts by performing a mass
erase of the MFB. This ensures the MFB is put into a clean state and saves time, since the
mass erase takes the same amount of time as a single page erase.
Production Programming of EM35x Chips 120-5065-000A
7. Page 7
Note: Mass erase erases only the MFB, and erases the entire MFB.
The eight option bytes at the bottom of the CIB have special behavior that differs from all
other flash. The chip’s flash interface requires that each option byte be written with a
companion byte that is the inverse of the option byte. Therefore, a single option byte
requires writing a full 16 bit, structured quantity. One of the option bytes configures flash
read protection and two (EM351) or three (EM357) option bytes control flash write
protection. Refer to the EM35x Datasheet (120-035X-000) for complete details of the option
bytes.
Note: Because the option bytes configure flash read and write protection, special care
must be taken when manipulating the option bytes. Read and write protection, as
defined by the option bytes, is only updated when the nRESET pin is asserted and the
chip is reset. Therefore, it is valid to erase and write read and write protection and
then manipulate other flash as long as the nRESET pin is not asserted. Once read
protection or write protection is set and nRESET is asserted, no further flash read or
write operations should be attempted, except for disabling read or write protection (by
reprogramming the option bytes).
Note: Read protection is only disabled by writing the value 0xA5 to the read protection
byte. Any other value, including the erased state of 0xFF, will enable read protection.
Note: It is the programming image creator’s responsibility to ensure any option bytes
being programmed contain the correct inverse option byte value. If the inverse option
byte is not correct, the programming operation will fail verification.
RAM
The EM35x RAM memory exists as a single block of memory. The bottom of the RAM is address
0x20000000 and the top of the RAM is address 0x20002FFF. The flashloader s37 image file
does not define a value for every byte in the RAM, but does define an address and value for
every byte that must be programmed. Any byte in RAM that is not defined by the flashloader
s37 image file may be left in any state.
While RAM is executable, it does not execute out of reset. Therefore, one of the
programming steps defines how to capture the CPU and execute the flashloader after the
flashloader has been written into RAM.
Description and File Format
Creation of Production programming uses the standard Intel HEX-32 file format. The normal development
Programming process for EM35x chips involves creating and programming images using the Motorola S-
Image record file format, specifically the S37 file format. The s37 files are intended to hold
applications, bootloaders, manufacturing data, and other information to be programmed
during development. The s37 files, though, are not intended to hold a single image for an
entire chip. For example, it is often the case that there is an s37 file for the bootloader, an
s37 file for the application, and an s37 file for manufacturing data. Since production
programming is primarily about installing a single, complete image with all the necessary
code and information, the file format used is Intel HEX-32 format. While s37 and hex files are
functionally the same – they simply define addresses and the data to be placed at those
addresses – Ember has adopted the conceptual distinction that a single hex file contains a
single, complete image often derived from multiple s37 files.
Production Programming of EM35x Chips 120-5065-000A
8. Page 8
Since no special addressing or programming is used with EM35x chips, standard hex file
formats are used and can be interpreted without extra knowledge. All bytes in flash have
their own absolute 32 bit address. There is no strict requirement that a hex image defines
every byte to be programmed on a chip. If a byte must be programmed and is not defined by
the hex image, the byte should be programmed to the erased state, 0xFF. Any byte that is
not programmed will be left in the erased state, 0xFF, when programming is complete, due
to the fact that a mass erase is performed and the CIB is page erased. The only restriction is
that the smallest writable quantity is 16 bits. The addresses of any data provided to the
flashloader must be 16 bit aligned, and the data must be multiples of 16 bits.
Creation of a Programming Image
Programming images in the hex format are created from the standard em3xx_load.exe
development tool, which is part of the ISA3 Utilities. The ISA3 Utilities are part of the
EmberZNet 4.0 or later stack release. The em3xx_load.exe tool is very versatile and capable
of generating hex files from a variety of sources. The sources include multiple s37 files,
existing chips, and manual file patching operations. Ultimately, em3xx_load.exe allows the
developer to merge a variety of sources into a final hex image and modify individual bytes in
that image if necessary.
Programming The Programming Details section is organized in the general programming flow. The basic
Overview production programming flow is as follows:
1. Power up and CPU Capture
2. Install and Execute Flashloader Firmware
3. Disable Read/Write Protection
4. Power up and CPU Capture
5. Install and Execute Flashloader Firmware
6. Mass Erase MFB
7. Program MFB
8. Program CIB
9. Final Verification
If the Program CIB step enables read or write protection, the new protection setting will not
take effect until the chip is next reset by either asserting the nRESET pin or performing a
standard power-on-reset. Therefore, the programming flow does not have to worry about
flash protection because protection will not take effect until production programming has
completed.
Programming This section details all of the individual steps that comprise the complete production
Details programming process.
Note: The numerical values provided in these programming steps are values intrinsic to
the EM35x chip and will never change. The names in all capital letters are values tied to
a specific flashloader image and are defined in the header files that accompany the
flashloader s37 image file.
Power up and CPU Capture
1. Apply power while nRESET is held low.
2. Hold nRESET low and wait 10 µs after power has stabilized.
Production Programming of EM35x Chips 120-5065-000A
9. Page 9
3. Do not release nRESET less than 30 µs after asserting nRESET.
4. While nRESET is low, logically attach the programmer to the SWJ by setting the
CDBGPWRUPREQ and CSYSPWRUPREQ signals defined by ARM®.
5. Release nRESET and wait 100 µs.
6. Validate the SWJ communications path is operational by reading the Silicon ID at address
0x40004000 and verifying this value is 0x069A962B.
7. Perform a standard ARM® CortexTM-M3 CPU Halting Core Reset.
Install and Execute Flashloader Firmware
1. Write the value 0x00000307 to the address 0x40000018.
2. Write the entire flashloader firmware image to the chip’s RAM. The flashloader image is
a standard s37 file format indicating what bytes to write and the 32-bit absolute
addresses to write to in the memory map.
3. Read the flashloader firmware image from RAM to verify the flashloader is installed
properly.
4. Write the address of the bottom of RAM, 0x20000000, to the address 0xE000ED08.
5. Write the stack pointer value to the CPU’s stack pointer register, R13, using a standard
ARM® CortexTM-M3 CPU Stack Pointer Write. The stack pointer value is a literal, 32-bit
number named STACK_POINTER_INIT, and is defined with the flashloader image.
6. Write the program counter value to the CPU’s program counter register, R15, using a
standard ARM® CortexTM-M3 CPU Program Counter Write. The program counter value is a
literal, 32-bit number named PROGRAM_COUNTER_INIT, and is defined with the
flashloader image.
7. Perform a standard ARM® CortexTM-M3 CPU Single Step.
8. Using a CPU Stack Pointer Write, rewrite the stack pointer with the STACK_POINTER_INIT
literal.
9. Using a CPU Program Counter Write, rewrite the program counter with the
PROGRAM_COUNTER_INIT literal.
10. Clear the flashloader’s command and status shared memory by writing 0x00000000 to
SHAREDMEM_COMMAND and SHAREDMEM_STATUS, defined with the flashloader image.
11. Perform a standard ARM® CortexTM-M3 CPU Run.
12. Read from SHAREDMEM_COMMAND, until this address contains the value COMMAND_IDLE.
13. Read from SHAREDMEM_STATUS, until this address contains the value STATUS_BOOTED.
Disable Read/Write Protection
1. Initiate disabling of read protection by writing the value COMMAND_DISABLE_RDPROT to
SHAREDMEM_COMMAND. This inherently disables write protection as well.
2. Read from SHAREDMEM_COMMAND, until this address contains the value COMMAND_IDLE.
3. Read from SHAREDMEM_STATUS. If SHAREDMEM_STATUS does not contain the value
STATUS_SUCCESS, the operation failed and the chip should be recorded as failed.
4. Repeat the step Power up and CPU Capture.
5. Repeat the step Install and Execute Flashloader Firmware.
Production Programming of EM35x Chips 120-5065-000A
10. Page 10
Mass Erase MFB
1. Initiate a mass erase by writing the value COMMAND_MASS_ERASE to
SHAREDMEM_COMMAND.
2. Read from SHAREDMEM_COMMAND, until this address contains the value
COMMAND_IDLE.
3. Read from SHAREDMEM_STATUS. If SHAREDMEM_STATUS does not contain the value
STATUS_SUCCESS, the operation failed and the chip should be recorded as failed.
Program MFB
The target flash address must be 16 bit aligned. A minimum of 16 bits and a maximum of 2 kB
of data may be written in a single program command.
Loop over all MFB data, programming a block, at most 2kB, per program command:
1. Write the starting address for this block to SHAREDMEM_DATAADDRESS.
2. Write the data to be installed into flash to SHAREDMEM_DATABUFFER.
3. Write the size, in bytes, of the block of data to be programmed to
SHAREDMEM_DATALENGTH. This size must be a multiple of 16 bits.
4. Initiate a write operation by writing the value COMMAND_PAGE_WRITE to
SHAREDMEM_COMMAND.
5. Read from SHAREDMEM_COMMAND, until this address contains the value COMMAND_IDLE.
6. Read from SHAREDMEM_STATUS. If SHAREDMEM_STATUS does not contain the value
STATUS_SUCCESS, the operation failed and the chip should be recorded as failed.
Program CIB
Programming the CIB follows the same sequence of steps described in Program MFB.
Final Verification
After programming activities have completed, the programmer should directly readout all
MFB and CIB addresses and verify those addresses match the data in the source hex image.
Addresses not defined by the hex image should be verified as still being in the erased state,
0xFF.
At this point, production programming is complete.
Gang Because the production programming process described in this document relies on the SWJ
Programming interface and uses a lot of handshake style communication with the chip, it is impractical to
share GPIO between EM35x chips and drive multiple chips from a single controller. Because
the Serial Wire interface uses a single bidirectional data line for all communications, it is not
possible to tie the SWDIO pin from multiple chips together, and therefore each chip must be
controlled independently. It is possible to link multiple chips together in a standard JTAG
scan chain configuration and access memory on each chip individually. In theory, it might be
possible to tie the JTAG interface of multiple chips together, as long as the controller can
still access the JTDO pin of each chip individually. Ember has not attempted this mode of
operation, cannot say if it will or will not work, and cannot say if it is practical.
Serialization The EM35x comes pre-programmed with an EUI64 when shipped from the factory. This Ember
EUI64 exists in the FIB and is not modifiable. It may, however, be desirable for a customer to
override the default EUI64 with their own unique serial numbers for each chip, or set other
Production Programming of EM35x Chips 120-5065-000A
11. Page 11
per-chip unique manufacturing tokens. This can be done by customizing the CIB programming
so that the values to be written to flash are taken from some other source, such as a
database, in addition to the programming image.
Details of pre-defined manufacturing tokens in the CIB are available in Ember application
notes and HAL source header. Refer to Bringing Up Custom Devices for the EM35x SoC
Platform (120-5064-000), Setting Manufacturing Certificates and Installation Codes (120-5058-
000), and hal/micro/cortexm3/token-manufacturing.h. These documents are available from
Ember support.
ARM® CortexTM-M3 The following sections give an overview of the basic CPU manipulation necessary to
CPU Manipulation accomplish production programming. The CPU manipulation is standard CortexTM-M3
Details functionality. Refer to the ARM CortexTM-M3, r1p1, Technical Reference Manual (DDI 0337D)
for all the necessary details. Specifically, the Core Debug chapter and the Nested Vectored
Interrupt Controller chapter of the Technical Reference Manual describe the registers needed
and how to use them. This document is available from ARM’s Infocenter website,
http://infocenter.arm.com, and Ember support.
Halting Core Reset
While a pin reset – asserting nRESET – is used during powerup to reset the entire chip, this
type of reset leaves the CPU executing code. The purpose of the Halting Core Reset is to
reset the CPU and leave the CPU in a halted state at the reset vector so no code is executed.
The Debug Exception and Monitor Control Register provides a means of halting the running
system if a core reset occurs. The Application Interrupt Register provides a means of
resetting the system while the reset vector catch is enabled.
Stack Pointer Write
The Core Debug registers are used to write the Stack Pointer to a specific value.
Program Counter Write
The Core Debug registers are used to write the Program Counter to a specific value.
Single Step
The Core Debug registers are used to perform a single step of the CPU.
Run
The Core Debug registers are used to halt and run the CPU.
Flashloader Table 2 shows the timing of the flashloader commands. The timing was measured on-chip,
Firmware Timing from the moment the flashloader left the idle state, COMMAND_IDLE, until the flashloader
returned to the idle state.
Note: The timing of COMMAND_PAGE_WRITE is for the worst case scenario. The worst
case scenario is defined as writing a full 2 kB of data where all data is 0x0000.
Production Programming of EM35x Chips 120-5065-000A
12. Page 12
Table 2. Flashloader Firmware Timing
Flashloader command Execution time of command
COMMAND_MASS_ERASE 109 ms
COMMAND_PAGE_ERASE 21 ms
COMMAND_PAGE_WRITE 56 ms
COMMAND_DISABLE_RDPROT 21 ms
Flashloader The following are the three files that define the flashloader firmware and the interface with
Firmware and the firmware. While these three files are added to the document here, the latest versions are
Interface available to download from the developer support site.
• flashloader-cmd-stat.h defines the COMMAND and STATUS values used when interacting
with the flashloader.
• flashloader-em35x.h defines the memory addresses used when interacting with the
flashloader.
• flashloader-em35x.s37 is Motorola S-record file that defines the actual flashloader
firmware that is to be loaded into and executed from RAM.
The following is the flashloader-cmd-stat.h file:
/*
* Header file for flashloader-<micro>.[h|s37], defining the command
* and status values needed in order to interact with the flashloader.
*
*/
#ifndef __FLASHLOADER_CMD_STAT_H__
#define __FLASHLOADER_CMD_STAT_H__
#define COMMAND_IDLE 0xC0000001
#define COMMAND_PAGE_ERASE 0xC0000002
#define COMMAND_PAGE_WRITE 0xC0000003
#define COMMAND_DISABLE_RDPROT 0xC0000004
#define COMMAND_MASS_ERASE 0xC0000005
#define STATUS_BOOTED 0xA0000001
#define STATUS_INVALID_CMD 0xA0000002
#define STATUS_SUCCESS 0xA0000003
#define STATUS_BUSY 0xA0000004
#define STATUS_VERIFY_ERASE_FAIL 0xA0000005
#define STATUS_PROG_FAIL 0xA0000006
#define STATUS_VERIFY_PROG_FAIL 0xA0000007
#define STATUS_BAD_ADDR_OR_LEN 0xA0000008
#endif //__FLASHLOADER_CMD_STAT_H__
The following is the flashloader-em35x.h file:
/*
* Header file for flashloader-em35x.s37, defining the values
* needed in order to interface with this flashloader.
Production Programming of EM35x Chips 120-5065-000A
13. Page 13
*
* NOTE: This file is autogenerated. Do NOT edit this file directly.
*
*/
#ifndef __FLASHLOADER_SHAREDMEM_H__
#define __FLASHLOADER_SHAREDMEM_H__
#define CHIP_NAME "EM35X"
#define PROGRAM_COUNTER_INIT 0x20000220
#define STACK_POINTER_INIT 0x20000200
#define SHAREDMEM_COMMAND 0x200027f0
#define SHAREDMEM_DATAADDRESS 0x200027f8
#define SHAREDMEM_DATALENGTH 0x200027fc
#define SHAREDMEM_STATUS 0x200027f4
#define SHAREDMEM_DATABUFFER 0x20002800
#endif //__FLASHLOADER_SHAREDMEM_H__
The following is the flashloader-em35x.s37 file:
S0180000656D3378782D666C6173686C6F616465722E73333735
S315200002000002002021020020B5020020B5020020B5
S31520000210A70E010100000000000000000000000001
S31520000220084840F20731016007480849016072B664
S3152000023007480168490849000160064859210160BC
S3152000024000F00AB81800004008ED00E00002002087
S31520000250FCED00E00080004080B50C480C494FF0D2
S31520000260CD3200F021F80B480B490C4A03E050F838
S31520000270043B41F8043B9142F9D30948094900223D
S3152000028000F012F800F05EFA00BEFEE70000002043
S3152000029000020020F4080020EC270020F027002090
S315200002A0000000000000000001E040F8042B884216
S315200002B0FBD370470348002101604160024803498F
S315200002C0016070471C4000400CED00E00400FA0578
S315200002D0084809490160094A026041604260AE4906
S315200002E001220A604A68D207FCD58168C907FCD476
S315200002F0704700BF0480004023016745AB89EFCDDE
S3152000030010B50446FFF7E4FFA24A4FF40071DFF868
S31520000310BC05022C1BD1022353608368936083683B
S31520000320422050601068C007FCD4202010609A48F4
S315200003304468A407FCD40024046080205060DFF8C1
S3152000034000041468E40615D51021116010BD032C95
S315200003500DD14FF408735360DFF888350068DFF855
S315200003607845A04200D100214FF41870D9E7DFF874
S31520000370640510BD002201E0521C92B28A4205D2C9
S3152000038053F8044B14F1010FF6D010BDFCE070B504
S31520000390804A53684FF4007454604FF404755560D6
S315200003A0DFF8405505EB400001801568ED07FCD4C9
S315200003B0202515601568142635420DD010201060B2
S315200003C004201060744841688907FCD4002101602C
S315200003D080205060534870BD0078884211BFB648CF
S315200003E054605360DFF8E80470BD00002DE9F8433F
S315200003F0FFF76EFF674C40F201206060DFF8CC54B7
S31520000400AE680027DFF8C084DFF8C49402E0B61C8B
S31520000410781C87B26048E968B7EB510F33D2318830
S3152000042038F817209142F2D038F817104FF6FF729D
S315200004309142ECD07900AA688A18DFF8A8349A424B
S315200004400DD3AA6889181B4A914208D238F817108A
Production Programming of EM35x Chips 120-5065-000A
15. Page 15
S31520000820006F05D3401C884202D3FFF7DFFDF3E7B4
S315200008302C48874205D32248814205D2FFF7D6FDB0
S31520000840EAE71E488742E6D31E488142E3D20024C7
S3152000085002E0BF1C641CA4B2B4EB550F08D238F8D2
S3152000086014103846FFF7E0FE706070684845F0D0F7
S31520000870002400F039F88BDAFBE7FFF725FE03208A
S31520000880FFF73EFDFFF720FEC6F8049080E7FFF74E
S315200008904BFE7CE7FFF782FE7AE700BF1C80004014
S315200008A096070408FFFF0208010000C0010000A00F
S315200008B0040000A0020000C0001004080000040884
S315200008C0011004080108040800280020F027002051
S315200008D0030000A0020000A0040000C0EC270020B6
S315200008E0080000A00008040828F814A0641CB4F529
S30D200008F0806F7047FFFF01082D
S70520000221B7
After reading this If you have questions or require assistance with the procedures described in this document,
document contact Ember Customer Support. The Ember Customer Support portal provides a wide array
of hardware and software documentation such as FAQ’s, reference designs, user guides,
application notes, and the latest software available to download. To obtain support on all
Ember products and to gain access to the Ember Customer Support portal, visit
http://www.ember.com/support_index.html.
Production Programming of EM35x Chips 120-5065-000A