This document provides an overview of using the 16F87XA microcontroller's Master Synchronous Serial Port (MSSP) module in Serial Peripheral Interface (SPI) and Inter-Integrated Circuit (I2C) modes. It describes the module's configuration registers and how to set it up as a SPI or I2C master or slave. It also gives an example SPI program and discusses using the MSSP in I2C mode, highlighting the more complex configuration and signaling protocol required for I2C communication.
The SPI protocol uses only 2 pins for data transfer called SDI and SDO. It uses the SCLK pin to synchronize data transfer and the CE pin to initiate and terminate transfers. These 4 pins - SDI, SDO, SCLK, and CE - make up the SPI interface. SPI devices communicate serially one bit at a time over these pins.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
SPI (Serial Peripheral Interface) allows for high-speed synchronous serial communication between microcontrollers and peripheral devices. It uses three wires (MOSI, MISO, SCK) to transmit data serially from a master to a slave device. The master device generates a clock signal on SCK to synchronize data transfer. The SS pin is used to select a specific slave device when there are multiple slaves. Common applications of SPI include in-system programming of microcontrollers and communicating with sensors, memory, and other peripherals. An example shows how to use SPI to control LEDs on a slave microcontroller from a master using button inputs.
The SPI (Serial Peripheral Interface) is a synchronous serial communication protocol used for communication between devices. It uses a master-slave architecture with a single master device initiating data transfer. Key features include using separate clock and data lines, operating in full duplex mode, and allowing multiple slave devices through individual chip selects. It provides a lower pin count solution than parallel buses at the cost of slower communication speeds.
Join this video course on udemy . Click here :
https://www.udemy.com/course/mastering-microcontroller-with-peripheral-driver-development/?couponCode=SLIDESHARE
In this course, the code is developed such a way that, It can be ported to any MCU you have at your hand.
If you need any help in porting these codes to different MCUs you can always reach out to me!
The course is strictly not bound to any 1 type of MCU. So, if you already have any Development board which runs with ARM-Cortex M3/M4 processor,
then I recommend you to continue using it.
But if you don’t have any Development board, then check out the below Development boards.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals
The SPI protocol uses only 2 pins for data transfer called SDI and SDO. It uses the SCLK pin to synchronize data transfer and the CE pin to initiate and terminate transfers. These 4 pins - SDI, SDO, SCLK, and CE - make up the SPI interface. SPI devices communicate serially one bit at a time over these pins.
Serial Peripheral Interface (SPI) is an interface bus commonly used to send data between microcontrollers and small peripherals such as shift registers, sensors, and SD cards.
SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers.
It is a synchronous serial data link that operates in full duplex (signals carrying data go in both directions simultaneously).
Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously.
SPI (Serial Peripheral Interface) allows for high-speed synchronous serial communication between microcontrollers and peripheral devices. It uses three wires (MOSI, MISO, SCK) to transmit data serially from a master to a slave device. The master device generates a clock signal on SCK to synchronize data transfer. The SS pin is used to select a specific slave device when there are multiple slaves. Common applications of SPI include in-system programming of microcontrollers and communicating with sensors, memory, and other peripherals. An example shows how to use SPI to control LEDs on a slave microcontroller from a master using button inputs.
The SPI (Serial Peripheral Interface) is a synchronous serial communication protocol used for communication between devices. It uses a master-slave architecture with a single master device initiating data transfer. Key features include using separate clock and data lines, operating in full duplex mode, and allowing multiple slave devices through individual chip selects. It provides a lower pin count solution than parallel buses at the cost of slower communication speeds.
Join this video course on udemy . Click here :
https://www.udemy.com/course/mastering-microcontroller-with-peripheral-driver-development/?couponCode=SLIDESHARE
In this course, the code is developed such a way that, It can be ported to any MCU you have at your hand.
If you need any help in porting these codes to different MCUs you can always reach out to me!
The course is strictly not bound to any 1 type of MCU. So, if you already have any Development board which runs with ARM-Cortex M3/M4 processor,
then I recommend you to continue using it.
But if you don’t have any Development board, then check out the below Development boards.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
call for paper 2012, hard copy of journal, research paper publishing, where to publish research paper,
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals
its only for learning purpose for beginners who wants to understand this protocol.
Life is all about learning, hope u will enjoy in this my PPT.
for any suggestion your always welcome .
This document provides an overview of the Inter-Integrated Circuit (I2C) bus. It describes the key features and evolution of I2C buses, including their simplicity, flexibility, addressing schemes, and ability to support multiple masters. The document also details the I2C bus architecture, protocol for data communication including start/stop conditions and bit transfers, and how the Microchip Master Synchronous Serial Port module is used to implement I2C functionality.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
This document provides an overview of peripherals and interfacing using various communication protocols. It discusses the I2C bus protocol for accessing peripheral chips. It covers the operation of the I2C bus including start/stop bits and acknowledgement. It then summarizes the use of various peripherals that interface using I2C including EEPROM, analog to digital converters, LCDs, and sensors. It also covers serial communication protocols like UART and interfacing for devices like keyboards.
The document discusses the SPI protocol used in the LPC2148 microcontroller. It describes the SPI communication modes of master and slave. It explains the various SPI registers used for configuration - SPCCR for clock settings, SPCR for control settings like CPHA and CPOL, SPDR for data transfer, and SPSR for status. It provides steps for initialization and data transfer in both master and slave modes. The document also discusses factors like clock frequency, data length, and interrupt handling related to SPI communication using LPC2148.
The document describes the features and operating modes of the ARM7 LPC2148 I2C block. The I2C block can operate as a master, slave, or master/slave and supports bidirectional data transfer between devices. It describes the four basic operating modes: master transmitter, master receiver, slave receiver, and slave transmitter. Each mode follows a specific data transfer format with the transmission and acknowledgement of address and data bytes.
The document discusses the SPI (Serial Peripheral Interface) bus protocol. It describes SPI as a synchronous serial communication interface used for short-distance communication between a master and multiple slaves. Key points:
1) SPI uses separate clock and data lines to keep the master and slaves in sync for transmission. This eliminates issues with asynchronous protocols like UART having different clock speeds.
2) The master initiates communication by activating a slave's chip select line and generating the clock signal. It then sends and receives data on the MOSI and MISO lines respectively to/from the slave.
3) SPI allows full duplex high-speed communication without packet restrictions or unique slave addresses like in I2C. However,
The document discusses the features and architecture of the Spartan-II FPGA family from Xilinx. It offers densities from 15,000 to 200,000 logic gates and system performance up to 200 MHz. Key features include block RAM up to 56Kb, distributed RAM, 16 I/O standards, and four DLLs. The FPGA architecture consists of configurable logic blocks (CLBs) containing look-up tables, flip-flops, and logic, surrounded by input/output blocks (IOBs). It also includes block RAM columns and a routing architecture to interconnect the elements.
Raspberry Pi - Lecture 3 Embedded Communication ProtocolsMohamed Abdallah
The document discusses various embedded communication protocols. It begins by defining communication in embedded systems and examples of common protocols including UART, I2C, SPI, CAN and LIN. It then explains key concepts such as bit rate, baud rate, serial vs parallel communication and synchronous vs asynchronous communication. The document proceeds to provide detailed explanations of the UART, I2C and SPI protocols, including their frame formats, data validity rules, arbitration mechanisms and usage examples. It concludes by noting some key characteristics of each protocol.
The Objective of this Paper is to optimize the area of (Serial peripheral interface) SPI module. SPI is a inter and intra communication protocol used for communication and testing’s like BST. Its occupies space in Embedded industry for communication of devices like Microcontrollers, peripheral’s for example ADC’s, DAC’s, Memories etc. ll these devices have a SPI module on it which acts as a master or Slave. This module is consuming more Area, here we made a approach in order to reduce Area, which reduces Cost as well. Protocol is implemented in Structural Code Verilog, Simulated and Synthesized Using Xilinx9.1 on various families of FPGA. Finally whole design is mapped onto Vertex 5 FPGA.
AN INTEGRATED FOUR-PORT DC-DC CONVERTER-CEI0080Vivek Venugopal
This document proposes a novel four-port DC/DC converter topology for renewable energy applications. The proposed topology adds two switches and two diodes to a traditional half-bridge topology to interface two power sources, one bidirectional storage port, and one isolated load port. Zero-voltage switching is achieved for all four main switches. Three ports can be tightly regulated through independent duty cycles while the fourth is unregulated to maintain power balance. Experimental results confirm independent control over three processing paths with low component count and losses.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
The 8254 programmable interval timer consists of three independent 16-bit programmable counters that can each count in binary or BCD up to a maximum frequency of 10 MHz. This timer is useful for controlling real-time events in microprocessors. In personal computers, the timer generates an 18.2 Hz interrupt, refreshes DRAM memory, and provides timing to devices like speakers. Each counter has inputs and outputs to control counting. The 8254 has various modes to generate pulses, squares waves, and one-shots using the counters.
100 MHz High Speed SPI Master: Design, Implementation and Study on Limitation...rahulmonikasharma
SPI or Serial Peripheral Interface is among the fastest synchronous serial communication protocols used in embedded systems. High throughput and simplicity of SPI communication has made SPI protocol; a de facto standard. Designs based on FPGAs (Field Programmable Gate Arrays) enhance reusability, flexibility and faster prototyping of digital systems, especially serial buses, which are inevitable in almost all designs. This paper discusses the design and implementation of a 100 MHz High Speed SPI Master Core on FPGA. State machine approach is employed for the RTL (Register Transfer Level) design of the core. The paper also discusses the challenges and limitations of implementing such a high speed SPI bus in digital systems. The SPI Master Core was successfully implemented on Altera Cyclone III FPGA for a speed of 100 MHz.
This document provides information about the XPS 16550 UART, XPS Serial Peripheral Interface (SPI), XPS Timer/Counter, and associated tools. It describes the features and modules of each peripheral component, including diagrams of their top-level and detailed block designs. Key aspects like supported device families, register modules, and operating modes are summarized for each component.
The document discusses the PIC16F877 microcontroller. It provides details about its memory, packaging options, I/O pins and their special functions. Examples are given to illustrate using the microcontroller for an LED flasher, lockout system, musical tone generator, stepper motor controller and PWM motor speed control using interrupts. The examples cover digital I/O, timers, interrupts, ADC and USART communication.
its only for learning purpose for beginners who wants to understand this protocol.
Life is all about learning, hope u will enjoy in this my PPT.
for any suggestion your always welcome .
This document provides an overview of the Inter-Integrated Circuit (I2C) bus. It describes the key features and evolution of I2C buses, including their simplicity, flexibility, addressing schemes, and ability to support multiple masters. The document also details the I2C bus architecture, protocol for data communication including start/stop conditions and bit transfers, and how the Microchip Master Synchronous Serial Port module is used to implement I2C functionality.
Serial peripheral Interface - Embedded System ProtocolAditya Porwal
Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by micro-controllers for communicating with one or more peripheral devices quickly over short distances. It can also be used for communication between two micro-controllers.
This document provides an overview of peripherals and interfacing using various communication protocols. It discusses the I2C bus protocol for accessing peripheral chips. It covers the operation of the I2C bus including start/stop bits and acknowledgement. It then summarizes the use of various peripherals that interface using I2C including EEPROM, analog to digital converters, LCDs, and sensors. It also covers serial communication protocols like UART and interfacing for devices like keyboards.
The document discusses the SPI protocol used in the LPC2148 microcontroller. It describes the SPI communication modes of master and slave. It explains the various SPI registers used for configuration - SPCCR for clock settings, SPCR for control settings like CPHA and CPOL, SPDR for data transfer, and SPSR for status. It provides steps for initialization and data transfer in both master and slave modes. The document also discusses factors like clock frequency, data length, and interrupt handling related to SPI communication using LPC2148.
The document describes the features and operating modes of the ARM7 LPC2148 I2C block. The I2C block can operate as a master, slave, or master/slave and supports bidirectional data transfer between devices. It describes the four basic operating modes: master transmitter, master receiver, slave receiver, and slave transmitter. Each mode follows a specific data transfer format with the transmission and acknowledgement of address and data bytes.
The document discusses the SPI (Serial Peripheral Interface) bus protocol. It describes SPI as a synchronous serial communication interface used for short-distance communication between a master and multiple slaves. Key points:
1) SPI uses separate clock and data lines to keep the master and slaves in sync for transmission. This eliminates issues with asynchronous protocols like UART having different clock speeds.
2) The master initiates communication by activating a slave's chip select line and generating the clock signal. It then sends and receives data on the MOSI and MISO lines respectively to/from the slave.
3) SPI allows full duplex high-speed communication without packet restrictions or unique slave addresses like in I2C. However,
The document discusses the features and architecture of the Spartan-II FPGA family from Xilinx. It offers densities from 15,000 to 200,000 logic gates and system performance up to 200 MHz. Key features include block RAM up to 56Kb, distributed RAM, 16 I/O standards, and four DLLs. The FPGA architecture consists of configurable logic blocks (CLBs) containing look-up tables, flip-flops, and logic, surrounded by input/output blocks (IOBs). It also includes block RAM columns and a routing architecture to interconnect the elements.
Raspberry Pi - Lecture 3 Embedded Communication ProtocolsMohamed Abdallah
The document discusses various embedded communication protocols. It begins by defining communication in embedded systems and examples of common protocols including UART, I2C, SPI, CAN and LIN. It then explains key concepts such as bit rate, baud rate, serial vs parallel communication and synchronous vs asynchronous communication. The document proceeds to provide detailed explanations of the UART, I2C and SPI protocols, including their frame formats, data validity rules, arbitration mechanisms and usage examples. It concludes by noting some key characteristics of each protocol.
The Objective of this Paper is to optimize the area of (Serial peripheral interface) SPI module. SPI is a inter and intra communication protocol used for communication and testing’s like BST. Its occupies space in Embedded industry for communication of devices like Microcontrollers, peripheral’s for example ADC’s, DAC’s, Memories etc. ll these devices have a SPI module on it which acts as a master or Slave. This module is consuming more Area, here we made a approach in order to reduce Area, which reduces Cost as well. Protocol is implemented in Structural Code Verilog, Simulated and Synthesized Using Xilinx9.1 on various families of FPGA. Finally whole design is mapped onto Vertex 5 FPGA.
AN INTEGRATED FOUR-PORT DC-DC CONVERTER-CEI0080Vivek Venugopal
This document proposes a novel four-port DC/DC converter topology for renewable energy applications. The proposed topology adds two switches and two diodes to a traditional half-bridge topology to interface two power sources, one bidirectional storage port, and one isolated load port. Zero-voltage switching is achieved for all four main switches. Three ports can be tightly regulated through independent duty cycles while the fourth is unregulated to maintain power balance. Experimental results confirm independent control over three processing paths with low component count and losses.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
The 8254 programmable interval timer consists of three independent 16-bit programmable counters that can each count in binary or BCD up to a maximum frequency of 10 MHz. This timer is useful for controlling real-time events in microprocessors. In personal computers, the timer generates an 18.2 Hz interrupt, refreshes DRAM memory, and provides timing to devices like speakers. Each counter has inputs and outputs to control counting. The 8254 has various modes to generate pulses, squares waves, and one-shots using the counters.
100 MHz High Speed SPI Master: Design, Implementation and Study on Limitation...rahulmonikasharma
SPI or Serial Peripheral Interface is among the fastest synchronous serial communication protocols used in embedded systems. High throughput and simplicity of SPI communication has made SPI protocol; a de facto standard. Designs based on FPGAs (Field Programmable Gate Arrays) enhance reusability, flexibility and faster prototyping of digital systems, especially serial buses, which are inevitable in almost all designs. This paper discusses the design and implementation of a 100 MHz High Speed SPI Master Core on FPGA. State machine approach is employed for the RTL (Register Transfer Level) design of the core. The paper also discusses the challenges and limitations of implementing such a high speed SPI bus in digital systems. The SPI Master Core was successfully implemented on Altera Cyclone III FPGA for a speed of 100 MHz.
This document provides information about the XPS 16550 UART, XPS Serial Peripheral Interface (SPI), XPS Timer/Counter, and associated tools. It describes the features and modules of each peripheral component, including diagrams of their top-level and detailed block designs. Key aspects like supported device families, register modules, and operating modes are summarized for each component.
The document discusses the PIC16F877 microcontroller. It provides details about its memory, packaging options, I/O pins and their special functions. Examples are given to illustrate using the microcontroller for an LED flasher, lockout system, musical tone generator, stepper motor controller and PWM motor speed control using interrupts. The examples cover digital I/O, timers, interrupts, ADC and USART communication.
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2. Outline
• 10.3 The 16F87XA Master Synchronous Serial
Port module in SPI mode
– Master and Slave Mode
– Program Example
• I2C Synch. Serial Communication.
Dr. Gheith Abandah 2
3. 10.3 The 16F87XA Master Synchronous Serial
Port module in SPI mode
• The MSSP module is designed for synchronous
communication and can be configured as
– a simple synchronous port (called SPI mode) , or
– as an I2C port (Inter-Integrated Circuit).
• It has three SFRs dedicated to it, SSPCON1, SSPCON2 and
SSPSTAT, which can be found in the register file map diagram
of Figure 7.6.
• It also has a register for data transfer, SSPBUF, and is the
source of an interrupt, as seen in Figure 7.10.
• In this section we look at the module in SPI mode.
Dr. Gheith Abandah 3
4. Port Overview
• Figure 10.7 on next slide shows the MSSP configured as an
SPI port.
• It can be configured as master or slave, with a variety of clock
speeds if master.
• At the heart of the serial port is the shift register SSPSR. When clocked, it
transfers serial data to pin SDO (if the output buffer gate is enabled) and
transfers serial data in from pin SDI.
• If the port is set up as a slave, it will receive the clock from the system
master through pin SCK.
• If the port is set up as master, it will generate the clock, which now
outputs through the SCK pin. This clock is derived either from the internal
clock oscillator, or from Timer 2.
Dr. Gheith Abandah 4
5. Port Overview
• An important enhancement to our earlier simple serial port is
the addition of the buffer register SSPBUF.
• This holds a data byte on its way to or from the shift register,
and is actually the addressable register that the program
writes to or reads from.
• This makes the serial port much more flexible in use.
Dr. Gheith Abandah 5
6. The Master Synchronous Serial Port block diagram, in Serial
Peripheral interface
Dr. Gheith Abandah 6
7. Port Configuration
• The two SFRs that control the action of the port in
SPI mode are SSPCON1 and SSPSTAT.
• Their use differs somewhat between the SPI and I2C
modes.
• They are shown, when used in SPI mode, in Figures
10.8 and 10.9 respectively.
• In them there are bits to do the following:
– Enable and configure the port.
– Sett clock rate and clock characteristics.
– Manage data transfer and buffering.
Dr. Gheith Abandah 7
10. Port Configuration Cont.
• The port is enabled with bit 5 (SSPEN) of SSPCON1, and its
operating mode selected with the lower four bits of the same
register. It can be seen that these bits determine whether the port
is to work as master or slave.
• If in Master mode, four clock sources are available. As can be seen,
these are either the clock oscillator signal divided by 4, 16 or 64, or
the Timer 2 output
• If in Slave mode, the Slave Select input pin SS can be enabled,
through the four lower bits of SSPCON1. In this case, an external SS
signal can control the tristate buffer that drives the SDO pin and the
clock to the shift register.
– The SS input then effectively enables the serial port action and the
port can be used in a multi-node configuration
Dr. Gheith Abandah 10
11. Managing Data Transfer
• If the port is set as Master, a write to the buffer register
SSPBUF automatically starts a transfer, clocking out whatever
data has been loaded into SSPBUF and clocking in whatever
data is present at the SDI pin.
• On completion of eight clock cycles, the interrupt flag SSPIF is
set and data in the shift register SSPSR is automatically
transferred to the buffer SSPBUF.
• The SSPIF flag can be used as an interrupt to alert the CPU
that the transfer is complete.
• If there is a write to SSPBUF before the previous word has
been completely sent, then the write collision bit WCOL is set.
Dr. Gheith Abandah 11
12. Managing Data Transfer
• If it is set as Slave, then, when the SCK input starts switching,
the port clocks data into the SSPSR shift register through the
SDI pin. At the same time, data is clocked out of it from the
other end through the SDO pin. It is, of course, up to the
system designer to ensure that valid data is ready in the
SSPSR register and/or is available at the SDI input, according
to the requirement.
• When eight cycles are complete, the interrupt flag SSPIF is set
and, again, data in SSPSR is automatically transferred to the
buffer SSPBUF.
• If the previous byte has not been read from SSPBUF, then the
SSPOV bit is set, indicating a receive overflow.
Dr. Gheith Abandah 12
13. 10.4 A simple Serial Peripheral Interface example
• The program enables the Derbot microcontroller SPI
by writing to SSPCON1 (for reasons of backward
compatibility the Assembler Include File calls this
SSPCON) and sets it up as a master, with clock
frequency Fosc/16. Clock control bits SMP and CKE
are both set to zero here.
• Clock and data output pins are set up as outputs via
TRISC.
• The program then transmits two bytes in turn
repeatedly on the serial link, with a 40 ms delay in
between.
Dr. Gheith Abandah 13
15. Enhancing synchronous serial and the Inter-Integrated Circuit bus
• The Inter-Integrated Circuit (I2C) protocol was developed by Philips to
provide a serial communication standard to overcome some of the
shortcomings of Microwire or SPI.
• As its name suggests, it is meant to provide communication between ICs
within a single system.
• It is intended to be flexible and tolerant of different technologies and
speeds.
• Main Inter-Integrated Circuit features
• I2C is based on a master–slave relationship between nodes.
• The master controls all bus usage.
– Standard mode (with bit rate up to 100 kbps),
– Fast-mode (with bit rate to 400 kbps),
– Fast-mode Plus (with bit rate to 1 Mbps) and
– High-speed mode (with maximum bit rate of 3.4 Mbps).
Dr. Gheith Abandah 15
16. I2C
• The I2C bus uses only two lines for all interconnection, called
SDA (serial data) and SCL (serial clock).
• The output of each node connects to the bus using an Open
Drain or Open Collector output
• while the node input is through a standard logic buffer.
• The two interconnect lines each have a pull-up resistor.
• Both lines are bi-directional, but the SCL clock signal is always
generated by the current master.
• When no node is accessing the bus the Open Drain outputs
are all inactive and the lines idle at Logic 1.
Dr. Gheith Abandah 16
18. I2C Signal Chsts.
• The I2C protocol follows a very clear format for data transfer, as
shown in Figure 10.13.
• It is initiated by a Start condition, in which the SDA line is taken
low, while the SCL line stays high.
• It is terminated by a Stop condition, in which the SDA line goes
high while the clock is held high.
• The Start and Stop conditions are asserted by the current master,
as is the clock.
• Between the Start and the Stop, data is transferred in bytes.
• During this time, the SDA value can only change when SCL is low;
data must remain stable when the clock line is high. This allows
data transfer and Start or Stop to be distinguished.
• The first byte of any transfer contains address information.
• The standard allows for either a 7-bit address, within a single
byte, or a 10-bit address spread across two bytes.
Dr. Gheith Abandah 18
20. The Master Synchronous Serial Port configured for Inter-
Integrated Circuit
• In this case the SCL line is shared with bit 3 of Port C
and SDA with bit 4 of Port C.
• In I2C mode the port is significantly more complex
than when in SPI mode, and care needs to be taken
to understand it.
• The first indication of the increased complexity is
the whole extra control register, SSPCON2, needed
for I2Cmode.
Dr. Gheith Abandah 20
26. Ex p 305
• Program Example 10.2 runs on the Derbot AGVand applies the I2C port as a
master. The key SFR settings are Port C (where I2C port bits must be set as inputs),
SSPADD (which determines the clock frequency) and SSPCON1 (which determines
the overall setting).
• Equation (10.1) is used to determine the value for SSPADD. The detail of the
SSPCON1 setting should be explored by comparing it with the register details in
Figure 10.14.
• All major I2C actions in the program are undertaken with the use of subroutines
and it is instructive to look at these.
• The program starts, from comment ;send opening string, by transmitting the
character message ‘Derbot’ to the hand controller.
• This is done in a single multiple-byte message. First the address is sent, using
subroutine I2C send add.
Dr. Gheith Abandah 26