1) Simulate an 8-bit VHDL Adders circuit built using Integer Arithme.pdf

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1) Simulate an 8-bit VHDL Adders circuit built using Integer Arithmetic. 2) Simulate an 8-bit Adder/Subtractor circuit built using LPM. Solution 2)using LPM: LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY lpm ; USE lpm.lpm_components.all ; entity LPM_8bit_Add_Sub is PORT ( Cin : IN STD_LOGIC ; A, B : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Sum : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; end LPM_8bit_Add_Sub; architecture Behavioral of LPM_8bit_Add_Sub is begin instance: lpm_add_sub GENERIC MAP (LPM_WIDTH => 16) PORT MAP ( cin => Cin, dataa => A, datab => B, result => Sum, cout => Cout ) ; end Behavioral; 1)Integer Arithmetic: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Adder_int_8bit is Port ( A,B : in STD_LOGIC_VECTOR (7 downto 0); S : out STD_LOGIC_VECTOR (7 downto 0); Cout : out STD_LOGIC); end Adder_int_8bit; architecture Behavioral of Adder_int_8bit is signal A1,B1,S1: STD_LOGIC_VECTOR (8 downto 0); begin A1<=0&A; B1<=0&B; S1<=A1+B1; S<=S1(7 downto 0); Cout<=S1(8); end Behavioral;.

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end Adder_int_8bit;
architecture Behavioral of Adder_int_8bit is
signal A1,B1,S1: STD_LOGIC_VECTOR (8 downto 0);
begin
A1<=0&A;
B1<=0&B;
S1<=A1+B1;
S<=S1(7 downto 0);
Cout<=S1(8);
end Behavioral;

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