The document describes the opcode fetch cycle of the 8085 microprocessor. It contains a block diagram of the main components involved in the opcode fetch cycle, including the program counter, address latch, memory, and instruction register. It also includes a timing diagram that shows the clock signals and control signal timings during an opcode fetch cycle, such as the addressing of memory to retrieve the opcode. The opcode is then stored in the instruction register to be decoded by the microprocessor.

1. MICROPROCESSOR 8085
OPCODE FETCH CYCLE
LECTURE 4
PROF. SANDIP DAS

2. B C
D E
H L
Stack Pointer(SP)
Program
Counter(PC)
Incrementer/Dec
rementer
Address Latch
ADDRESS BUFFER DATA/ADDRESS
BUFFER
8 BIT INTERNAL DATA BUS
INSTRUCTIO
N REGISTER
INSTRUCTIO
N DECODER
TIMING AND CONROL UNIT
STATUS
FLAGS
ALU
TEMPORAR
Y REGISTER
ACCUMUL
A-TOR
INTERRUPT
CONTROL
SERIAL I/O
CONTROL
CLK
𝑅𝐷 𝑊𝑅 ALE 𝑆0 𝑆1
CONTROL SIGNALS
INTERRUPT
SIGNALS
𝑋1
𝑋2
𝐴8 − 𝐴15
𝐴𝐷0 − 𝐴𝐷7

3. OPCODE FETCH
OPERATION
B C
D E
H L
Stack Pointer(SP)
PC
Incrementer/Decr
ementer Address
Latch
ADDRESS BUFFER DATA/ADDRES
S BUFFER
8 BIT INTERNAL DATA BUS
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
TIMING AND CONROL UNIT
ALU
ACCUMUL
A-TOR
CLK
𝑅𝐷
𝑊𝑅 ALE 𝑆0 𝑆1
CONTROL SIGNALS
𝑋1
𝑋2
MAR MDR
AC
1A
DB
MEMORY
(8000)
(8000)
(8000)
(DB)
(DB)

4. STATUS SIGNALS
𝑺 𝟏 𝑺 𝟎 Operation
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
When 𝐼𝑂/ 𝑀=0, Microprocessor performs memory related operation
When 𝐼𝑂/ 𝑀=1, Microprocessor performs IO related operation

5. OPCODE FETCH CYCLE (TIMING DIAGRAM)
CLOCK
𝑇1 𝑇2 𝑇3 𝑇4
𝐴15- 𝐴8
𝐴𝐷0 − 𝐴𝐷7
ALE
𝐼𝑂/ 𝑀
𝑆1, 𝑆0
𝑅𝐷
HIGHER ORDER M
ADDRESS
LOWER
ORDER M
ADDRESS
OPCODE 𝐷0 − 𝐷7
UNSPECIFIE
D