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Architecture 8085
- 2. It is a program controlled semiconductor device, which fetches, decodes and executes instructions. The basic functional blocks of a microprocessor are Arithmetic & Logical unit, an array of registers and control unit.
- 3. Internally, the microprocessor is made up of 3 main units. • The Arithmetic/Logic Unit (ALU) • The Control Unit. • An array of registers for holding data while it is being manipulated.
- 5. • Memory stores information such as instructions and data in binary format (0 and 1). It provides this information to the microprocessor whenever it is needed. • Usually, there is a memory “sub-system” in a microprocessor- based system. This sub-system includes: The registers inside the microprocessor • Read Only Memory (ROM) • used to store information that does not change. • Random Access Memory (RAM) (also known as Read/Write Memory). • used to store information supplied by the user. Such as programs and data.
- 6. • 8-bit general purpose µp • Capable of addressing 64 k of memory • Has 40 pins • Requires +5 v power supply • Can operate with 3 MHz clock • 8085 upward compatible
- 7. • To execute a program, the microprocessor “reads” each instruction from memory, “interprets” it then “executes” it. • To use the right names for the cycles: • The microprocessor fetches each instruction, • decodes it, • Then executes it. • This sequence is continued until all instructions are performed.
- 9. Arithmetic & Logical Unit Registers Instruction decoder & Machine cycle encoder Address Buffer Address/Data Buffer Incrementer/ Decrementer address Latch Interrupt Control Serial I/O control Timing And control Circuitry
- 11. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 12. It is the basic unit of the microprocessor and it performs arithmetic & Logical Functions on 8 bit variables. – Arithmetic Operations: • Every microprocessor has arithmetic operations such as add and subtract as part of its instruction set. – Logic Operations: • In addition, microprocessors have logic operations as well. Such as AND, OR, XOR, shift left, shift right, etc. Note: the number and types of operations define the microprocessor’s instruction set and depends on the specific microprocessor.
- 13. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 14. Temporary Register Temporary Data Register Temporary Register pair (W & Z) Special Purpose Register Accumulator (A Reg.) Flag register Instruction Register Sixteen bit Register Program Counter Stack Pointer
- 16. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 17. A B C D H E L F There are 2- 16 Bit Register: PROGRAM COUNTER STACK POINTER Special Purpose register 8 Bit Register General Purpose Register 8 Bit Register IR
- 18. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 B Register – 8 bit C Register – 8 bit D Register – 8 bit E Register– 8 bit H Register– 8 bit L Register– 8 bit Scratch Pad Registers : Functions as data pointer or memory pointer
- 19. Temporary Data Register W & Z Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Temporary Data Register – 8 bit W Register– 8 bit Z Register– 8 bit
- 20. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 21. Accumulator Flag register Instruction Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 S Z X AC X P X CY 7 6 5 4 3 2 1 0 Accumulator (A Register – 8 bit) Flag Register– 8 bit Instruction Register– 8 bit Used to hold the opcode of an instruction at the time of Execution
- 22. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 24. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 26. S Sign Flag Z Zero Flag AC Auxiliary Carry Flag P Parity Flag CY Carry Flag X Undefined
- 28. Program Counter (PC) Stack Pointer (SP) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Program Counter ( Register – 16 bit) Stack Pointer (Register– 16 bit) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 •Used to hold the address of the top of stack •Stack is the sequence of RAM memory locations
- 29. Program Counter (PC) • This is a register that is used to control the sequencing of the execution of instructions. • This register always holds the address of the next instruction. • Since it holds an address, it must be 16 bits wide. Stack pointer (SP) • The stack pointer is also a 16-bit register that is used to point into memory. • The memory this register points to is a special area called the stack. • The stack is an area of memory used to hold data that will be retrieved soon. • The stack is usually accessed in a Last In First Out (LIFO) fashion.
- 30. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 31. General Purpose Register Temporary Register Temporary Data Register W & Z Register Special Purpose Register Accumulator Flag register Instruction Register Sixteen bit Register Program Counter Stack Pointer
- 32. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 33. • Instruction Register • Instruction is stored in IR after fetched by processor • It decodes and accordingly gives the Timing and control signals which controls • The register • Data buffers • ALU • External Peripheral signals • Decoder • Decoder decodes instruction in IR
- 34. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)
- 35. There are 4 main control and status signals. These are: • ALE: Address Latch Enable. This signal is a pulse that become 1 when the AD0 – AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines. • RD: Read Active low. • WR: Write Active low. • IO/M: This signal specifies whether the operation is a memory operation (IO/M=0) or an I/O operation (IO/M=1). • S1 and S0 : Status signals to specify the kind of operation being performed. Usually un-used in small systems. Control bus is used to carry various control and status signals like 𝑅𝐷, 𝑊𝑅, ALE, READY, HLDA etc.
- 36. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS ACCUMALATOR(A-REG) TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND
- 37. – Address Bus • Unidirectional • Identifying peripheral or memory location – Data Bus • Bidirectional • Transferring data – Control Bus • Synchronization signals • Timing signals • Control signal
- 38. • An 8-bit internal data bus carries instructions and data between the CPU registers. • The external buses are the ones connected to other chips like memory, I/O and so on. • The 8085 transfers data on an 8-bit bi-directional 3-state bus (AD0-7) which is time-multiplexed and also it transmit with the eight lower-order address bits. • The main reason for multiplexing the AD0-7 buses was to retain the number of pin on the chip to 40. • An additional eight lines (A8-15) expand the 8085 family system memory addressing capability to 16 bits, thereby allowing 64K bytes of memory to be addressed directly by the CPU.
- 39. • The address bus has 8 signal lines A8 – A15 which are unidirectional. • The other 8 address bits are multiplexed (time shared) with the 8 data bits. • So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the same time. • During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. • In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes.
- 40. • From the above description, it becomes obvious that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. • The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. • To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7– AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.
- 41. • Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines.
- 42. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS ACCUMALATOR(A-REG) TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND
- 44. W-REG Z -REG INTERRUPT CONTROL SERIAL I/O CONTROL 8-BIT INTERNAL DATA BUS TEMP FLAG-REG (FLIP-FLOPS) INSTRUCTION REGISTER B-REG C-REG D-REG E-REG H-REG L-REG STACK POINTER PROGARM COUNTER INCREMETER/DECREMENTER ADDRESS LATCH ADDRESS/DATA BUFFER ADDRESS BUFFER INSTRUCTION DECODER & MACHINE CYCLE ENCODING TIMING AND CONTROL UNIT CLOCK GENERATOR CONTROL STATUS DMA RESET ARITHMETIC & LOGIC UNIT (ALU) POWER SUPPLY TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA SODSID X1 X2 +5V CLK OUT READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A15-A8 ADDRESS BUS AD7-AD0 ADDRESS / DATA BUS GND ACCUMALATOR(A-REG)