Vending machine

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ELE5FDD
FDD Assignment
Design and Synthesize a Vending Machine Prototype
BY
SAMARTH ANNAPPA SWAMY
18378408
LAV VISHNUBHAI PATEL
18398435

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CONTENTS
VENDING MACHINES AND ITS HISTORY 3
DESIGN METHODOLOGY OF VENDING MACHINE 4
BLOCK DIAGRAM 7
IMPLEMENTATION 7
STATE DIAGRAM 9
VHDL CODE 10
ADVANTAGES AND DISADVANTAGES 25
SIMULATION AND RESULTS 26
CONCLUSION 30
REFERENCES 31

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INTRODUCTION
Vending machines are quite popular from back 1880’s for dispensing coffee, snacks, cold
drinks etc. First vending machine was introduced and designed in London and England, which
was used for selling post cards. These are accessible and highly practical than the traditional
purchasing method. Nowadays it can be found everywhere in bus stations and railway stations
selling tickets, in schools and offices vending drinks and snacks, in banks as ATM machines.
Earlier CMOS based machines were used but they were more time consuming and little high
in maintenance. But once FPGA started being used which is quite flexible and re-
programmable. Nowadays we are getting vending machines based on Finite state machines
which supports cancel features too, when it’s done it returns all the money, it reduces cost and
time.
VENDING MACHINES AND ITS HISTORY
Vending machine was invented in late 215 B.C by a mathematician Hero, he designed a
vending machine which accepted bronze coins for dispensing holy water in temples of
Alexandria.
In AD 1076, a coin operated pencil vendor invented by Chinese, then in late 1700 tobacco
boxes were dispensed in English taverns.
United States started granting more funds for vending machines during 1896, but came into
real market in late 1888. Adams Gum Company dispensed a tutti-fruity for a single penny.
During 1926, William Rowe invented a vending machine which dispensed cigarettes which
started a merchandise including soft drinks and nickel candy machines that emerged during
1920-30’s.Coffee vendors were developed during 1946.
Now practically anything can be vended one at a time or another, beverage vending started
dated 1890 in Paris, France offered Beer, wine and liquor. Now items dispense clothing,
flowers, milk, cigars, live bait, flowers, postage stamps, lottery tickets, CD’s. Nowadays they
are dispensing pizza, pop-corn and French fries too [1].

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DESIGN METHODOLOGYOF VENDING MACHINE.
Figure 1a. Figure 1b.
1a. Dr Pepper vending machine© [3]
1b. Coca cola vending machine© [4]
A state machine is a device which can store the status of the information at a given time and
could operate on input to change the status at for any given change. For example we could
take a computer which is basically a state machine and each instruction (machine
instructions) is input which changes one or more states causing other actions to take place [2].
Finite state machines or state machine can be designed in two ways.

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Mealy State machine
Figure 1.2a: Simple Mealy FSM Asynchronous © [6]
Figure 1.2b: Simple Mealy FSM Synchronous © [7]
These are the Sequential systems where output depends on current input and state. A state can
be a register or a flip flop. For example counters.

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Moore State machine
Figure 1.3a: Simple Moore FSM Asynchronous ©[6]
Figure 1.3b: Simple Moore FSM Synchronous © [7]
These are the Sequential systems where output depends only on
current state. For example Traffic light controller

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BLOCK DIAGRAM
INPUT
DESIGN LOGIC
OUTPUT
CLK
RESET
PRODUCT
[4:0]
CONFIRM
CANCEL
RESP
SID
HEX
[6:0]
REPEAT
_INSERT
EXACT
_PAYMENT
DISPENSE
RETURN
_COINS
Figure 1.4: Top level of the vending machine
IMPLEMENTATION
Binary Representation
(Sw9-sw7)
Product ID Cost in Dollars
000 Product 1 0.70
001 Product 2 1.20
010 Product 3 2.00
011 Product 4 2.70
100 Product 5 3.20
101 Product 6 6.10
110 Product 7 8.90
111 Product 8 10.60
Table 1.1: Product numbers in binary representation
Binary Representation
Of price of the product
Product ID Cost in Dollars
0000000011000000 Product 1 0.70
0000000100100000 Product 2 1.20
0000001000000000 Product 3 2.00
0000001011000000 Product 4 2.70
0000001100100000 Product 5 3.20
0000011000010000 Product 6 6.10
0000011110010000 Product 7 8.90
0001000001100000 Product 8 10.60
Table 1.2: Product Price in binary representation

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FLOWCHART:
Figure 1.5: Flowchart of the complete vending machine

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STATE DIAGRAM
Figure
Figure 1.6: State diagram for vending machine for coin entry and change.
State diagrams are very useful for designing the state machines and especially for the vending
machines where it goes to so many states and evolves around it, doing many calculation
while returning coin as well as inserting coin.
After a product is confirmed it goes to price state when coin sel =1 and checks for the price
for the particular product when it becomes 0 it goes to pay state when user needs to pay the
money, if he has put more money than it goes to coin repository state where it checks for the
change, if it has it starts calculating for the change at 50 cents state, 10 cents, 20 cents, 1
dollar, likewise, once everything is sorted out it dispenses the product.
If the user doesn’t want that particular product then he has to press cancel which takes the
vending machine to initial state, else he has put some money then it should provide all the
money back.
When giving change, we have designed to display leds how much change is being dispenced
by beep half sec and one sec , it’s just shows us how many coins are being dispensed , only
one then only one beep for 1 sec if two coins the half second.

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VHDL CODE
-----------------------------------------------------------TOPMODULE-------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top_module is port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Product : in STD_LOGIC_VECTOR (2 downto 0); --(SW9-SW7)
Ent_coin : in STD_LOGIC_VECTOR (4 downto 0);--(SW4-SW0)
confirm : in STD_LOGIC; --(Key3)
Cancel : in STD_LOGIC; --(Key1)
resp: in std_logic; --(SW6)
SID: in std_logic; --(SW5)
Repeat_insert: out std_logic; --(R4)
exact_payment:out std_logic; --(R5)
Hex1: out std_logic_vector(6 downto 0):="0111111";
Dispense : out STD_LOGIC_VECTOR (3 downto 0); --(R9-R6)
Return_coins : out STD_LOGIC_VECTOR (3 downto 0) --(R3-R0)
);
end top_module;
architecture Behavioral of top_module is
signal pr: integer;
signal hd: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(3 downto 0);
signal ac: std_logic;
signal dt: std_logic_vector(23 downto 0);-- seven seg
signal ds: std_logic_vector(1 downto 0);
signal pn: std_logic_vector(3 downto 0);
component main_1 is
port(
clk : in STD_LOGIC;---------------------------------------------50 M clk
reset : in STD_LOGIC; ---------------------------------------sync reset
confirm : in STD_LOGIC; ----------------------(Key3)
Cancel : in STD_LOGIC; -----------------------(Key1)
resp: in std_logic; ---------------------------(SW6)
SID: in std_logic;
dis_sid: out std_logic_vector(1 downto 0);
exact_payment:out std_logic; --(R5
price_t: out integer; --(hex 4-1) -----------------------------S BCD
P_C: out std_logic_vector(3 downto 0);--(Hex5)-----------------S VGA
prod_num_t: out std_logic_vector(3 downto 0);--(Hex6)----------S VGA
active: out std_logic; -- activate signal
Return_coins : out STD_LOGIC_VECTOR (3 downto 0)); --(LED)

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end component;
component BCD is
port(
clk : in STD_LOGIC;
active: in std_logic;
price : in integer; ----------------------------------S main_1
hexdata : out STD_LOGIC_VECTOR (15 downto 0) ---------S VGA
);
end component;
component ver2_2 is
port(
clk : in STD_LOGIC;
price:in std_logic_vector(15 downto 0);
dis_sid: in std_logic_vector(1 downto 0);
P_C : in std_logic_vector(3 downto 0);
prod_num_t :in std_logic_vector(3 downto 0);
Hex6: out std_logic_vector(6 downto 0):="0111111"
);
end component;
begin
comp1: main_1
port map (
clk => clk,
reset => reset,
Product => Product,
Ent_coin => Ent_coin,
SID => SID,
dis_sid=> ds,
resp => resp,
Confirm => Confirm,
Cancel => Cancel,
Repeat_insert => Repeat_insert,
exact_payment=>exact_payment,
price_t => pr,---BCD S
P_C => pc,
prod_num_t => pn,
active => ac,
Dispense => Dispense,
Return_coins => Return_coins
);
comp2: BCD
port map(
clk => clk,
reset => reset,
price => pr,
active => ac,
hexdata => hd
);

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comp3: ver2_2
port map(
clk => clk,
reset => reset,
active => ac,
dis_sid => ds,
P_C => pc,
Hex1 => Hex1,
Hex2 => Hex2,
Hex3 => Hex3,
Hex4 => Hex4,
Hex5 => Hex5,
Hex6 => Hex6,
prod_num_t => pn,
price => hd
);
end Behavioral;
-------------------------------Main Module--------------------
library IEEE;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_signed.ALL;
use IEEE.numeric_std.ALL;
entity main_1 is
Port ( clk : in STD_LOGIC;
confirm : in STD_LOGIC; --(Key3)
Cancel : in STD_LOGIC; --(Key1)
resp: in std_logic;
SID: in std_logic;
dis_sid: out std_logic_vector(1 downto 0);
exact_payment:out std_logic; --(R5)
price_t: out integer; --(hex 4-1)
P_C: out std_logic_vector(3 downto 0);--(Hex5)
prod_num_t: out std_logic_vector(3 downto 0);--(Hex6)
active: out std_logic;
Return_coins : out STD_LOGIC_VECTOR (3 downto 0)); --()
end main_1;
architecture Behavioral of main_1 is
--------------------- product->price list--------------
signal n1,n2,n3,n4:integer :=0;
--signal product_temp: std_logic_vector(2 downto 0) := (others => '0');
-------------------XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX------
--signal Return_coins: std_logic_vector(3 downto 0);
---------------------HEX display-------------------------
signal price, price_ret, price_temp1: integer range 0 to 1500 ;
signal price_temp2: integer range -1500 to 1500;
signal prod_num: std_logic_vector(3 downto 0);
signal coin: integer range 0 to 200 := 0;
signal coin_sel: std_logic :='0';
signal ret_change: std_logic_vector(7 downto 0):= (others => '0');
------------------------ FSM --------------------------
type state_names is (intzn, zero, sel_updt, pay_st1, pay_st2, pay_st3, change,
chk_rsp, repeat, dspns, return_coins1,
return_coins050, return_coins020, return_coins010,
beep_onsec, beep_halfsec, stay);

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signal state, state_return: state_names;
------------------------ change resipository-----------
--signal c0100: std_logic_vector(9 downto 0) := (others => '1');
signal n0100: integer range 0 to 9:=0;
signal nt100: integer range 0 to 9:=0;
------------------------one_second_window-----------------
signal onsec: integer:=0;
signal clkt,clk20k : std_logic;
signal cnt20k: integer range 0 to 50000;
begin
clk20kHz: process(clk,reset)
begin
if reset = '0' then
clkt <= '0'; cnt20k <= 0; -- reset values
elsif rising_edge(clk) then
if cnt20k < 50000 then -- to avoid 2 ms key debounce
cnt20k <= cnt20k + 1; -- counts up until it reaches 25000
else
clkt <= not clkt; -- clk1k inverts itself every 25000 counts
cnt20k <= 0;
end if;
end if;
end process;
clk20k <= clkt;
price_t <= price_temp1;
--with product_temp select
--price <= "0000000011000000" when "000", --$00.70
-- "0000000100100000" when "001", --$01.20
-- "0000001000000000" when "010", --$02.00
-- "0000001011000000" when "011", --$02.70
-- "0000001100100000" when "100", --$03.20
-- "0000011000010000" when "101", --$06.10
-- "0000011110010000" when "110", --$08.90
-- "0001000001100000" when "111", --$10.60
-- "0000000000000000" when others;
----------------------------Price--------------------------------
price <= 70 when ( Product = "000") else --$00.70
120 when ( Product = "001") else --$01.20

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1060 when ( Product = "111"); --$10.60
----------------------------display product number --------------
prod_num <= "0001" when ( Product = "000") else --1
"0010" when ( Product = "001") else --2
"1000" when ( Product = "111"); --8
---------------------------payment input ---------------------------
coin <= 200 when ( Ent_coin = "10000") else --$02.00
100 when ( Ent_coin = "01000") else --$01.00
0;
coin_sel <= Ent_coin(4) or Ent_coin(3) or Ent_coin(2) or Ent_coin(1) or
Ent_coin(0);
exact_payment <= '0' when resp = '1' else
'1';
process(clkt,reset)
variable ret: std_logic_vector(7 downto 0):=(others => '0');
begin
if reset = '0' then
--HEX_data <= (others => '0');
-- Dispense <= (others => '0');
Return_coins <= (others => '0');
state <= intzn;
elsif rising_edge(clkt) then
if SID = '1' then
if confirm = '0' then
-- Return_coins <= "1010";
dis_sid <= "10"; -- display 1st student id
else
-- Return_coins <= "0101";
dis_sid <= "01"; -- display second student id
end if;
else
dis_sid <="00";
case state is
when intzn =>
Dispense <= "0000";
Return_coins <= "0000";
-- HEX_data <= (others => '0');
P_C <= "0000";
prod_num_t <= "1111";
Repeat_insert <= '0';
price_temp1 <= 0;
price_temp2 <= 0;
active <= '0';
-- exact_payment<='1';
n0100<=0;
n0050<=0;
n0020<=0;
n0010<=0;

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active <= '1';
state <= zero;
else
state <= intzn;
end if;
when zero =>
state <= sel_updt;
else
state <= zero;
end if;
when sel_updt => --if cancel = '0' then
P_C <= "1010"; -- indicate P
price_temp1 <= price;
price_temp2 <= price;
prod_num_t <= prod_num;
--HEX_data <= prod_num & P_C & price_temp;
state <= pay_st1;
--else
--state <= intzn;
--end if;
when pay_st1 => --Return_coins <= "1111";
if cancel= '1' then
if coin_sel = '0' then
state <= pay_st2;
else
state <= pay_st1;
end if;
else
state<= intzn;
end if;
when pay_st2 => if cancel = '1' then
if coin_sel = '1' then
price_temp2 <= price_temp2 - coin;
state <= pay_st3;
else
state <= pay_st2;
end if;
else
state <= intzn;
end if;
when pay_st3 =>
if cancel = '1' then
if price_temp2 <= 0 then
ret :=
not(conv_std_logic_vector(price_temp2,8)); --1's complement
ret_change <= ret+'1'; -- 2's
complement
price_ret <= conv_integer(ret_change);
state <= change;
else
price_temp1 <= price_temp2;
state <= pay_st1;
end if;
else
state<= intzn;
end if;
when change =>
-- price_temp1 <= conv_integer(ret_change) ; --
convert it back to the integer
-- price_ret <= conv_integer(ret_change);
if resp = '0' then
if price_ret = 0 then

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state <= chk_rsp;
else
state <= repeat;
end if;
else
state <= chk_rsp;
end if;
when chk_rsp =>
-- if resp = '1' then
if price_ret >= 100 then
-- if n0100 <= 10 then
-- if c0100(n0100) = '1' then
price_ret <= price_ret - 100;
-- c0100(n0100) <= '0';
n0100 <= n0100+1;
state <= chk_rsp;
-- else
-- state <= repeat;
-- end if;
-- else
-- state <= repeat;
-- end if;
elsif price_ret >=50 then
-- if n0050 <= 10 then
-- if c0050(n0050) = '1' then
-- c0050(n0050) <= '0';
n0050 <= n0050+1;
state <= chk_rsp;
-- else
-- state <= repeat;
-- end if;
-- else
-- state <= repeat;
-- end if;
-- if n0020 <= 10 then
-- if c0020(n0020) = '1' then
-- c0020(n0020) <= '0';
n0020 <= n0020+1;
state <= chk_rsp;
-- else
-- state <= repeat;
-- end if;
-- else
-- state <= repeat;
-- end if;
-- if n0010 <= 10 then
-- if c0010(n0010) = '1' then
-- c0010(n0010) <= '0';
n0010 <= n0010+1;
state <= chk_rsp;
-- else
-- state <= repeat;
-- end if;
-- else
-- state <= repeat;
-- end if;
elsif price_ret = 0 then
state <= dspns;
elsif price_ret < 0 then
state <= repeat; -- repeat
-- price_temp1 <= price_ret ;
end if;

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-- else
-- state <= repeat;
-- end if;
when repeat =>
-- price_ret <= 0;
-- n0010 <= -- I need to store the information to
ensure that the original coins are restored
-- get rid of arrays and just use a
std_logic_vector
state_return<=sel_updt;
state<=beep_onsec;
when dspns =>
P_C <= "1011";
-- prod_num_t <= "1111";
nt100 <= n0100;
nt050 <= n0050;
nt020 <= n0020;
nt010 <= n0010;
Dispense <= prod_num ;
price_temp1 <= conv_integer(ret_change) ;
state <= beep_onsec;
state_return <= return_coins1;
When return_coins1 =>
if nt100 > 0 then
nt100 <= nt100-1;
Return_Coins(3) <= '1';
else
-- state <= beep_halfsec;
-- state_return <= return_coins1;
-- else
end if;
state <= return_coins050 ;
when return_coins050 =>
if nt050 > 0 then
nt050 <= nt050-1;
else
-- else
end if;
when return_coins020=>
if nt020 > 0 then
nt020 <= nt020-1;
else
--
-- else
-- return_coins <= (others => '0');
end if;
when return_coins010 =>
if nt010 > 0 then
nt010 <= nt010-1;

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else
end if;
state <= beep_halfsec;
state_return <= stay;
when beep_onsec =>
if onsec <= 500 then
onsec <= onsec+1;
elsif onsec <= 1000 then
onsec <= onsec +1;
Return_Coins <= "0000";
dispense<=(others=>'0');
repeat_insert<='0';
else
return_coins <= (others => '0');
onsec <= 0;
state <= state_return;
end if;
when beep_halfsec =>
if onsec <= 250 then
onsec <= onsec+1;
elsif onsec <= 500 then
onsec <= onsec +1;
Return_Coins <= "0000";
else
return_coins <= (others => '0');
onsec <= 0;
state <= state_return;
end if;
when stay =>
-- price_temp1 <= n0020;
state <= intzn;
end case;
end if;
end if;
end process;
end Behavioral;
------------------------------BCD-----------------------------
library IEEE;
use IEEE.STD_LOGIC_unsigned.ALL;
entity BCD is
price : in integer;
hexdata : out STD_LOGIC_VECTOR (15 downto 0):="1111111111111111");
end BCD;
architecture Behavioral of BCD is
signal n4,n3,n2,n1, price_temp: integer:=0;
type state_names is (intzn, start_BCD);
signal state: state_names;
begin

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process (clk, reset, price)
begin
if reset = '0' then
n4 <= 0;
n3 <= 0;
n2 <= 0;
n1 <= 0;
price_temp <= price;
state <= intzn;
case state is
when intzn =>
if active = '1' then
n4 <= 0;
n3 <= 0;
n2 <= 0;
n1 <= 0;
price_temp <= price;
state <= start_BCD;
else
hexdata <= "1111111111111111";
end if;
when start_BCD =>
if price_temp >= 1000 then
price_temp <= price_temp - 1000;
n4 <= n4+1;
state <= start_BCD;
elsif price_temp >= 100 then
price_temp <= price_temp -100;
n3 <= n3+1;
state <= start_BCD;
elsif price_temp >= 10 then
price_temp <= price_temp -10;
n2 <= n2+1;
state <= start_BCD;
else
hexdata(15 downto 12) <=
conv_std_logic_vector(n4,4); -- thousand
conv_std_logic_vector(n3,4); -- 100's
conv_std_logic_vector(n2,4); --10's
conv_std_logic_vector(price_temp,4); --1's
state <= intzn;
end if;
end case;
end if;
end process;
end Behavioral;
-----------------------------------------------------ver2.2------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_unsigned.ALL;

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entity ver2_2 is
price:in std_logic_vector(15 downto 0);
dis_sid: in std_logic_vector(1 downto 0);
P_C : in std_logic_vector(3 downto 0);
prod_num_t :in std_logic_vector(3 downto 0);
Hex6: out std_logic_vector(6 downto 0):="0111111"
);
end ver2_2;
architecture Behavioral of ver2_2 is
----------------------BCD-------------------
signal display1: std_logic_vector(6 downto 0):="0111111";
----------------------------------------------
signal dcount1: std_logic_vector(3 downto 0):="1111";
----------------------------------------------
---- clk_process ----
signal clk25M: std_logic;
signal cnt25M: integer range 0 to 1;
signal clk1m: std_logic;
signal cnt1m: integer range 0 to 100000000:=0;
-- clk process -----------
signal clkt: std_logic:='0';
signal cnt20k: integer range 0 to 50000:=0;
--state maching for assigning-------
type state_names is (intzn, assign);
signal state: state_names;
begin
------------------------------------seven segment output --------------------------
----------------
--seg <= dcount6 & dcount5 & dcount4 & dcount3 & dcount2 & dcount1;
--
Hex1 <= display1;
Hex2 <= display2;
Hex3 <= display3;
Hex4 <= display4;
Hex5 <= display5;
Hex6 <= display6;
-----------------------------------------------------------------------------------
----------------
------------------------------------display process -------------------------------
-------------

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process(clkt, reset)
begin
if reset = '0' then
dcount1 <= "1111";
dcount2 <= "1111";
dcount3 <= "1111";
dcount4 <= "1111";
dcount5 <= "1111";
dcount6 <= "1111";
elsif rising_edge(clkt) then
case dis_sid is -- student id 1
when "01" =>
dcount1 <= "1000"; --8
dcount2 <= "0000"; --0
dcount3 <= "0100"; --4
dcount4 <= "1000"; --8
dcount5 <= "0111"; --7
dcount6 <= "0011"; --3
when "10" => -- change here to enter student id 2
dcount1 <= "0110";--6
dcount2 <= "0110";--6
dcount3 <= "0000";--0
dcount4 <= "1000";--8
dcount5 <= "1001";--9
dcount6 <= "0001";--1
when others =>
case state is
when intzn =>
if active = '1' then
dcount1 <= price(3 downto 0);
dcount5 <= P_C;
dcount6 <= prod_num_t;
state <= assign;
else
dcount1 <= "1111";
dcount2 <= "1111";
dcount3 <= "1111";
dcount4 <= "1111";
dcount5 <= "1111";
dcount6 <= "1111";
state <= intzn;
end if;
when assign =>
state <= intzn;
end case;
end case;
end if;
end process;
--------------------------------------------------------clk process----------------
-----------
clk20kHz: process(clk,reset)
begin
if reset = '0' then
clkt <= '0'; cnt20k <= 0; -- reset values
if cnt20k < 50000 then -- to avoid 2 ms key debounce

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cnt20k <= cnt20k + 1; -- counts up until it reaches 25000
else
clkt <= not clkt; -- clk1k inverts itself every 25000 counts
cnt20k <= 0;
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '0' then
cnt25M <= 0;
clk25M <= '0';
clk25M <= not clk25M;
end if;
if reset = '0' then
cnt1m <= 0;
clk1m <= '0';
clk1m <= '0';
cnt1m <= 0;
if cnt1m <= 50000000 then
cnt1m <= cnt1m+1;
else
cnt1m <= 0;
clk1m <= not clk1m;
end if;
end if;
end process;
----------------------------------------dcount(in_binary) to sevensegment
conversion---------------------
process (clk, reset)
begin
if reset = '0' then
display1 <= "0111111";
case dcount1 is
when "0000" => display1 <= "1000000"; --0
when "0001" => display1 <= "1111001"; --1
when "0010" => display1 <= "0100100"; --2
when "0011" => display1 <= "0110000"; --3
when "0100" => display1 <= "0011001"; --4
when "0101" => display1 <= "0010010"; --5
when "0110" => display1 <= "0000010"; --6
when "0111" => display1 <= "1111000"; --7
when "1000" => display1 <= "0000000"; --8
when "1001" => display1 <= "0010000"; --9
when others => display1 <= "0111111";
end case;
end if;
end process;
begin
if reset = '0' then
display2 <= "0111111";
case dcount2 is
when "0000" => display2 <= "1000000"; --0
when "0001" => display2 <= "1111001"; --1
when "0010" => display2 <= "0100100"; --2
when "0011" => display2 <= "0110000"; --3

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when "0100" => display2 <= "0011001"; --4
when "0101" => display2 <= "0010010"; --5
when "0110" => display2 <= "0000010"; --6
when "0111" => display2 <= "1111000"; --7
when "1000" => display2 <= "0000000"; --8
when "1001" => display2 <= "0010000"; --9
end case;
end if;
end process;
begin
if reset = '0' then
display3 <= "0111111";
case dcount3 is
when "0000" => display3 <= "1000000"; --0
when "0001" => display3 <= "1111001"; --1
when "0010" => display3 <= "0100100"; --2
when "0011" => display3 <= "0110000"; --3
when "0100" => display3 <= "0011001"; --4
when "0101" => display3 <= "0010010"; --5
when "0110" => display3 <= "0000010"; --6
when "0111" => display3 <= "1111000"; --7
when "1000" => display3 <= "0000000"; --8
when "1001" => display3 <= "0010000"; --9
end case;
end if;
end process;
begin
if reset = '0' then
display4 <= "0111111";
case dcount4 is
when "0000" => display4 <= "1000000"; --0
when "0001" => display4 <= "1111001"; --1
when "0010" => display4 <= "0100100"; --2
when "0011" => display4 <= "0110000"; --3
when "0100" => display4 <= "0011001"; --4
when "0101" => display4 <= "0010010"; --5
when "0110" => display4 <= "0000010"; --6
when "0111" => display4 <= "1111000"; --7
when "1000" => display4 <= "0000000"; --8
when "1001" => display4 <= "0010000"; --9
end case;
end if;
end process;
begin
if reset = '0' then
display5 <= "0111111";
case dcount5 is
when "0000" => display5 <= "1000000"; --0
when "0001" => display5 <= "1111001"; --1
when "0010" => display5 <= "0100100"; --2
when "0011" => display5 <= "0110000"; --3
when "0100" => display5 <= "0011001"; --4
when "0101" => display5 <= "0010010"; --5

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when "0110" => display5 <= "0000010"; --6
when "0111" => display5 <= "1111000"; --7
when "1000" => display5 <= "0000000"; --8
when "1001" => display5 <= "0011000"; --9
when "1010" => display5 <= "0001100"; --P
when "1011" => display5 <= "1000110"; --C
end case;
end if;
end process;
begin
if reset = '0' then
display6 <= "0111111";
case dcount6 is
when "0000" => display6 <= "1000000"; --0
when "0001" => display6 <= "1111001"; --1
when "0010" => display6 <= "0100100"; --2
when "0011" => display6 <= "0110000"; --3
when "0100" => display6 <= "0011001"; --4
when "0101" => display6 <= "0010010"; --5
when "0110" => display6 <= "0000010"; --6
when "0111" => display6 <= "1111000"; --7
when "1000" => display6 <= "0000000"; --8
when others => display6 <="0111111";
end case;
end if;
end process;
end Behavioral;

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ADVANTAGES ANDDISADVANTAGES
Advantages
I. Vending machine gives customer a wide choice to purchase, and it could be
bought in any 24 hours of the day, i.e. User friendly.
II. It is diverse, it can cover product ranging from fruits to cigarettes and similar
other products. This method is used in service provision industries like public
utility practises.
III. Location of vending machines are made at that point where the traffic of
people is high, which saves lot of time and creates high convenience to the
user.
IV. No need to hire staff which saves labour and capital, increasing profits. It’s a
onetime investment.
V. Easily transferable to other locations, in case of transfer of place, which is
easy to relocate as only power plug needs to be removed making it more
mobile.
Disadvantages
I. It has many disadvantages too, like it creates a gap between the consumer and
the owner as the customer cannot negotiate for the cost of the product applying
fixed prices being unfriendly.
II. Fraud cases are common in this type of machines as some people find a
method to hack into system and dispense the product without paying.
III. Competition in the market can cause vandalism, causing irregular behaviour of
the vending machines and faulty program can cause continuous dispense of
products due to technical error.
IV. Before investing on the vending machine one has to think over proper
maintenance and some unexpected losses also [5].

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SIMULATION AND RESULTS
Aftersimulatingandcompilingthe top_module_TB(TestBench) for100 us we getthe following
waveformfrommodelsim,choosingproduct6.
Figure 1.7: Waveform for 100us for product 6
In thiswaveformwe cansee that reset=1,thenclkis higha productis loadedandthenitswaitingfor
the userto confirm,once confirmthe change/paymentsignal goeshigh.

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Figure 1.8: Waveform for product 8
As we have made the tb to have exact change =1, so the final state of return_coins will always be
low.
Figure 1.9 : Complete Waveform for product 6
As we couldn’tprintthe waveformforproduct6, we had to take screenshotforcomplete overview
of the processhappeninginthe vendingmachine.

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Test Bench for VendingMachine
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY top_module_TB IS
END top_module_TB;
ARCHITECTURE behavior OF top_module_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_module
PORT(
clk : IN std_logic;
reset : IN std_logic;
Product : IN std_logic_vector(2 downto 0);
Ent_coin : IN std_logic_vector(4 downto 0);
confirm : IN std_logic;
Cancel : IN std_logic;
resp : IN std_logic;
SID : IN std_logic;
Repeat_insert : OUT std_logic;
exact_payment : OUT std_logic;
Hex1 : OUT std_logic_vector(6 downto 0);
Dispense : OUT std_logic_vector(3 downto 0);
Return_coins : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal Product : std_logic_vector(2 downto 0) := (others => '0');
signal Ent_coin : std_logic_vector(4 downto 0) := (others => '0');
signal confirm : std_logic := '0';
signal Cancel : std_logic := '0';
signal resp : std_logic := '0';
signal SID : std_logic := '0';
--Outputs
signal Repeat_insert : std_logic;
signal exact_payment : std_logic;
signal Hex1 : std_logic_vector(6 downto 0);
signal Dispense : std_logic_vector(3 downto 0);
signal Return_coins : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN

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-- Instantiate the Unit Under Test (UUT)
uut: top_module PORT MAP (
clk => clk,
reset => reset,
Product => Product,
Ent_coin => Ent_coin,
confirm => confirm,
Cancel => Cancel,
resp => resp,
SID => SID,
Repeat_insert => Repeat_insert,
exact_payment => exact_payment,
Hex1 => Hex1,
Hex2 => Hex2,
Hex3 => Hex3,
Hex4 => Hex4,
Hex5 => Hex5,
Hex6 => Hex6,
Dispense => Dispense,
Return_coins => Return_coins
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- reset process
reset_proc: process
begin
reset <= '0'; --active low
wait for 10 ns;
reset <= '1';
wait;
end process;
--product switch
product_button: process
begin
Product <= "101";
wait for 10 us;
confirm <= '1'; -- press confirm key
wait for 10 us;
confirm <= '0'; -- and, release confirm key
wait;
end process;
cancel_process: process
begin
cancel <= '1';
wait;
end process;
--pay process
Enter_coin: process
begin
Ent_coin <= "00000";
wait for 30 us;
Ent_coin(4) <= '1'; -- 02.00
wait for 10 us;
Ent_coin <= "00000";

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wait for 10 us;
Ent_coin(4) <= '1'; -- 02.00
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(3) <= '1'; -- 01.00
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(2) <= '1'; -- 00.50
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(1) <= '1'; -- 00.20
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(0) <= '1'; -- 00.10
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(0) <= '1'; -- 00.10
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(0) <= '1'; -- 00.10
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(4) <= '1'; -- 00.10
wait for 10 us;
Ent_coin <= "00000";
wait for 10 us;
Ent_coin(0) <= '1'; -- 00.10
wait ;
end process;
END;
CONCLUSION
Vending machine has been developed on DE0 board successfully and all its design
specifications are met. Maximum resources has been used on the board to get the output as
soon as possible using 50MHz clock and it’s a synchronous and mealy FSM has been
implemented to design this vending machine.

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REFERENCES
1. Encyclopaedia.com, http://www.encyclopedia.com/topic/vending_machine.aspx
2. WhatIs.com http://whatis.techtarget.com/definition/finite-state-machine
3. http://picturejedi.com/old-coke-machine-coin-mechanism?adoff
4. https://www.pinterest.com/pin/343821752772365304/
5. http://www.costsoldier.com/facilities/vending-machines/a/advantages-and-
disadvantages-of-vending-machines/ .
6. Lecture notes- Intro. To comp. Eng chapter VIII-32, FSM by R.M. Dansereau.
http://users.ece.gatech.edu/limsk/course/ece2020/lecs/lec8.pdf .
7. Lecture notes- Finite state machines and design FSM using VHDL Examples by Ba
Son Thai, 2015
https://lms.latrobe.edu.au/pluginfile.php/2214316/mod_resource/content/1/Lecture_17_18.pdf.

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