1. NAVEEN REDDY
4441 Laird Cir Santa Clara CA 95054
(408)-876-9719, reddyn@gmail.com
OBJECTIVE
Utilize my extensive Semiconductor Test Engineering experience to contribute to a fast growing company as a Senior Test
Engineer/Manager.
EDUCATION
• Illinois Institute of Technology, Chicago, USA Aug 1999 - Dec 2001
MS in Computer & Electrical Engineering
• Dayananda Sagar College of Engineering, Bangalore, India Aug 1994 - Aug 1998
Bachelor of Engineering, with focus on Electronics and Communications.
EXPERIENCE
Broadcom (through acquisition of NetLogic) – Santa Clara, CA April 2011 – Present
Principal Test Engineer (Platform: Verigy smartscale)
Products: Digital Front End products • Netlogic CAM products
Work at a glance: NPI (New Product Introduction) involving •Design of High speed DIB, wafer sort, burn-in boards
•Developing qualification, characterization & Final test programs •EVCD vector conversion using VTRAN •Custom UTM
development •Production program handoff to offshore test houses. Production support involving •Yield improvement, test
time reduction and RMA support
Teamwork: Work with design team in bringing up scan based DFT •Co-ordinate with design and apps team in developing
high speed Serdes tests •Work with PE in designing UTMs to collect and analyze STDF data using Dataconductor.
Highlights:
 Developed an instruction based test vector to implement MDIO protocol. Using this vector, the Serdes framer registers
could be written into via the MDIO interface, for both the characterization of the Serdes eye and for 4 point Serdes
testing in production. Vectors were developed using Memory Test Plus (MTP) (Verigy proprietary software to test
memory) and Perl. This method was used for 100% Serdes testing correlation between system and ATE.
• Reduced production test time by converting the above vector to a multiport vector thereby reducing the number of
sequencer instructions.
• Developed custom UTM’s in C/C++ to suit test needs and to collect STDF data as per Dataconductor format.
• Project planning/management of test and reliability hardware and software, from pre-tapeout, to prototype samples,
characterization, and high volume production release at offshore contract manufacturers (UTAC, KYEC, ASE).
Optichron, Inc. (acquired by NetLogic) – Fremont, CA Sep 2007 – Apr2011
Senior Test Engineer
• Responsible for ATE test development on the Verigy Pinscale tester. As the sole test engineer in the company, developed
wafer-sort and final-test programs for characterization, production and qualification of the company’s DPD (Digital Pre-
Distortion) products.
• Project planning/execution of new products from pre-tapeout, to prototype samples, characterization, and volume production:
− Test hardware design and manufacturing (ATE load-boards, probe-cards, handler change-kits)
− ATE software development (characterization and production test plans, development, debug, and release). This included
detailed DC/AC datasheet parameters characterizations of single-ended CMOS and high speed differential (LVDS) I/O’s.
− Reliability test development (HTOL/HAST boards design, ESD/LU, vector generation, pre-qualification debug)
− Bench test product characterization planning & execution in co-ordination with the Design and Applications teams.
Centillium – Bangalore, India Feb 2007 – Jul 2007
Test Engineer
Developed test programs for a VoIP chip (code name Atlanta 2) on Agilent 93K tester, which consisted of simulation to ATE test
vector conversion, ATE test program development, test vector debug, Engineering Samples shipments, characterization and
production test programs development and release. This required interaction with various teams such as Design, DFT and Sales.
Integrated Device Technology – San Jose, CA Nov 2005 – Sep 2006
Product Applications Engineer
Worked as a product application engineer, on a SPI-4 protocol product, in the Flow Control Management division. My duties
involved developing scripts/programs in Tcl to test the device on the evaluation board, download firmware and develop scripts to
configure the chip to emulate applications like a 3-port switch, aggregator, developing data sheet and application notes.

2. Advantest America Inc. – Santa Clara, CA Jan 2001 – Oct 2005
Applications Engineer
Worked as an application engineer supporting the T6682/83 & T2000 Logic testers. My duties included supporting major
customers (LSI, Intel) in development of their test programs using these testers, conducting training sessions, pre-sales technical
presentations at trade shows, vector translation from Teradyne to Advantest using Perl, C++. In this role I had to interact with our
parent company in Japan for training and support.
Skills
• ATE Testers: Advantest (T6682/83, T2000), Verigy (P-series, Pinscale, Smartscale)
• Test Tools: Memory Test Plus(MTP), Algorithmic Pattern Generation (APG), convertors (VTRAN), Verigy
Smartest
• Software Tools: C/C++, PERL, Tcl, MS Word/EXCEL/Powerpoint