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Peter Vinh
Cell Phone: (408) 528-5204
Email: kcpvinh@gmail.com
OBJECTIVE: Seeking for full time Product and Test Engineer
QUALIFICATIONS:
 Over ten plus years of experience in product and test engineer in Semiconductor
industry to develop the test methodology and design the test hardware
 Developing and generating the test patterns to verify the device functionality and
improving the device quality and reliability
 Willing to learn to be successful
 PCB and IC component trouble shooting
 Very helpful for cost reduction through yield improvement and test time
 Excellent organizational and communication skills. Quick learner and hard
working. Great in team works and get along well with co-workers
 Able to carry out multi tasks, prioritize and complete to meet deadlines for all
tasks assignments
 Experienced on lab equipments such as: Logic Analyzers, Protocol Analyzers,
Microscope, and Oscilloscopes
 Knowledge Shell Scripting on Linux and Batch Scripting on Window
 Use Allegro viewer to review the layout to debug and rework the load board
 Able to solder the small components under microscope with size 0402
EXPERIENCE:
Product/Test Engineer, Texas Instruments (from Feb/2014 to Present)
Accomplishments:
 Develop coding setup and debug for Analog IP such as: Band-Gap, Charge
Pump, Oscillator, POR, I2C, and PLL
 Develop coding setup and debug for Memory IP such as: NVM OTP Trim, Single-
Ended OTP Trim, Differential-Ended OTP Trim, OTP with Trim Register
(Serial/Parallel), ROM, SRAM, and FRAM
 Design Hardware for all MSIP Verification
 Characterizing Analog IP and Memory IP device performance per design
specification data sheet and generating the report in order to give the feedback to
the designer for device enhancement
 Coordinating with failure analysis engineers and designers to find the root cause
of the reliability failed units
Lam Research Corporation (from March/2012 to Feb/2014 as Sr. Engineering
Technician)
Accomplishments:
 Clean Pilot Line
 Assembly and Test Serene
 Assembly EFEM (Wafer Robot Loading)
 2300 Serene BRS Module System Testing: Using procedure to facilitize,
setup and perform functional test
 Assembly PM (Position Module) and Test
Lam Research Corporation (from Oct/2010 to March/2012 as Test Engineering
Technician)
Accomplishments:
 Test PM (position module) Kiyo Conductor Etch Production
 2300 Versus Kiyo
 2300 Versus Kiyo 45
 2300 Versus Kiyo C
 2300 Versus Kiyo E
 Test PM Flex Dielectric Etch Product Family
 2300 Exelan Flex
 2300 Exelan Flex 45
 2300 Exelan Flex D Series
 2300 Exelan Flex E Series
ATE Test, Telegent Systems (July/2009 to Sept/2010)
Accomplishments:
 Support Product/Test/QA Engineers to trouble shoot the failure of RF IC.
 Soldering small components 0204 for Test boards.
 Tested Jupiter, Zeus, Poseidon devices on Catalyst and Verigy 93K
 Help to collect data, summarize, analyze low yield, and failure mode of RF
Integrate Circuit
Product/Test Engineer, National Semiconductor (Sept/2000 - Nov/2008)
Accomplishments:
 Supporting the designers to test, debug the new SRAM and Non-Volatile Memory
chips
 Design ATE load board and probe card to support for the test program in both
wafer sort and FT testing environment
 Characterizing SRAM and NVM device performance per design specification
data sheet and generating the report in order to give the feedback to the designer
for device enhancement
 Process technology qualification for reliability prior to implementing into the real
product
 Coordinating with failure analysis engineers and designers to find the root cause
of the reliability failed units
 Coordinating with outside vendor to test and contract for package assembly
 Defect and low yield product analyzing by using the yield analyzing software
tools, bitmap and wafer-map to find the systematic or random process defect
 Bench testing to debug the device and tested validation.
 Developing the active laser trim test program to interface the ATE tester with the
laser trim machine to support for Amplifier Group
EDUCATION:
 Bachelor of Science in Electrical Engineering, Long Beach University, 2000
TESTER AND COMPUTER LANGUAGES:
 ATE Tester: Teradyne Micro-flex/Catalyst, Eagle Test System, LTX, and
Teradyne J971
 Programming Languages: Visual Basic, C/C++, M/S Office (Word, Outlook,
Excel, PowerPoint), Unix, Linux
REFERENCE: Available upon request

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Peter Vinh Resume

  • 1. Peter Vinh Cell Phone: (408) 528-5204 Email: kcpvinh@gmail.com OBJECTIVE: Seeking for full time Product and Test Engineer QUALIFICATIONS:  Over ten plus years of experience in product and test engineer in Semiconductor industry to develop the test methodology and design the test hardware  Developing and generating the test patterns to verify the device functionality and improving the device quality and reliability  Willing to learn to be successful  PCB and IC component trouble shooting  Very helpful for cost reduction through yield improvement and test time  Excellent organizational and communication skills. Quick learner and hard working. Great in team works and get along well with co-workers  Able to carry out multi tasks, prioritize and complete to meet deadlines for all tasks assignments  Experienced on lab equipments such as: Logic Analyzers, Protocol Analyzers, Microscope, and Oscilloscopes  Knowledge Shell Scripting on Linux and Batch Scripting on Window  Use Allegro viewer to review the layout to debug and rework the load board  Able to solder the small components under microscope with size 0402 EXPERIENCE: Product/Test Engineer, Texas Instruments (from Feb/2014 to Present) Accomplishments:  Develop coding setup and debug for Analog IP such as: Band-Gap, Charge Pump, Oscillator, POR, I2C, and PLL  Develop coding setup and debug for Memory IP such as: NVM OTP Trim, Single- Ended OTP Trim, Differential-Ended OTP Trim, OTP with Trim Register (Serial/Parallel), ROM, SRAM, and FRAM  Design Hardware for all MSIP Verification  Characterizing Analog IP and Memory IP device performance per design specification data sheet and generating the report in order to give the feedback to the designer for device enhancement  Coordinating with failure analysis engineers and designers to find the root cause of the reliability failed units Lam Research Corporation (from March/2012 to Feb/2014 as Sr. Engineering Technician) Accomplishments:  Clean Pilot Line  Assembly and Test Serene
  • 2.  Assembly EFEM (Wafer Robot Loading)  2300 Serene BRS Module System Testing: Using procedure to facilitize, setup and perform functional test  Assembly PM (Position Module) and Test Lam Research Corporation (from Oct/2010 to March/2012 as Test Engineering Technician) Accomplishments:  Test PM (position module) Kiyo Conductor Etch Production  2300 Versus Kiyo  2300 Versus Kiyo 45  2300 Versus Kiyo C  2300 Versus Kiyo E  Test PM Flex Dielectric Etch Product Family  2300 Exelan Flex  2300 Exelan Flex 45  2300 Exelan Flex D Series  2300 Exelan Flex E Series ATE Test, Telegent Systems (July/2009 to Sept/2010) Accomplishments:  Support Product/Test/QA Engineers to trouble shoot the failure of RF IC.  Soldering small components 0204 for Test boards.  Tested Jupiter, Zeus, Poseidon devices on Catalyst and Verigy 93K  Help to collect data, summarize, analyze low yield, and failure mode of RF Integrate Circuit Product/Test Engineer, National Semiconductor (Sept/2000 - Nov/2008) Accomplishments:  Supporting the designers to test, debug the new SRAM and Non-Volatile Memory chips  Design ATE load board and probe card to support for the test program in both wafer sort and FT testing environment  Characterizing SRAM and NVM device performance per design specification data sheet and generating the report in order to give the feedback to the designer for device enhancement  Process technology qualification for reliability prior to implementing into the real product  Coordinating with failure analysis engineers and designers to find the root cause of the reliability failed units  Coordinating with outside vendor to test and contract for package assembly  Defect and low yield product analyzing by using the yield analyzing software tools, bitmap and wafer-map to find the systematic or random process defect  Bench testing to debug the device and tested validation.  Developing the active laser trim test program to interface the ATE tester with the laser trim machine to support for Amplifier Group
  • 3. EDUCATION:  Bachelor of Science in Electrical Engineering, Long Beach University, 2000 TESTER AND COMPUTER LANGUAGES:  ATE Tester: Teradyne Micro-flex/Catalyst, Eagle Test System, LTX, and Teradyne J971  Programming Languages: Visual Basic, C/C++, M/S Office (Word, Outlook, Excel, PowerPoint), Unix, Linux REFERENCE: Available upon request