1. Zheng Ma
Elk Grove, CA | linkedin.com/in/zhengjohnma | 916-647-4763 | johnzhengma@gmail.com
PROFILE
Highly experienced Product Development Manager and Computer Engineer, with extensive experience in Design
or Testing & RTL validation, High Volume Manufacture (HVM) content development and deployment. Worked
with cross-functional and diverse teams.
 Creating and delivering differentiated products and solutions.
 Change-agent focused on product life cycle process for faster Time-to-Market (TTM).
 Demonstrated business growth success in both disruptive-innovation and sustaining-innovation situations.
 Tenacity to succeed with proven leadership and a track record of developing strong engineering teams
through mentoring.
Languages: Perl, C, C++, VHDL
Technology: Client, Server and SoC Scan test technology and methodology, RTL Logic validation, functional
fault grading, High Volume Manufacture Content Development and Deployment
Intel Corp. Folsom CA
Tech Lead, SOC ATPG Content Development 2015 – 2016
Delivered SoC Graphic IP ATPG Pattern Suite and Drove Technical Readiness for upcoming SOC product.
 Assume responsibility to generate ATPG pattern on Display engine, preventing project delay due to site
realignment. Root caused faulty pattern to design timing constrain bug.
 Developed execution plan, outlining cross team responsibilities and developing SoC converged ATPG Tes ter
Pattern Generation Automation flow.
Engineering Manager, Client Graphic Scan Validation and ATPG Content Development 2007 – 2015
Managed a Client Graphic IP Product Development Team (PDE) to delivered 4 Generations of ATPG High Volume
Manufacture (HVM) content and successfulproduct launches.
 Single handed built a 9 engineers team at 2 worldwide locations with little ATPG experience, introducing new
team members to ATPG tool usage and execution best known method.
 Established design operations metrics, baseline, goals, and reporting system, created a sharing platform to
improve cross functional team communications. This best-practices are adopted by other Intel team to improve
their execution.
 Pioneered DFT Design Rule Check Execution Flow, ensuring design free of error before Silicon tape-out.
 Headed team execution with owing ATPG execution and coverage improvement on 4 partitions.
 Delivered many of Intel first such as Advanced Cell Library Scan Pattern Generation to improve defect
screening and at-speed binning to maximum Intel income revenue.
 Received many Intel Division Awards such as Test Time Reduction > 45% and helping to deliver Intel 1st CPU
with integrated Graphics Core.
Engineering Manager, SOC Scan Validation and ATPG Content Development 2012 – 2013
Coordinated a group of 6 engineers focusing in unCore, Core and Graphic Scan DFT Validation and ATPG Content
Development.
 Defined cross team accountability with execution plan including project reviews, team technical ramp up plan,
receivables quality and timeline and team deliverable schedule.
 Guided the team to develop Intel 1st SOC documentation including Scan Architecture implementation, content
generation and testerpattern generation flow, content validation flow, test model flow and Silicon debug triage
steps.
 Conducted a smooth project transfer with cross site trainings and project status reviews, avoiding project mis -
step that could cost Silicon delay.

2. EngineeringManager,Xeron unCore Scan DFT Validationand ATPG Development 2008 – 2011
Directed a group of 9 engineers at 3 Intel Sites and created ATPG production pattern suite. Developed Scan DFT
Design Validation Flow, ATPG generation tool enhancements, stuck-at pattern above coverage requirements and
at-speed pattern on low speed clusters.
 Enabled 30+ DFT design role checkers, preventing design bug slip into Silicon. Provided training/supports to
30+ designers and provided fix suggestions,reducing week long bug fix time into hours.
 Enabled ATPG content generation flow and defined new features, enabling fast and accrual stuck-at and at-
speed content generation flow meeting design requirements.
 Proactively reviewed receivable quality and drove issue closures, preventing month long upstream re-work and
keeping project on schedule.
 Delivered at-speed ATPG patterns on low speed clusters without additional engineer resource, eliminated the
need to fund 3 functional test writers and month long silicon debug efforts.
 Received Intel Awards such as delivering ATPG stuck-at content suite to launch Intel 1st Datacenter and cloud
computing Server CPU with Integrated I/O and Intel 1st Server with Low Speed Clusters with at-speed ATPG
Patterns.
Engineer, Pentium 4 unCore Scan DFT Validation and ATPG Content Development 2004 – 2007
Established Folsom Site unCore Scan PDE Team. Delivered content ahead of schedule, helped to successfully PRQ
Intel 1st Converged Client CPU Core
 Partnered with cross site member to pioneer fault disposition method for ATPG coverage assessment,helping
Intel to design robust Scan design architecture. Uncovered tool bugs and validation hole, providing bug fix
suggestions to help Design Automation team on tool deployment.
 Chaired a Weekly Work Group to outline Content Delivery expectations and drove Silicon Debug efforts.
Work Group consists ofRTL and DFT designer, Design for Automation and Scan Test Module Owner.
 Published Full-Chip Coverage Report 8 months before Tape-Out and improved ATPG Coverage exceeding
requirement, helping Intel to screen out faulty part before customer delivery.
 Received 2 Intel Division Awards for faultless executions.
Engineer, Pentium CPU Product Development 2003 – 2004
Supported the development & execution of Fault Grading (FG) for two CPU products. Pioneered many methods
and automation to keep team meeting project milestone.
 Created multiple Perl script to streamline execution, such as automated module build process and improve
execution time > 10x+, reduced hour long data collection to minutes, conducted automation process to
determine the best FG command options,spited multi-million fault list into smaller chunk to overcome memory
allocation error and generated report file to track execution phases and status.
 Pioneered many new methods including Zero-state, non x-free and fast reset direct circuits initialization, create
delta delay cell library to module circuits race condition. Contributed for keeping project on time despite
unexpected roadblocks and a team without any prior Fault Grading Experience.
 Went above expectation to help other to debug their issues and provided Manager coverage to keep the team on
track for deliverables.
 Received Division Awards such as Advanced Array Modeling reducing Memory Size.
Engineer, Micro-Architecture Validation 2000 – 2002
Responsible for Pentium 4 RTL validations. Meeting Test Coverage goal with robust Test Plan and new RTL tests.
 Enabled internal tools such as Testbanch Build, RTL signal tracing and others between three CPU products.
Reached project milestone with new RTL tests to fill in low coverage areas.
 Created new script to cover exiting test into newer format and filed total 11 bugs that outpaced the whole
validation team.

3. Intel Corp. Folsom CA
Engineer, System Level Simulation 1997 – 1999
Responsible for three Chipset family validation. Developed new validation capabilities and drove bug fix closures.
 Delivered DRAM tracker to print out bus traffic and 31 bus protocols checker, ensuring no bug are escaped into
design.
 Developed Hub Link 8 & 16 Module with capability of sending and responding commands, enabling RTL
designer to validate RTL design before Project Tape-In.
 Owner of 7 partitions validation, developing test plan and writing new tests for test coverage and catching 61
RTL bugs.
EDUCATION
Bachelor of Science, Computer Engineering – California State University of Sacramento