Digital Electronics

1. 1
CSE370, Lecture 14
Lecture 17
u Logistics
n HW5 due on Wednesday
n HW6 will be out on Wednesday, due in one week
n Lab6 this week
u Last lecture
n Memory storage elements
n State diagrams
u Today
n Registers
n Counters
n Start of Finite State Machine (FSM)
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2. 2
CSE370, Lecture 14
The “WHY” slide
u Registers and Counters
n Registers and counters are very simple yet powerful examples
of how you can use the basic memory elements to conduct
productive behavior. They are used everywhere in a
computer.
u Finite State Machine
n This is what we have been waiting for in this class. Using
combinational and sequential logics, now you can design a lot
of clever digital logic circuits for functional products. We will
learn different steps you take to go from word problems to
logic circuits in the next few lectures.
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3. 3
CSE370, Lecture 14
Registers
u Group of storage elements read/written as a unit.
n Store related values (e.g. a binary word)
u Collection of flip-flops with common control
n Share clock, reset, set lines
u Example:
n Storage registers
n Shift registers
n Counters
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4. 4
CSE370, Lecture 14
Storage registers
u Basic storage registers uses flip flops
u Example: 4 bit storage register
R S R S R S
D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT4
CLK
IN1 IN2 IN3 IN4
R S
"0"
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5. 5
CSE370, Lecture 14
Shift registers
u Hold successively sampled input values
n Delays values in time
n Example: 4-bit shift register
í Stores 4 input values in sequence
D Q D Q D Q D Q
IN
OUT1 OUT2 OUT3 OUT4
CLK
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6. 6
CSE370, Lecture 14
Shift-register applications
u Parallel-to-serial conversion for signal transmission
u Pattern recognition (circuit recognizes 1001)
D Q D Q D Q D Q
IN
CLK
OUT
parallel inputs
parallel outputs
serial transmission
CLK CLK
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7. 7
CSE370, Lecture 14
D Q D Q D Q D Q
IN
OUT1 OUT2 OUT3 OUT4
CLK
Counters
u Ring counter: Sequence is 1000, 0100, 0010, 0001
n Assuming one of these patterns is the starting state
u Johnson counter: Sequence is 1000, 1100, 1110,
1111, 0111, 0011, 0001, 0000
D Q D Q D Q D Q
IN
OUT1 OUT2 OUT3 OUT4
CLK
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8. 8
CSE370, Lecture 14
A binary counter
u Has logic between flip-flops
D Q D Q D Q D Q
OUT1 OUT2 OUT3 OUT4
CLK
"1”
D1 D2 D3 D4
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9. 9
CSE370, Lecture 14
Combinational
Logic
Storage Elements
Outputs
State Outputs
State Inputs
Inputs
“States” for finite state machines are kept
in the storage elements
u Combinational logic and storage elements
n Localized feedback loops
n Choice of storage elements alters the logic
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10. 10
CSE370, Lecture 14
In = 0
In = 1
In = 0
In = 1
100
010
110
111
001
Finite-state machines (FSMs)
u States: Possible storage-element values
u Transitions: Changes in state
n Clock synchronizes the state changes
u Sequential logic
n Sequences through a series of states
n Based on inputs and present state
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11. 11
CSE370, Lecture 14
100 110
111
011
101
010
000
001
0
1
1 1
1
1
1
1
0
0
0
0 0
1
0
0
D Q D Q D Q
IN
OUT1 OUT2 OUT3
CLK
Drawing state diagrams
u Show input values
on transition arcs
u Show output values
in state nodes
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12. 12
CSE370, Lecture 14
010
100
110
011
001
000
101
111
3-bit up-counter
Counters revisited
u Great simple examples of state machines
n Output is the counter’s state
u Next state is well defined
n Does not depend on input (no inputs)
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13. 13
CSE370, Lecture 14
FSM design procedure (using counters)
1. Draw a state diagram
2. Draw a state-transition table
3. Encode the next-state functions
Minimize the logic using k-maps
4. Implement the design
We will use a ‘3-bit up counter’ as an example
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14. 14
CSE370, Lecture 14
1. Draw a state diagram
010
100
110
011
001
000
101
111
3-bit up-counter
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15. 15
CSE370, Lecture 14
2. Draw a state-transition table
Like a truth-table
State encoding is easy for counters  Use count value
current state next state
0 000 001 1
1 001 010 2
2 010 011 3
3 011 100 4
4 100 101 5
5 101 110 6
6 110 111 7
7 111 000 0
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16. 16
CSE370, Lecture 14
3. Encode the next state functions
Assume D flip-flops
as state elements
C3 C2 C1 N3 N2 N1
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
0 0 1 1
0 1 0 1
C2
C3
C1
N3
1 1 1 1
0 0 0 0
C2
C3
C1
N1
0 1 1 0
1 0 0 1
C2
C3
C1
N2
N1 := C1'
N2 := C1C2' + C1'C2
:= C1 xor C2
N3 := C1C2C3' + C1'C3 + C2'C3
:= C1C2C3' + (C1' + C2')C3
:= (C1C2) xor C3
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17. 17
CSE370, Lecture 14
D Q D Q D Q
OUT1 OUT2 OUT3
CLK
"1"
4. Implement the design
3 flip-flops hold state
Counter is synchronously clocked
Minimized logic computes next state
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