This document describes a novel algorithm for designing low complexity programmable FIR filters based on an extended double base number system. The algorithm aims to maximize the sharing of adders in the filter's time-multiplexed constant multiplication block by directly mapping coefficients to a quasi-minimum extended double base number system representation. This provides more efficient implementation of coefficient multipliers, which are otherwise complex parts of programmable FIR filters. Logic synthesis results on over 100 filters showed the algorithm reduced logic complexity by up to 47.81% and critical path delay by up to 14.32% compared to existing design methods. The document also provides contact information for Logic Mind Technologies in Bangalore, India regarding the project flow and hardware/software requirements.

1. Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Novel Design Algorithm for Low Complexity
Programmable FIR Filters Based on Extended
Double Base Number System
Abstract—Coefficient multipliers are the stumbling blocks in programmable finite
impulse response (FIR) digital filters. As the filter coefficients change either
dynamically or periodically, the search for common subexpressions for
multiplierless implementation needs to be performed over the entire gamut of
integers of the desired precision, and the amount of shifts associated with each
identified common subexpression needs to be memorized. The complexity of a
quality search is thus beyond the existing design algorithms based on conventional
binary and signed digit representations. This paper presents a new design paradigm
for the programmable FIR filters by exploiting the extended double base number
system (EDBNS). Due to its sparsity and innate abstraction of the sum of binary
shifted partial products, the sharing of adders in the time-multiplexed multiple
constant multiplication block of the programmable FIR filters can be maximized
by a direct mapping from the quasi-minimum EDBNS. The multiplexing cost can
be further reduced by merging double base terms. Logic synthesis results on more
than one hundred programmable filters with filter taps ranging from 10 to 100 and
coefficient word lengths of 8, 12, and 16 bits show that the average logic
complexity and critical path delay of the programmable FIR filters designed by our
proposed algorithm have been reduced by up to 47.81% and 14.32%, respectively
over the existing design methods.

2. SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com