1. UNIT II
ARM PROCESSOR AND PERIPHERALS
ARMArchitecture Versions –ARMArchitecture – Instruction Set
– Stacks and Subroutines – Features of the LPC 214X Family –
Peripherals – The Timer Unit – Pulse Width Modulation Unit –
UART – Block Diagram ofARM9 andARM Cortex M3 MCU.
2. 2.1 ARMArchitecture Versions
⚫The ARM processor isa Reduced Instruction Set
Computer (RISC).
⚫The first ARM processor was developed at Acorn
Computers Limited, of Cambridge, England, between
October 1983 and April 1985. It is very simple
architecture.
⚫At that time, and until the formation of Advanced
RISC Machines Limited (which laterwas renamed
simplyARM Limited) in 1990, ARM stood for Acorn
RISC Machine
3. ⚫Second, both ARM ISA and pipelinedesign areaimed
to minimize theenergyconsumption.
⚫Third, the ARM architecture is highly modularonly
mandatorycomponent of ARM processor is the integer
pipeline, others areoptional. Thisgives more
flexibility in application dependentarchitecture
4. Revision Example
core
implementa
tion
ISA Enhancement
ARM v1 ARM1 • First ARM Processor
• 26bitaddressing
ARMv2 ARM2 • 32bitmultiplier
•32bit
coprocessor
support
ARMv2a ARM3 • Onchipcache
• Atomicswap instruction
•Coprocessor 15 forcache
management
ARMv3 ARM6and ARM7DI • 32 bitaddressing
•Separatecpsr
(current Program
status register)and
spsr (Saved program
status register)
•New modes
undefined instruction
and abort
•MMU
support(Memory
Management Unit)
5. ARMv3M ARM7M Signedand un
signed long
multiply
instruction
ARMv4 Strong ARM •loadstore
instructions for
signed half
words/bytes
•Reserve
SWI(software
interrupt) space fro
architecturallydefine
operations.
•26 bitaddressing
mode no longer
supported
ARMv4T ARM7TDMIand ARM9T • Thumb
ARMV5TE ARM9E AND ARM10E • Supersetof ARM
•Enhanced
multiply
instructions
•Extra
DSPtype
instructio
n
•Faster
multiply
instructio
n
7. ARM processor Features
Terms Extention
X Familyorseries
Y MemoryManagement
Z Cache
T 16bitthumbdecoder
D Jtag Debugger
M Fast multiplier
I Embedded Incircuit Emulator
E Enhanced Instruction for DSP
J Jazelle
F Vector floating pointunit
S Synthesizableversion
8. ARM 7family
⚫ARM7 core hasavon neumann stylearchitecture
⚫ARM7 TDMI is first processor introduced in 1995 by
ARM
⚫It provideaverygood performance to powerratio
⚫ARM7TDMI-S has the synthesizable
⚫ARM720T is the most fexible member of ARM7 family
because it include MMU. MMU handle both platforms
Linuxand windows
⚫It having unified 8k cache and vector table are
relocated depend on the priority
10. ARM9 family
⚫The ARM9 familywas announced in 1997
⚫ARM9 has five stage pipelineand high clock
frequencies
⚫Memory have been redesign Harvard architecture
⚫ARM9 process includescacheand MMU
⚫Operating system requiring virtual memory support
⚫ETM (Embedded Trace Macrocell) which allows a
developer to trace instruction and data execution in
real timeoperation. So thatdebugging is doneduring
thecritical time segments.
⚫
11. ⚫ARM946E-S includeTCM, cache and MPU. The size
of the TCM and cacheareconfigurable
⚫The processor is designed for theembedded control
application that require deterministic real time
response
⚫ARM926EJ-S synthesizableprocessorcore, announced
in 2000
⚫It isa javaenabledevice such as 3G phones and
personal digital assistant
12. ARM10 FAMILY
⚫The ARM10 announced in 1997 was designed for
performance
⚫Itextended version of 6 stage pipeline
⚫Vectorfloating point unitwhich addsa seventh stage
to the ARM10 pipeline
⚫VFP combined with IEEE 754.1985 floating point
⚫ARM1020 E it includes E instruction. it having cache,
VFP and MMU
⚫ARM1026EJ-S is similarto ARM926EJ-S . But ARM10 is
flexible when compare toARM9
13. ARM11
⚫ARM1136J-S, announced in 2003 wasdesigned for high
performanceand powerefficientapplications
⚫ARM1136J-S was the first processortoexecute
architecture ARMv6 instructions
⚫It has eight pipelinestages with load and store
arithmeticpipeline.
⚫ARMv6 instruction are single instruction with
multipledataextensions for mediaprocessing.
14. ⚫2.2 ARM PROCESSORS
⚫ARM Processorcan be divided into three types
⚫ARM classic processor
⚫ARM Embedded Processor
⚫ARM Applicationprocessor
18. 2.3 ARM ARCHITECTURE
⚫Thearchitecture has evolved overtime, and starting
with cortex series of cores, three profilesare,
⚫Application Profile Cortex- A series
⚫Real time profile- Cortex- R series
⚫Microcontrollerprofile-Cortex –M series
2.3.1 Arm Features
⚫A load-storearchitecture,
⚫Fixed-length 32-bit instructions
⚫3-Address instruction formats.
19. ⚫It has 32 bitarchitecture but it supports to 16bitand 8
bitdata typesalso
⚫A widechoiceof development tools and simulation
models for leading EDA (Electronic Design
Automation) environments and excellent debug
support
⚫ARM uses a Intelligent Memory Manager (IEM). It
implementsadvanced algorithms tooptimally balance
processorworkload and powerconsumption.IEM work
with operating systemand mobile OS
⚫ ARM uses AHB (AMBA Advanced High performance
Bus) interface. AMBA is open source specification for
on chip interconnection
⚫
22. 2.3.2 ARM ARCHITECTURE
⚫ARM core has functional unitsconnected bydata
buses.
⚫Arrow represents the flow of data.
⚫Lines represent buses.
⚫Boxes representeitheroperation unit orstoragearea
⚫Design of ARM is simpleand Programmer’sdesign.
⚫Flexibledesign fordifferentapplication with simple
changes
⚫Instruction Pipelineand Read Data Registerare 32 bit
23. ⚫ARM instructions have two registers:
⚫Rm, Rn- source register
⚫Rd-destination register.
⚫Address bus line A(31:0) and data in lines DATA (31:0)
tostore thedata into the register.
⚫Address Register holds theaddress of next instruction
/ data to be fetched
⚫Address Incrementer the address register value to
appropriateamount to point the next instruction/ data
⚫Itcontains 31 Register bank, each registerare 32 bit
registersand alsocontains 6 status registers each of 32
bits
24. and applications.
2.3.3CPU Modesof ARM:
⚫User mode: It is used for programs
It isa only non privileged mode.
⚫System Mode: It is a special version of user mode. It
allows the full read write access to the CPSR.
⚫Supervisor Mode: it is privileged mode it enters
whenever the processorget resetor SWI instruction is
executed. In this mode OS kernel operates in.
⚫Abort Mode: Itoccurs when there isa failed attempt
toaccess the memory. This mode is entered when
prefetchabortand dataabortexception occurs.
25. ⚫Undefined mode: it is used when the processor
encountered an instruction that is undefined or not
supported by the implementation. It is a privileged
mode.
⚫Interrupt Mode: It is a privileged mode. When the
processoraccepts the IRQ itoccurs.
⚫Fast InterruptMode : It isa privileged mode. When
the processoraccepts the IRQ itoccurs.
⚫HYP Mode: This mode introduced in the ARMV-7A
fir cortex- A15 processor to providing hardware
virtualizationsupport.
26. The Current Program Status
Register (CPSR)
⚫Itgives the statusof ALU result foreveryexecution
⚫The CPSR is used in user-level programs tostorethe
condition code bits.
⚫Example, to record the result of a comparison
operation and tocontrol whetheror nota conditional
branch is taken
27. ⚫N: Negative; the last ALU operation which changed the
flags produced a negativeresult
⚫Z: Zero; the last ALU operation which changed the flags
produced a zero result (every bit of the 32-bit result was
zero).
⚫ C: Carry; the last ALU operation which changed the flags
generated a carry-out, either as a result of an arithmetic
operation in the ALU or from the shifter.
⚫ V: oVerflow; the last arithmetic ALU operation which
changed the flags generated an overflow into the sign
bit.
34. Types of instruction set
⚫Data Processing Instructions
⚫Branch Instructions
⚫Load Store Instructions
⚫Software interrupt Instructions
⚫Program Status Register Instructions
37. The Barrel Shifter
⚫The ARM doesn’t haveactual shift instructions.
⚫Instead it has a barrel shifter which provides a
mechanism to carry out shifts as part of other
instructions.
⚫Barrel Shifter - Left Shift
⚫Shifts left by the specified amount (multiplies by
powersof two)
⚫e.g.
LSL #5 = multiply by 32
38. Barrel Shifter - Left Shift
Logical Shift Left (LSL)
Destination
CF 0
39. Logical Shift Right
•Shifts right by the
specified amount (divides
by powersof two) e.g.
LSR #5 = divide by 32
Barrel Shifter - Right Shifts
Destination CF
Logical Shift Right
...0
Arithmetic Shift Right
•Shifts right (divides by
powersof two) and
preserves thesign bit, for
2's complement
operations. e.g.
ASR #5 = divide by 32
Destination CF
Arithmetic Shift Right
Sign bit shifted in
40. Barrel Shifter - Rotations
• Rotate Right (ROR)
Similar to an ASR but the bits wrap
around as they leave the LSB and
appear as the MSB.
• e.g. ROR #5
•Note the last bit rotated is also
used as the Carry Out.
•Rotate Right Extended (RRX)
•This operation uses the CPSR C
flag as a 33rd bit.
•Rotates right by 1 bit. Encoded
as ROR #0.
Destination CF
Rotate Right
Destination CF
Rotate Right through Carry
56. Stacks and Subroutines Stacks are highly flexible in the ARM architecture.
In the ARM processor, any one of the general purpose registers could be used as
a stack pointer.
Stack instructions : The ARM instruction set does not contain any stack
specific instructions like push and pop. The instruction set also does not enforce
in anyway the use of a stack. Push and pop operations are performed by memory
access instructions, with auto-increment addressing modes.
Stack pointer : The stack pointer is a register that points to the top of the stack.
In the ARM processor, there are no dedicated stack pointer registers, and any
one of the general purpose registers can be used as the stack pointer.
Stack types : Since it is left to the software to implement a stack, different
implementation choices result different types of stacks.
There are two types of stack depending on how the stack grows.
Ascending stack : In a push the stack pointer is incremented, i.e the stack grows
towards higher address.
Descending stack : In a push the stack pointer is decremented, i.e the stack
grows towards lower address.
57. There are two types of stack depending on what the stack pointer points to.
Empty stack : Stack pointer points to the location in which the next item will be
stored. A push will store the value, and increment the stack pointer.
Full stack : Stack pointer points to the location in which the last item was stored. A
push will increment the stack pointer and store the value.
Four different stacks are possible : Full-ascending, full-descending, empty
ascending, empty-descending.
All four can be implemented using the register load store instructions.
A subroutine is a reusable program module. A main program can call or jump to the
subroutine one or more times. The stack is used in several ways when subroutines
are called.
62. ⚫The LPC2148 is a 16 bitor 32 bit ARM7 family based
microcontroller and available in a small LQFP64
package.
⚫ISP (in system programming) or IAP (in application
programming) using on-chip boot loadersoftware.
⚫On-chip static RAM is 8 kB-40 kB, on-chip flash
memory is 32 kB-512 kB, thewide interface is 128 bit,
oracceleratorallows 60 MHz high-speed operation.
⚫It takes 400 milliseconds time forerasing thedata in
full chip and 1 millisecond time for 256 bytes of
programming.
63. ⚫Embedded Trace interfaces and Embedded ICE RT
offersreal-timedebugging with high-speed tracing of
instruction execution and on-chip Real Monitor
software.
⚫It has 2 kB of endpoint RAM and USB 2.0 full speed
device controller. Furthermore, this microcontroller
offers 8kB on-chip RAM nearby to USB with DMA.
⚫One or two 10-bit ADCs offer 6 or 14 analogs i/ps with
lowconversion timeas 2.44 μs/ channel.
⚫Only 10 bit DAC offers changeable analog o/p.
⚫External eventcounter/32 bit timers-2, PWM unit, &
watchdog.
⚫Low power RTC (real timeclock) & 32 kHz clock
input.
64. ⚫Several serial interfaces like two 16C550 UARTs, two
I2C-buseswith 400 kbit/s speed.5 volts tolerant quick
general purpose Input/outputpins in a small LQFP64
package.
⚫Outside interruptpins-21.60 MHz of utmost CPU
CLK-clockobtainable from the programmable-on-chip
phase locked loop by resolving time is 100 μs.
⚫The incorporated oscillatoron thechipwill work byan
exteriorcrystal that ranges from 1 MHz-25 MHz
⚫The modes for power-conserving mainlycomprise idle
& powerdown.
⚫Forextra poweroptimization, thereare individual
enable or disable of peripheral functions and
peripheral CLK scaling.
66. ⚫Embedded systems that interacts with the outside
world, needs some peripheral device. A peripheral
device performs input and output functions for the
chip byconnecting tootherdevices orsensors thatare
off chip.
⚫Each peripheral device performs one function from
outsideof chip. Peripheral range is from simpleserial
communication tocomplex 802.11 wireless devices.
⚫All ARM peripherals are memory mapped. It has setof
addressed registers. This address registers used to
selecttheexact peripheral deviceaddress
67. Controllers-Specialized peripherals for higher level functionality. Its two
typesare,
⚫ Memorycontrollers.
⚫ Interruptcontrollers.
Memorycontrollers:
⚫ Connectdifferenttypesof memory to the processor bus.
⚫ On- power-upa memorycontroller is configured in hardwaretoallow
thecertain memorydevices to beactive.
⚫ Some memorydevices must beset up by software.
Interruptcontrollers:
⚫ Whena peripheral device requires a attention it raises the interrupt to
the processor.
⚫ The interruptcontroller provides the programmablegoverning policy
that allows the software to determine which peripheral device can
interrupt the processor at specific time. This is done by bits in the
interruptcontrollerregister.
68. Twotypesof interruptcontrollers forARM:
⚫ The Standard interruptcontroller.
⚫ TheVectorinterruptcontroller(VIC).
The Standard interruptcontroller:
⚫ Itsends the interruptsignal to the processorcore, when an external
devicerequestsservicing.
⚫ Itcan be programmed to ignoreor mask otherindividual deviceorset
of devices.
⚫ The interrupt handlerdetermineswhich device requires toservicing by
reading adevice bitmap register in the interruptcontroller.
TheVectorinterruptcontroller(VIC):
⚫ It is powerful than Standard interrupt controller. It has prioritizes
interrupts. Sodeterminationof which devicecaused the interrupt is
simple.
⚫ TheVIC only allowsan interruptsignal to thecore if the new higher
prioritycamethan currently executing interrupt.
72. Timer is a specific type of clock which is used to measure the time intervals. It
provides/measures the time interval by counting the input clocks. Every timer needs a
clock to work. We can provide/measure any time interval if we know the time of one
clock period.
e.g. Let’s say we have 1 kHz input clock frequency for the timer unit, then,
We can calculate time of one clock period as,
Time of one clock period = 1 / clock frequency
= 1 / 1000
= 1millisecond
i.e. 1000 clock counts provide a time interval of 1 second, and hence we can provide 1
second delay with these 1000 clock counts.
73. Counter is the unit which is similar to Timers but works in a reverse manner to
the timers. It counts the external events or we can say external clock ticks. It is
mostly used to measure frequency from the counts of clock ticks.
e.g. Let’s say Counter is measuring counts of external clock ticks, and frequently
its count reaches 2000 in one second i.e. 2000 clock ticks/second.
Then, we can calculate external clock frequency as,
External clock frequency = count of clocks / one second
= 2000 / 1
= 2 kHz
Hence, we can measure such external clock/event frequencies using counter.
There are many applications for which we can use these timers and counters in
real world.
74. LPC2148 Timer& Counter
LPC2148 has two 32-bit timers/counters:Timer0/Counter0 & Timer1/Counter1.
LPC2148 Timer has input of peripheral clock (PCLK) or an external clock. It
counts the clock from either of these clock sources for its operation.
LPC2148 Timer/Counter can generate an interrupt signal at specified time
value.
LPC2148 has match registers that contain count value which is continuously
compared with the value of the Timer register. When the value in the Timer
register matches the value in the match register, specific action (timer reset, or
timer stop, or generate an interrupt) is taken.
75. Timer0 Registers
1. T0IR (Timer0 Interrupt Register)
It is an 8-bit read-write register.
Consists of 4 bits for match register interrupts and 4 bits for compare register
interrupts.
If interrupt is generated, then the corresponding bit in this register will be high,
otherwise it will be low.
Writing a 1 to any bit of this register will reset that interrupt. Writing a 0 has no effect.
T0IR (Timer0 Interrupt Register)
76. . T0TCR (Timer0 Timer Control Register)
It is an 8-bit read-write register.
It is used to control the operation of the timer counter.
T0TCR (Timer0 Timer Control Register)
Bit 0 – Counter Enable
0 = Counters are disabled
1 = Timer counter and Prescale counter are enabled for counting
Bit 1 – Counter Reset
0 = Counter not reset
1 = Timer counter and Prescale counter are synchronously reset on next positive edge
of PCLK
81. Register Associated with UART
in LPC2148
⚫UART0 Receiver Buffer Register(U0RBR)
⚫UART0 Transmit Holding Register(U0THR)
⚫UART0 Divisor Latch Register (U0DLL and U0DLM)
Determine the baud rate generator (U0DLL /
U0DLM). (0x00:00x01)
⚫UART0 Fractional dividerregister (U0FDR)
⚫It is used for prescale for the baud rate
⚫Both Multiply and Divisioncan be done in prescale
⚫Bit 0 – 3 used for prescale divisorvalue for baurd rate
⚫Bit 4 -7 used multipliervalue
82. ⚫UART0 Interrupt Enable Register(U0IER)
0 bit- RBR (Receiver buffer Register)interrupt
1 bit- Interrupt enable register
2 bit- Rx line status register
8 bit – End of auto baud rate interrupt
9 bit- auto baud timeout interrupt
⚫U0LCR (UART0 Line Control Register)
⚫Bit 1:0 - Word Length Select
00 = 5-bit character length
01 = 6-bit character length
10 = 7-bit character length
11 = 8-bitcharacter length
83. ⚫ Bit 2 - Numberof Stop Bits
0 = 1 stop bit
1 = 2 stop bits
⚫ Bit 3 - Parity Enable
0 = Disableparitygeneration and checking
1 = Enableparitygeneration and checking
⚫ Bit 5:4 - Parity Select
00 = Odd Parity
01 = Even Parity
10 = Forced “1” Stick Parity
11 = Forced “0” Stick Parity
⚫ Bit 6 - Break Control
0= Disablebreak transmission
1 = Enable break transmission
⚫ Bit 7 - Divisor Latch Access Bit (DLAB)
0 = Disableaccessto Divisor Latches
1 = Enableaccess to Divisor Latches
84. Register)
⚫ Itprovides status informationon UART0 RX and TX blocks.
⚫ Bit 0 - ReceiverData Ready
0 = U0RBR isempty
1 = U0RBR containsvalid data
⚫ Bit 1 - Overrun Error
0 = Overrun errorstatus inactive
1 = Overrun errorstatusactive
This bit iscleared when U0LSR is read.
⚫ Bit 2 - Parity Error
0 = Parityerrorstatus inactive
1 = Parityerrorstatusactive
This bit iscleared when U0LSR is read.
85. ⚫ Bit 3 - Framing Error
0 = Framing errorstatus inactive
1 = Framing errorstatusactive
This bit iscleared when U0LSR is read.
⚫ Bit 4 - Break Interrupt
0 = Break interruptstatus inactive
1 = Break interruptstatusactive
This bit iscleared when U0LSR is read.
⚫ Bit 5 - TransmitterHolding Register Empty
0 = U0THR hasvalid data
1 = U0THR empty
⚫ Bit 6 - Transmitter Empty
0 = U0THR and/orU0TSR contains valid data
1 = U0THR and U0TSR empty
⚫ Bit 7 - Error in RX FIFO (RXFE)
0 = U0RBR contains no UART0 RX errors
1 = U0RBR contains at leastone UART0 RX error
This bit iscleared when U0LSR is read
86. Register)
⚫ The U0TER enables implementation of software flow control. When
TXEn=1, UART0 transmitterwill keepsending dataas long as theyare
available. As soonas TXEn becomes 0, UART0 transmissionwill stop.
⚫ Software implementing software-handshaking canclearthis bitwhen
it receivesan XOFF character (DC3). Software can set this bit again
when it receivesan XON (DC1) character.
⚫ Bit 7 : TXEN
0 = Transmissiondisabled
1 = Transmissionenabled
⚫ If this bit is cleared to 0 while a character is being sent, the
transmissionof thatcharacter is completed, but no furthercharacters
aresent until this bit is setagain
U0TER (UART0 Transmit Enable
98. LPC 2148
⚫It consistof 32 timer /counter ie PWMTC
⚫Counter count thecycles of peripheral clock(PCLK)
⚫It having 32bit prescale register (PWMPR)
⚫It having 7 matching register (PWMR0-PWMR06)
⚫6 different pwm signal in single edgecontrolled pwm
or 3 different pwm signal in doubleedgecontrolled
pwm
⚫Match register will match and then itwill reset the
timer/counter orstop.
99.
100.
101.
102. PWM Registers
1.PWMIR (PWM Interrupt Register)
•It has 7 interrupt bits corresponding to the 7 PWM
match registers.
•If an interrupt is generated, then the corresponding bit
in this register becomes HIGH.
•Otherwise the bit will be LOW.
•Writing a 1 to a bit in this register clears that interrupt.
•Writing a 0 has no effect.
103. 2. PWMTCR (PWM Timer Control Register)
⚫It is an 8-bit register.
⚫It is used to control the operation of the PWM Timer Counter.
⚫Bit 0 – Counter Enable
When 1, PWM Timer Counter and Prescale Counterare enabled.
When 0, the counters are disabled.
⚫Bit 1 – Counter Reset
When 1, the PWM Timer Counter and PWM Prescale Counter are
synchronously reset on next positive edge of PCLK.
Counter remains reset until this bit is returned to 0.
⚫Bit 3 – PWM Enable
This bit always needs to be 1 for PWM operation. Otherwise PWM will operate
as a normal timer.
When 1, PWM mode is enabled and the shadow registers operate along with
match registers.
A write to a match register will have no effect as long as corresponding bit
in PWMLER is not set.
104. 3. PWMTC (PWM TimerCounter)
⚫ It isa 32-bit register.
⚫ It is incremented when the PWM Prescale Counter (PWMPC) reaches
its terminal count.
4. PWMPR (PWM Prescale Register)
⚫ It isa 32-bit register.
⚫ It holds the maximumvalueof the Prescale Counter.
5. PWMPC (PWM Prescale Counter)
⚫ It isa 32-bit register.
⚫ Itcontrols thedivisionof PCLK by someconstantvalue before it is
applied to the PWM Timer Counter.
⚫ It is incremented onevery PCLK.
⚫ When it reaches thevalue in PWM Prescale Register, the PWM Timer
Counter is incremented and PWM Prescale Counter is reset on next
PCLK.
105. 6. PWMMR0-PWMMR6 (PWM Match Registers)
⚫Theseare 32-bit registers.
⚫Thevaluesstored in these registers arecontinuously
compared with the PWM Timer Countervalue.
⚫When the twovaluesareequal, the timercan be reset
orstoporan interrupt may be generated.
⚫The PWMMCR controlswhataction should be taken
on a match.
7. PWMMCR (PWM Match Control Register)
⚫It isa 32-bit register.
⚫It controls what action is to be taken on a match
between the PWM Match Registers and PWM Timer
Counter.
106. Bit 0 – PWMMR0I (PWM Match register 0 interrupt)
0 = This interrupt is disabled
1 = Interrupt on PWMMR0. An interrupt is generated when PWMMR0
matches the value in PWMTC
Bit 1 – PWMMR0R (PWM Match register 0 reset)
0 = This feature is disabled
1 = Reset on PWMMR0. The PWMTC will be reset if PWMMR0 matches it
Bit 2 – PWMMR0S (PWM Match register 0 stop)
0 = This feature is disabled
1 = Stop on PWMMR0. The PWMTC and PWMPC is stopped and Counter
Enable bit in PWMTCR is set to 0 if PWMMR0 matches PWMTC
PWMMR1, PWMMR2, PWMMR3, PWMMR4, PWMMR5 and PWMMR6
has same function bits (stop, reset, interrupt) as in PWMMR0.
107. ⚫Bit 2 – PWMSEL2
0 = Single edge controlled mode for PWM2
1 = Doubleedgecontrolled mode for PWM2
⚫All other PWMSEL bits have similaroperation as
PWMSEL2 above.
⚫Bit 10 – PWMENA2
0 = PWM2 outputdisabled
1 = PWM2 outputenabled
⚫All other PWMENA bits have similaroperation as
PWMENA2 above.
108. 9. PWMLER (PWM Latch Enable Register)
⚫It isan 8-bit register.
⚫It is used tocontrol the update of the PWM Match Registers when they are
used for PWM generation.
⚫When a value is written to a PWM Match Register while the timer is in
PWM mode, the value is held in the shadow register. The contents of the
shadow register are transferred to the PWM Match Register when the
timerresets (PWM Match 0 event occurs) and if the corresponding bit in
PWMLER is set.
⚫Bit 6 – Enable PWM Match 6 Latch
Writing a 1 to this bit allows the last written value to PWMMR6 to
become effective when timer next is reset by the PWM match event.
⚫Similardescription as that of Bit 6 for the remaining bits.
109. ⚫ Resetand disable PWM counterusing PWMTCR
⚫ Load prescalevalue according to need of application in the PWMPR
⚫ Load PWMMR0 with avaluecorresponding to the time period of your
PWM wave
⚫ Load anyoneof the remaining six match registers (twoof the
remaining six match registers for double edge controlled PWM) with
the ON duration of the PWM cycle. (PWM will begenerated on PWM
pin corresponding to the match registeryou load thevaluewith).
⚫ Load PWMMCR with avalue based on theaction to be taken in the
eventof a match between match registerand PWM timercounter.
⚫ Enable PWM match latch forthe match registersused with the helpof
PWMLER
⚫ Selectthe typeof PWM wave (singleedgeordoubleedgecontrolled)
and which PWMs to beenabled using PWMPCR
⚫ Enable PWM and PWM counterusing PWMTCR
112. ⚫INTNMI- Non-maskable interrupt
⚫INTISR[239:0]- External interruptsignals
⚫SLEEPING- Indicates that the Cortex-M3 clock can be
stopped.
⚫SLEEPDEEP - Indicates that the Cortex-M3 clock can be
stopped
⚫WIC - Wake-up Interrupt Controller
⚫NVIC- Nested Vectored Interrupt Controller
⚫ETM- Embedded Trace Macrocell
⚫The ETM is an optional debug component that enables
reconstruction of program execution. The ETM is
designed to bea high-speed, low-powerdebug tool
that only supports instruction trace
113. ⚫MPU- Memory Protection Unit
⚫The MPU provides full support for:
⚫protection regions
⚫overlapping protection regions, with ascending
region priority:
⚫— 7 = highest priority
⚫— 0 = lowest priority.
⚫accesspermissions
⚫exporting memory attributes to the system.
114. ⚫FPB-Flash Patch and Breakpoint
⚫ unit to implement breakpointsand codepatches.
⚫DWT -Data Watchpointand Trace () unit to
implementwatchpoints, triggerresources, and system
profiling.
⚫ITM- Instrumentation Trace Macrocell for application-
driven trace source that supports printf style
debugging.
⚫TPIU- Trace Port Interface Unit
⚫it is an optional component that acts as a bridge
between the on-chip trace data from the Embedded
Trace Macrocell (ETM) and the Instrumentation Trace
Macrocell(ITM), with separate IDs, to a data stream,
encapsulating IDs where required, that is then captured
bya Trace Port Analyzer (TPA).
115. ⚫SW/SWJ-DP - SW-DP or SWJ-DP debug port
interfaces.
⚫Thedebug port providesdebug access toall registers
and memory in the system, including the processor
registers.
⚫The SW/SWJ-DP might not be present in the
production device if nodebug functionality is present
in the implementation.
