2. ARM Architecture
RISC Architecture
• Large Uniform register files
• Load and Store Architecture
• Simple Addressing modes
• Uniform and fixed length instruction fields
RISC + Enhanced feature = ARM
3. • It is an Advanced RISC Machine
• It is mainly used for commercial purpose
• Used in Video Games controllers, Wireless
Communication, MODEMs, Mobile phones and
Handy CAMs.
Features of ARM
• It has Architectural Simplicity.
• Each Instruction controls ALU and Shifting
• It has Auto Increment and Auto Decrement
Addressing Modes.
• Multiple Load and Store conditional execution
4. Results
• It has high performance
• Low Code Size
• Low power consumption
• Low Silicon area
5. • ARM has 32 bit Architcure in version 7
• 64 bit in version 8
ARM Data notation
• Byte – 8 bit
• Half word – 16 bit
• Word – 32 bit
• ARM has two instruction sets
• 32 bit instruction sets
• 16 bit thumb instruction sets
• It also uses JAVA byte code also called as JAZELLA
code
7. Registers in ARM
ARM has 37 Registers, each register is 32 bit long
They are as follows
Program Counter
CPSR – Current Program Status Register.
SPSR (5) – Save Program Status Register.
General purpose Register (30).
11. Thumb Architecture of ARM
• ARM supports three states of operation
• ARM default Operation
• ARM ‘Thumb’ Operation
• Jazelle Coding Operation
It uses Jave byte code
Above mentioned each operation have their own
instruction sets
CPSR has T-bit If T= 1 – It is a Thumb Operation
If T = 0 It is a ARM default operation
12. • Jazelle code mainly used for JAVA program operation, this
code increases the efficiency of operation.
• In CPSR when 24th bit = 1 then it means we are using Jazelle
code.
• In Thumb operation clock rate increases to 40 MHz
• Cache gets expanded to 8Kb
• In Thumb operation new 16 bit instruction set is used.
• It is hardwired logic unit.
• 16 bit instructions get translated to 32 bit instuction format.
• It is cleaver feature that has very little complexity.
• Thumb improves ARM instruction density b 25 % to 30%.
• In ARM operation when we run the application it would run
faster in Thumb operation than 32 bit normal ARM operation.
13. ARM Modes of Operation
It support two mode of operation
1. Previledged mode of operation
It is a powerful mode of operation as it has wide level of
access permission.
2.Non-Previledged mode of operation
It is not having that level of access permission.
There are total 7 modes of operation all of which falls
under any of these two modes of operation.
31. Syntax:
MUL{<cond>}{S} Rd, Rm, Rs Rd = Rm * Rs
MLA{<cond>}{S} Rd,Rm,Rs,Rn Rd = (Rm * Rs) + Rn
[U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := Rm*Rs
[U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs
RdHi,RdLo:=(Rm*Rs)+RdHi,RdLo
Cycle time
Basic MUL instruction
2-5 cycles on ARM7TDMI
1-3 cycles on StrongARM/XScale
2 cycles on ARM9E/ARM102xE
+1 cycle for ARM9TDMI (over ARM7TDMI)
+1 cycle for accumulate (not on 9E though result delay is one cycle
longer)
+1 cycle for “long”
Above are “general rules” - refer to the TRM for the core you are
using for the exact details
