Programmable Devices En 01

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The presentation is an introduction to the electronics programmable devices and VHDL programming

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Programmable Devices En 01

  1. 1. October 2005 October 2008 October 2012 “FPGA – CPLD Technologies and VHDL programming basics” Seminar Updated 2012 VersionTeodoro BOVE (Alstom) - Svetozar Jovanovic (Altran- Italia)
  2. 2. Programmable logic and VHDL programming SEMINAR SCHEDULE l 09.00-09.15 Welcome and coffee l 09.15-10.30 FPGA Technologies compared to previous generation of programmable devices like SPLD e CPLD l 10.30-10.45 Coffee Break l 10.45-13.00 Today FPGA scenario and ACTEL® PROAsic® APA devices family » for LO.RE railway vehicle RACK-BUS l 13.00-13.45 Lunch Break l 13.45-15.00 Introduction to VHDL programming l 15.00-15.30 Coffee Break l 15.30-17.00 Application example: FPGA for ETHERNET BUS interface board LO.RE l 17.00-17.30 Today trands and last news- technology evolutionDate of last change Reference/Name of Presentation/SN 2
  3. 3. FPGA technologies comparison to previous generation programmable devices SPLD and CPLD / history overview27-12-2008 FPGA-CPLD-VHDL Seminar 3
  4. 4. CPLD and FPGA, history resume • Gates volume • 1970-75 SPLD’s 22V10 PAL (22 INPUTS 11 OUTPUTS) • 1995 CPLD’s (5K Gates), FPGA’s 100K Gates) • 2005 CPLD’s (50K Gates), FPGA’s (2,5 Mgates) • 2008 CPLD’s (75K Gates), FPGA’s (5 Mgates) • 2012 FPGA’s (20 Mgates) • Configuration technology • 1970-75 EPROM, EEPROM, ANTIFUSE • 1990 / 1995 EEPROM, ANTIFUSE, SRAM • 1999 / 2012 EEPROM, ANTIFUSE, SRAM, FLASH27-12-2008 FPGA-CPLD-VHDL Seminar
  5. 5. CPLD e FPGA configuration bitstreaming The configuration operations of programmable devices is implemented switching stably the connection transistors, nowtimes the typical technologies are EEPROM, SRAM, FLASH, mainly through ISP (in circuit programming feature) and ANTIFUSE which is one time not-reversible configuration. The user logic cells of course are all in x-CMOS tech.27-12-2008 FPGA-CPLD-VHDL Seminar 5
  6. 6. CPLD ARCHITECTURE The CPLD architecture for example is as follows: Picture 8: PIA -Programmable interconnect array Picture 13: Global routing pool27-12-2008 FPGA-CPLD-VHDL Seminar 6
  7. 7. Macrocella CPLD CPLD typical logic macrocell structure (PIA = Programmable interconnect array)27-12-2008 FPGA-CPLD-VHDL Seminar 7
  8. 8. CPLD global aspects • The internal signals propagation time are predictable because the routing paths are all the same for all logic macrocells. Normally the typical delays are between 4 and 15 ns IN-OUT • The typical CPLD architecture is based on more macrocelles connected between them. Each macrocell is implemented with more integrated basic logic gates builded toghether, like happens in PLA/PAL SPLD (22V10 like) devices. All the macrocells are interconnected between them with a dedicated logic matrix • The CPLD common architecture is’ « typically not so much flexible », this on the other hand is also a their advantage because the internal signal delays are predictable : • The CPLD devices are « right tailored » for a some typical applications • The « LOGIC » volume of these devices is up-limited to 75K Gate • The typical applications are for instance various kind of « low level » interfaces, like BUS control signals, simple state machine, simple real time processing in applications without memory requirements, combinatorial functions27-12-2008 FPGA-CPLD-VHDL Seminar 8
  9. 9. Current FPGA-CPLD scenario and comparison between the FPGA ACTEL® PROASIC PLUS « APA « LO.RE project choice and competitor devices27-12-2008 FPGA-CPLD-VHDL Seminar 9
  10. 10. FPGA ARCHITECTURE This picture shows an example:27-12-2008 FPGA-CPLD-VHDL Seminar 10
  11. 11. FPGA logic element architecture27-12-2008 FPGA-CPLD-VHDL Seminar 11
  12. 12. Current FPGA overview Has been considered three FPGA devices providers / vendors: • XILINX® • ALTERA® • ACTEL® Some others was not considered only for practical reasons. Each one (independently by economical aspects) has its preferred market, is also true that they has different device architectural approach. This has the consequence that logic implementations are different.27-12-2008 FPGA-CPLD-VHDL Seminar 12
  13. 13. XILINX®, ALTERA®, ACTEL® All the mentioned FPGA providers are using different physical implementations (both architectural and technological) this means that same VHDL designs could produce better or less kind of performances. Specially what has a relevant impact on the overall FPGA performances, is the « connectivity capability» between its logic elements and the mean delay amount. This is resulting in : • timing performances • logic, routing and I/O resources saturation27-12-2008 FPGA-CPLD-VHDL Seminar 13
  14. 14. ALTERA® typical architecture This architecture is characterised by following morphoology : Altera : The LE logic elements are all grouped in the logic array blocks, for instance 8 or 16 with great connectivity between the macrocells which belongs to the same LE, the connectivity between different groups is demanded to relatively limited « cross highways » as shown below (this because certain amount of silicon area is filled by group of LE itself) :27-12-2008 FPGA-CPLD-VHDL Seminar 14
  15. 15. XILINX® typical architecture With a different approach, Xilinx prefer single LE, simplest macrocells blocks interconnected with a diffentiated stronger net, as shown below, which gives a very good connectivity and routing capability, the direct consequence is a benefit role in minimizing signals delay:27-12-2008 FPGA-CPLD-VHDL Seminar 15
  16. 16. ACTEL® typical architecture The Actel architecture approach follows the Xilinix « direction », but much more intensively : In practice the ACTEL® FPGA devices achieve a « granularity » up to a « quasi » ASIC level. The LE logic elements are simple, but with really impressive connectivity and routing capability between them, this imply a valuable benefit in terms of signals delay as shown below:27-12-2008 FPGA-CPLD-VHDL Seminar 16
  17. 17. Comparison about architecture approaches - ALTERA® devices architecture is typically aggregating LE the logic elements, in other words blocks of macrocells, the consequence is that are favored designs with highly concentrated logic and / or combinatorial complexity, on the other hand this approach may impact a global connectivity, and IN-OUT signal delay - XILINIX® devices architecture has a different approach, in practice, the major difference are: • Less aggregation of simplest LE logic elements • More resources dedicated to the connectivity and routing between LE. This may affect designs, the complexity is distributed over more LE, which are anyway connectable due to rich and differentiated routing resources. - ACTEL® devices as already mentioned about the logic elements LE they are the simplest compared to other two, this results in a high grade of “granularity”, the connectivity and routing resources are powerful and flexible, so these devices are ASIC like. The impact on designs is a large “spectrum” of implementable applications, high device usage efficiency. The other side of “medal” is that global application speed is limited.27-12-2008 FPGA-CPLD-VHDL Seminar 17
  18. 18. Comparing table for the LO.RE project 2005 FPGA COMPARE I/O I/O SPEED DEVELOPING QUOT. POWER PACK. TEC. VOLTAGE. PROG. COMMENTS TABLE FOR LORE PROJ. PINS NEC GRADE SYSTEM CONS. 208 GOOD ISE WEB / ISP EFFICiENT XILINIX SPARTAN 3 PQFP 141 DESKTOP 20$ + 3: 1.2V EXTERNAL ARCHITECTURE, HIGH VOLAT. XC3S200 173 MAX LIMITED FLASH 2.6V FLASH O R MEDIUM SPEED, MEDIUM SRAM 200KG 256 173 CLKIN MODELSIM PROG 3.4V PROM VIA COMPLEXITY LOGIC FBGA 280 MHZ 500$ JTAG ELEMENTS NEXT GEN. DEVICE MORE I/O 190 IN FBGA PACK, MAY BE INTERNAL SMALL INTERNAL FLASH XC3S500E DUE TO FLASH TECH. LIBERO IDE, VERY HIGH RELIABILITY 208 SUFFIC. SYNPLIFY, ISP ONE IN HARSH ACTEL PROASIC PLUS PQFP SYNTH, NON- TIME ENVIRONMENT HIGH APA 150 158 2: 2.5V VERY 173 MAX SIMULATORE 25$ VOLAT. PROGRAM GRANULARITY 150KG 186 3.3V LOW 256 CLKIN MODELSIM FLASH MING VIA ARCHITECTURE , FBGA 180 MHZ VHDL JTAG SIMPLE LOGIC CELLS, FREE OF RICH ROUTING CHARGE RESOURCES NEXT GEN. DEVICE REDUCED PROGRAMMING TIME 1 MIN. TO TEN SE. SMALL INTERNAL FLASH A3P400 VERY QUARTUS COMPLEX 240 GOOD TWO ISP ARCHITECTURE, HIGH PQFP LIMITED 27$ + EXTERNAL INTEGRATION LE ALTERA CYCLONE EP1C6 173 VOLAT. 2: 1.5V RELAT. 173 MAX EDITION FREE FLASH FLASH O R ELEMENTS, WELL 300KG 185 CLKIN SRAM 3.3V HIGH 256 OR FULL WITH PROG PROM VIA SUITED FOR COMPLEX FBGA 400 MHZ MODELSIM 2000 JTAG AND FAST $ APPLICATIONS NEXT GEN. DEVICE BETTER INTEGRATION ADDED DSP FUNCTIONS, ENHANCED POWER CONSUMPTION EP2C627-12-2008 FPGA-CPLD-VHDL Seminar 18
  19. 19. ACTEL® PROAsic PLUS® APA FPGA – Choice highlights: • For LO.RE project the choice has been finalised, resulting in ACTEL® FPGA APA150 device, considering the following aspects: • Higher I/O pin count, 186 in FBGA package – (183 used pin) • Properly tailored gate volume (150 Kgate) • Two operating voltages 2.5 V for core and 3.3 V for the I/O • Free of charge « LIBERO® » developing system Modelsim® included • Very low power consumption • No need external device for data retention • High reliability in hostile and harsh environment • Easy technical support, very well suited in Italy • Overall Logic elements architecture, well calibrated to the application27-12-2008 FPGA-CPLD-VHDL Seminar 19
  20. 20. FPGA-CPLD global aspects and conclusions A Looking back on previous considerations, comparing FPGA vs. CPLD we can state that: • The FPGA’s has shown generally speaking improved average density, and complexity, possibly driven by growing design integration demand of embedded SRAM memory, FLASH memory, processor cores, this isn’t case for CPLD • Nowtimes the FPGA devices are reaching 3,5 million gates • As « pro » for the CPLD, still the predictable signals delay is an advantage, that’s also one of the reasons because this devices has still their market • The case of FPGA’s is that there is still a unpredictability of signal delays, but the enormous gate avalaibility and connectivity and routing resources are partially compensating this aspect.27-12-2008 FPGA-CPLD-VHDL Seminar 20
  21. 21. FPGA-CPLD global aspects and conclusions B • About the EDA tools is interesting to observe that today a place and route process for a FPGA 1 MLN gate big, used at 90% and with the 95% fixed I/O, takes on a modern laptop something like 15 mins • In 1993 a FPGA 5K gate big used at 60% and 85% fixed I/O has been taking several hours to complete the place and route process, with 1 to 15 net left to be connected manually • So the EDA tools has been following in some way interleaved the technology in FPGA development and design, even that, today you can find in a current design pin to pin delays form 10 to 40 ns, this because the FPGA architectures has been improved but are still too much dependent from the origins • Today in the CPLD usage is still possible to obtain pin to pin delays contained in 5-15 ns range • For the reasons above, nowtimes in the FPGA are integrating dedicate I/O channels for high or very high frequency signals, for instance the standard JEDEC LVPECL signals, differential, LVDS or similar etc.27-12-2008 FPGA-CPLD-VHDL Seminar 21
  22. 22. FPGA-CPLD global aspects and conclusions C • Today the FPGA thanks also to HW languages VHDL,VERILOG, SYSTEM VERILOG are integrating as already mentioned above, variuous IP, embedded 16/32 bit processors realizing systems on chip « SoC », which are replacing sometimes a entaire HW boards belonging times ago • In conclusion we can say that FPGA and CPLD are not in competition at all, each one has its market • The very well known differences, are sharply separating their usage in applications. Very often in the same application you can find both FPGA and CPLD which are satisfying well different requirements: - FPGA for medium-high end designs - CPLD for low end designs, or special cases27-12-2008 FPGA-CPLD-VHDL Seminar 22
  23. 23. VHDL programming basics Each slide will be explained using also a simulation examples with « ACTIVE® VHDL » EDA tool27-12-2008 FPGA-CPLD-VHDL Seminar 23
  24. 24. Preface VHDL 93 (what is this ?) • Is a digital HW programming language (as VERILOG or SYS. VERILOG) • Is a IEEE standard IEEE®, the 93 is last version • Can be considered in some way higher level abstraction language compared to VERILOG • Is a parallel language, sometimes include sequential statements « C » like • The implementation statements can be inferred, or instantiated (see the following section « VHDL comments « A ») • The designs implemented as inferred pure VHDL source code, are portable over all HW platforms FPGA – CPLD in a vendor independent way • The designs implemented with instantiated statments are using vendor specific HDL macros, therefore are depending by them • Today there are a lot IP HDL open source or to pay as a package or netlist • In the following sections (see « Template VHDL ») you can see code examples27-12-2008 FPGA-CPLD-VHDL Seminar 24
  25. 25. Comments on VHDL section « A » • Is useful to clear a bit the concepts of INFRERENCE and INSTANTCE what they are in practice ? : • INSTANCE – is to insert in your VHDL code a statement which is referring to a « component » which is a separate file that contain a blind VHDL code, the statement in your code is « viewing » only the components inputs and outputs, that are usable in your code to interact with a component itself. The component usually is vendor own property. So very often in its EDA tools editions the vendors leave available for free a basic digital components, like counters, arithmetic functions, glue logic, logic functions etc. Of course its usage is very convenient because you don’t have to write the code for them, but your design is depending by specific HW platform • INFERENCE – see the next page27-12-2008 FPGA-CPLD-VHDL Seminar 25
  26. 26. Comments on VHDL section « A » continued • INFERENCE – means to write the VHDL code using the language primitives and instructions – key words, this is almost mandatory to complete whole design, because even you are using also a vendor components, then anyway you have to write the VHDL code to interface – intergrate it in your design. Is straightforward that you can write also your open source VHDL components and use it in your design. This approach has the advantage that your code ideally is portable on every HW platform regardless the vendor that you want to use27-12-2008 FPGA-CPLD-VHDL Seminar 26
  27. 27. VHDL code example27-12-2008 FPGA-CPLD-VHDL Seminar 27
  28. 28. Comments on VHDL section « B » • A very important concept is that every VHDL complete design (that has to be fit in a physical programmable device) is normally hierarchically organized. So the typical structure of a VHDL deign is a kind of « tree » of different files (extension *.vhd) : - top entity VHDL (device I/O visibility) - component 1 VHDL entity of component 1 - component 1a VHDL entity of component 1a - component 2 VHDL entity of component 2 - component 2a VHDL entity of component 2a The top entity VHDL is contained in a VHDL main file, on which appears as language structure which include all the I/O of device signals name, every one of them has its reference inside the main file-27-12-2008 FPGA-CPLD-VHDL Seminar 28
  29. 29. Comments on VHDL section « B » continued some of them have a reference to a sections limited at main file, others are « pointing » to one or more components, as shown in hierarchy tree shown above, in previous page. Another important aspect to highlight is the VHDL design testing. The VHDL testing is in pratice a simulation done with proper EDA tools. For instance two very popular EDA simulators are Moedlsim® and ACTIVE®. The simulation can be done at different level of programmable device design: 1) functional simulation, at VHDL code entry level 2) postsynthesis simulation at physical implementation level (see for instance a SYNPLIFY® synthsizer) 3) postlayout simulation after the place and route succesful process For more details see the examples that follows-27-12-2008 FPGA-CPLD-VHDL Seminar 29
  30. 30. Comments on VHDL section « B » continued As global knowledge, has to be pointed out, that every type of simulation is done « facing » two objects: - the whole VHDL design under test, with file that contains the « top entity » - the « testbench VHDL file » that contains also the top entity which is the « mirror » of VHDL design top entity. This file inlude all the statements that are stimulating top entity inputs The simulation EDA tool, « reads » both, merging properly the related signals, achieving the design under test outputs time evolving view, giving to user the opportunity to evaluate the signals behaviour. Follows the VHDL section « C », VHDL project design flow chart and project example.27-12-2008 FPGA-CPLD-VHDL Seminar 30
  31. 31. Comments on VHDL section « C » Here are shown some examples of VHDL language primitives and defines, assignements: Constants : constant NAME := integer 1000; Variables : signal, std_logic, std_logic_vector(n..0) for 1 or more bit, integer Control : if, then, else, elsif, endif, when-case, when others (like default in C), for, while Assignement : SWAP <= dir_cross; var <= ‘0’; Combinatorial : and, or, nand, not, xor etc. Comparing : = equal Rising clk edge capture : if (clock’event) and (clock=‘1’)27-12-2008 FPGA-CPLD-VHDL Seminar 31
  32. 32. VHDL design process Flow chart ACTIVE VHDL FPGA DESIGN VHDL TOOL PROCESS LIBERO ACTEL INTEGRATED TOOL SYTHESIS AND PHYSICAL W AVEFORM SHAPING MAPPING, VHDL TRANSLATION IN NETLIST PLACE AND ROUTE BLOCK DIAGRAM .EDN FILE SYNPLIFY TOOL BACKANNOTATION VHDL DESIGN ENTRY PROCESS (VHDL WARNING AND TIMING EXTRACTION) CHECK-OUT IF NECESSARY DESIGNER SYNTAX FIRST CHECK CONSTRAINT INJECTION, (FORMAL COMPILE) FLOORPLANNING POSTSYNTHESIS OPTIMISATION SIMULATION TESTBENCH SIMULATION POSTLAYOUT TIMING STIMULUS SYNTHESIS ANALYSIS DESIGNER PROCESSING POSTLAYOUT FUNCTIONAL SIMULATION CONSTRAINTS ENTRY SIMULATION BITSTREAM STAPL FILE COMPILE GENERATION FIRST EXAMPLE END SECOND FPGA PROGRAMMING EXAMPLE END27-12-2008 FPGA-CPLD-VHDL Seminar 32
  33. 33. A VHDL design project example l Project concept and wanted signals time evolution l Functional block diagram l VHDL code design l Testbench stimuli signal definitions l VHDL functional simulation l The VHDL entry and simulation has been done with EDA ACTIVE® VHDL tool27-12-2008 FPGA-CPLD-VHDL Seminar 33
  34. 34. Functional block diagram (for the other signals, the logic is the same) BUS SIGNAL GENERATOR 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK SET OUT BUS WR RESET SET OUT BUS ALE RESET WR ALE27-12-2008 FPGA-CPLD-VHDL Seminar 34
  35. 35. Wanted signals timing27-12-2008 FPGA-CPLD-VHDL Seminar 35
  36. 36. VHDL main file, top entity design included, first section27-12-2008 FPGA-CPLD-VHDL Seminar 36
  37. 37. VHDL main file, top entity design included, second section27-12-2008 FPGA-CPLD-VHDL Seminar 37
  38. 38. VHDL main file, top entity design included, third section27-12-2008 FPGA-CPLD-VHDL Seminar 38
  39. 39. VHDL main file, top entity design included, fourth section27-12-2008 FPGA-CPLD-VHDL Seminar 39
  40. 40. Component file flip_flop_sr.vhd first section27-12-2008 FPGA-CPLD-VHDL Seminar 40
  41. 41. Component file flip_flop_sr.vhd second section22-10-2012 FPGA-CPLD-VHDL Seminar 41
  42. 42. Testbench stimuli file tb_peripheral.vhd first section27-12-2008 FPGA-CPLD-VHDL Seminar 42
  43. 43. Testbench stimuli file tb_peripheral.vhd second section27-12-2008 FPGA-CPLD-VHDL Seminar 43
  44. 44. Testbench stimuli file tb_peripheral.vhd third section27-12-2008 FPGA-CPLD-VHDL Seminar 44
  45. 45. Functional simulation27-12-2008 FPGA-CPLD-VHDL Seminar 45
  46. 46. Application example: Project- VHDL design for a FPGA part of ETHERNET CONNECTIVITY board Each slide will be explained using also a design- simulation examples with « ACTEL® Libero® » EDA tool27-12-2008 FPGA-CPLD-VHDL Seminar 46
  47. 47. Board block diagram and FPGA interfacing C EEPROM GPIO TEST POINTS A SPI INTERF E LED E 232 N CAN PHYSICAL DRIVER C O VOLTAGE N MONITOR D SP TMS320F2812 16 BIT ADDR_DSP N AND RESET SECTION JTAG / ICE RS232 16 BIT ADDR_DSP 16 BIT DATA_DSP CONN 16 BIT DATA_DSP CTR_DSP SM SC LAN 91C111 T R R J45 C A AND CLK M AC + PHY O N B SECTION F LED U O N CTR_DSP_C LAN F E OSC OR ETH ER NET F C BUFFERED E C ONTROLLER T DESKEW ED R O LORE CLK S CTR_DX R S OSC L S E T R V O E A L ADDR_DX L M O 5 GENERAL PURPOSE CONNECTIONS TO LORE S R H E I PARI POW ER SUPPLY F FPGA BU S_SW ITC HER 16 BIT DATA_DX B T CTR_LORE SEC TION E U R S ADDR_LORE 16 BIT S +5V B +5 CTR_SX +3.3V A S C +2.5V T DATA_LORE 16 BIT K O R P A L +3,3 ISP ADDR_SX M A V PROGRAM M ING N E M INIFLAT CONN IL +5V ARRIVA DISPA RI +5V D AL BUS 16 BIT DATA_SX LORE27-12-2008 FPGA-CPLD-VHDL Seminar 47
  48. 48. Board and FPGA brief functional explanation In this application the FPGA has been set to be a interface a ETHERNET 10/100 Mbit for the “LORE” custom BUS, toghther with a DSP and LAN controller chip. The interface between the DSP and custom rack BUS backplane has been implemented through a double external SRAM buffer, configured in a “ping-pong” way. One of the main reasons for doubled SRAM implementation was to achieve a continous upstream and downstream data between DSP on the ETHERNET board and the RACK CPU. For example in downsteram process, the FPGA was charghed to take care that during the DSP writes in one of two SRAM, the RACK CPU was addressed to read from the other one SRAM. So the main FPGA function was to manage the handshake between the CPU and DSP, switching properly the data flowing through the SRAM double buffer. The following block diagram shows this: --27-12-2008 FPGA-CPLD-VHDL Seminar 48
  49. 49. BUS switch block diagram, rack LO.RE CPU—DSP via FPGA27-12-2008 FPGA-CPLD-VHDL Seminar 49
  50. 50. Switch BUS handshake testbench sequenceDate of last change Reference/Name of Presentation/SN 50
  51. 51. FPGA has been designed in fully integrated ACTEL tool « LIBERO »27-12-2008 FPGA-CPLD-VHDL Seminar 51
  52. 52. Below is shown the VHDL top entity in peripheral.vhd file27-12-2008 FPGA-CPLD-VHDL Seminar 52
  53. 53. VHDL component reg_gpio_bank declaration in the peripheral.vhd file27-12-2008 FPGA-CPLD-VHDL Seminar 53
  54. 54. VHDL component reg_gpio_bank instantation, DSP part27-12-2008 FPGA-CPLD-VHDL Seminar 54
  55. 55. VHDL component reg_gpio_bank instantation, BUS « LORE » part27-12-2008 FPGA-CPLD-VHDL Seminar 55
  56. 56. VHDL component reg_gpio_bank in the its file27-12-2008 FPGA-CPLD-VHDL Seminar 56
  57. 57. VHDL component reg_16_spec_1 in the reg_gpio_bank.vhd file27-12-2008 FPGA-CPLD-VHDL Seminar 57
  58. 58. DSP data read demultiplexing in periperhal.vhd file, for BUS LORE read there is another similar process27-12-2008 FPGA-CPLD-VHDL Seminar 58
  59. 59. Downstram and upstream state machine istance27-12-2008 FPGA-CPLD-VHDL Seminar 59
  60. 60. FPGA tool design choice27-12-2008 FPGA-CPLD-VHDL Seminar 60
  61. 61. FPGA syntax check each file27-12-2008 FPGA-CPLD-VHDL Seminar 61
  62. 62. FPGA design synthesis27-12-2008 FPGA-CPLD-VHDL Seminar 62
  63. 63. FPGA constraints27-12-2008 FPGA-CPLD-VHDL Seminar 63
  64. 64. FPGA physical design layout and routing27-12-2008 FPGA-CPLD-VHDL Seminar 64
  65. 65. Floorplanning (chip planner tool)27-12-2008 FPGA-CPLD-VHDL Seminar 65
  66. 66. FPGA postlayout simulation27-12-2008 FPGA-CPLD-VHDL Seminar 66
  67. 67. Conclusions A Today seminar had a goal to give a simple « window » to a programmable logic devices, alligned with state of art in this electronics field. Another objective was to introduce not experienced people to the HW programming, as example has been used the VHDL 93 language. Has been focused the VHDL highlight aspects, trying to give a real feeling with the « core » of code logic and developing. The main issues related to that was to point out : - advantage to have a portable HW language: for instance if one write a code for a special custom logic function component in inferenced way, according to a basic HW platform requirement, is possible to use it on a FPGA or even on an CPLD - the simulation, using VHDL is possible to create a virtually whatever complexity stimulus à27-12-2008 FPGA-CPLD-VHDL Seminar 67
  68. 68. Conclusions B Nowtimes the EDA tools has achieved very powerful performances, offering to a designers – architects, integrated suites to develop the whole digital implementation on a programmable chip, from CPLD to complex FPGA’s . Today are also available a lot of IP’s free or to pay, which make easy its integration in a design. The last trend is going towards to integrate also a various processors cores, pushing the integration of programmable devices at reasonable prices and high performances. One example is ALTERA® vendor, which has its « QUARTUS 2® » EDA which include several free IP, macros and the NIOS 2® 32 bit RISC processor. In that EDA is included a wizard guided tool « SOPC BUILDER » which is powerful graphical-to-VHDL generator. With this tool is relatively easy to build-up a single or multiprocessor platform mixed with rich library of IP’s and macros (UART, SPI, GPIO etc.). The tool is easy interacting with a NIOS EDA®, which is a developing, debug platform for C/C++ code which will run on a NIOS 2® processors, from this EDA you can write a code and then simulate it with Modelsim® running the code on NIOS 2 together with its peripherals.27-12-2008 FPGA-CPLD-VHDL Seminar 68
  69. 69. Conclusions C The purpose of this seminar – presentation was not intended to approach a comparison between ASIC and/or programmable devices, even now is also possible to develop on a programmable device entaire application and do the “hardcopy” on a silicon getting a wanted ASIC tested chip. Even what sentenced above, is clear that in some way the end performances “distance” between a programmable devices and ASICs, today is not so big as in relatively past times.27-12-2008 FPGA-CPLD-VHDL Seminar 69
  70. 70. www.altran.comwww.alstom.com

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