AN EFFICIENT DSP ARCHITECTURE DESIGN IN FPGA USING LOOP BACK ALGORITHM

J.Nasreen Fathima et al., International Journal of Advanced Research in Innovative Discoveries in Engineering and
Applications[IJARIDEA]
Vol.2, Issue 2,27 April 2017, pg. 55-66
© 2017, IJARIDEA All Rights Reserved
55
AN EFFICIENT DSP ARCHITECTURE DESIGN
IN FPGA USING LOOP BACK ALGORITHM
J.Nasreen Fathima1
, K.RenugaDevi2
1
M.E student, 2
Teaching Fellow
1,2
Department of Electronics Engineering, Madras Institute of Technology,
Anna University, Chennai-600044, India
1
Fathimameera35@gmail.com
Abstract— Advanced flag processors assume a noteworthy part in electronic gadgets, bio restorative applications,
correspondence conventions. Effective IC configuration is a key variable to accomplish low power and high throughput
IP center improvement for convenient gadgets. Computerized flag processors assume a huge parts progressively figuring
and preparing yet region overhead and power utilization are real disadvantages to accomplish productive outline
requirements. Adaptable DSP engineering utilizing circle back calculation is a proposed way to deal with beat existing
outline limitations. For instance, plan of 8 point FFT engineering requires 3 phases for butterfly calculation unit that 48
adders and 12 multipliers prompts high power and territory utilization. To lessen range and power, Loop back calculation
is proposed and it requires 16 adders and 4 multipliers for general outline. Likewise outline of various DSP layouts like
FFT, First request FIR channel and Second request FIR channel is acquainted and mapping in with the design as
preparing component and applying the circle back calculation. In the outline of FFT,FIR formats adders, for example,
parallel prefix viper, move and include multiplier, baugh-wooley multiplier are utilized to break down effective plan of
DSP engineering. Recreation and examination of inactivity, territory, control productivity with the current structures are
happens utilizing model sim 6.4a and combine utilizing Xilinx 14.3 ISE.
Keywords— Baugh-UWooley Multiplier, Loop Back Algorithm, Parallel Prefix Adders.
I. INTRODUCTION
Advanced Signal Processors (DSP) are uncommon sort of chip with its engineering
improved for the computerized flag preparing application. So as to quicken the execution of
computerized flag processors DSP quickening agents can be utilized. Installed frameworks
utilize specific quickening agents enhancing execution and decrease vitality utilization
particularly in zones, for example, flag handling, video preparing, and correspondences. The
joining of heterogeneity through specific equipment quickening agents enhances execution
and diminishes vitality utilization. In spite of the fact that application-specific incorporated
circuits (ASICs) shape the perfect speeding up arrangement regarding execution and power,
their inflexibility prompts expanded silicon many-sided quality, as different instantiated
ASICs are expected to quicken different parts. Numerous specialists have proposed the
utilization of space specific coarse-grained reconfigurable quickening agents so as to build
ASICs' flexibility without significantly trading off their execution.
Calculations are connected to consolidate the usage of quickening agents that are utilized
freely to lessen the range. This approach[2] makes multi operational information ways for a
given arrangement of uses; be that as it may, only it doesn't give more prominent adaptability
as the client of such framework may wish to make extra applications. Adaptability can be
accomplished with the utilization of various sorts of operation layouts. A format might be
characterized as a particular equipment unit or a gathering of tied units. The execution of
DSP systems[1] is predominantly influenced by choices on the outline in regards to
assignment and engineering of number-crunching units. The plan of number-crunching parts
consolidating operations that share information, can prompt noteworthy execution change.
The work[2] for the most part concentrates on the implanted usage of effective and improved
quickening agent design for computerized flag processors to upgrade the execution. The vast

56
majority of the operations performed with the assistance of formats can be executed inside
the quickening agent module without meddling the center.
In this an elite compositional plan for the amalgamation of flexible equipment DSP
accelerators[1] by joining advancement procedures from both the design and number juggling
levels of reflection. In this they present a flexible information way design that adventures CS
improved layouts of fastened operations. The proposed architecture[1] contains flexible
computational units (FCUs), which empower the execution of an extensive arrangement of
operation layouts found in DSP pieces. The proposed quickening agent architecture[2]
conveys normal increases of up to 61.91% in territory postpone item and 54.43% in vitality
utilization contrasted with condition of-craftsmanship flexible information ways managing
efficiency toward scaled advancements. The quantity of computational unit is resolved at the
outline time in light of guideline level parallelism and region limitations forced by the
fashioner. The most appropriate FCU is chosen with the assistance of multiplexer
II. EXISTING METHOD DRAWBACKS
• In the current technique quickening agent configuration is by the layouts so the
formats are built with various multipliers and adders which expanded the
postponement, range and energy of the DSP processors.
• In the convey proliferation viper each opportunity to handle the following stage it
needs to sit tight for convey from the past stage this will expand the engendering
delay.
• Consumes more coherent elements(area) because of direct calculation design.
• Higher proliferation delay because of convey bypassing
• Due to the expanded components outline more static and dynamic power are devoured.
• DSP Processors are not improved
• Creation of more layouts which increment the general zone of the chip.
III. PROPOSED METHODOLOGY
The proposed work fundamentally concentrate on an effective execution of advanced design
for computerized flag processors to upgrade the execution. The majority of the operations
performed with the assistance of formats can be executed inside the quickening agent module
without meddling the processor. A format might be characterized as a specific equipment unit
or a gathering of fastened unit. An information stream diagram (DFG) is a chart which speaks
to an information conditions between various operations .In this productive layouts for DSP,
for example, FFT and FIR channels are mapped into engineering as preparing component. In
the mapped design Loop Back calculation is proposed to decrease the region, power and
gives the improved engineering. The proposed design is appeared in Fig.1.

57
Fig.1. Proposed DSP Architecture
The Proposed DSP Architecture consists of FCU as FFT, First order FIT, Second order
FIR,LB indicates the Loop Back algorithm.
IV.DSP TEMPLATES
DSP Templates used in this are FFT and First order FIR and Second order FIR.
A. FFT TEMPLATE:
The FFT involves separating the N points into smaller groups. We compute the first stage
with groups of two coefficients, yielding N/2 blocks, each computing the addition and
subtraction of the coefficients scaled by the corresponding twiddle factors (called a
“butterfly” for its cross-over appearance). These results are used to compute the next state of
N/4 blocks, which will then combine the results of two previous blocks (combining 4
coefficients at this point). This process repeats until we have one main block, with a final
computation of all N coefficients
Fig.2. Illustration of FFT stages for an 8-pt FFT

58
Fig.3. Illustration of FFT Template
In above Fig.2., we can see the different stages. In stage 1, there are 4 blocks, with one
butterfly-per-block. In stage 2, there are two blocks with 2 butterflies each; and finally, in
stage 3, there is only one block, combining all 8 coefficients with 4 butterflies.
B. FIR TEMPLATE
In processing, a finite impulse response (FIR) filter is a filter whose impulse
response (or response to any finite length input) is of finite duration, because it settles to zero
in finite time. This is in contrast to infinite impulse response (IIR) filters, which may have
internal feedback and may continue to respond indefinitely.
Fig.4. Illustration of FIR Filter
Fig.5. Illustration of FIR Template

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V. ELEMENTS USED IN DSP TEMPLATES
The adders used in the FFT and FIR templates are Carry Select Adder and Parallel Prefix
adders.
A. CARRY SELECT ADDER:
The convey select snake by and large comprises of two swell convey adders and a
multiplexer. Including two n-bit numbers with a convey select snake is finished with two
adders (in this manner two swell convey adders) keeping in mind the end goal to play out the
figuring twice, one time with the supposition of the convey in being zero and the other
accepting it will be one. After the two outcomes are figured, the right total, and in addition
the right do, is then chosen with the multiplexer once the right convey in is known. Whenever
variable, the piece size ought to have a deferral, from expansion inputs. The 4 bit and 8 bit
Carry Select Adder is appeared in Fig. 6.
Fig.6. Bit Carry Select Adder
B. PARALLEL PREFIX ADDER STRUCTURE
To determine the postponement of convey look forward adders, the plan of
multilevel-look forward adders or parallel-prefix adders can be utilized. The thought is to
process little gathering of middle of the road prefixes and after that find extensive gathering
prefixes, until all the convey bits are registered. These adders have tree structures inside a
convey figuring stage like the convey engender viper. Notwithstanding, the other two phases
for these adders are called pre-calculation and post-calculation stages.
In pre-calculation organize, each piece figures its convey create/proliferate and an
impermanent whole as in Equations. In the prefix organize, the gathering convey
create/proliferate signs are processed to shape the convey chain and give the convey into the
viper underneath. In the post-calculation arrange, the total and complete are finally delivered.
The complete can be precluded if just a total should be created. The general outline of
parallel-prefix structures is appeared in Fig.7., where a 8-bit case is delineated.
All parallel-prefix structures can be actualized with the conditions above, be that as it may,
Equation 4 can be translated in different ways, which prompts diverse sorts of parallel prefix
trees. For instance, Brent-Kung is known for its inadequate topology at the cost of more
rationale levels.

60
Fig.7. Eight Bit Parallel Prefix Structure
C. KOGGE STONE PREFIX TREE ADDER:
KSA is a parallel prefix shape convey look forward snake. It creates convey in time and is
broadly considered as the speediest viper and is generally utilized as a part of the business for
superior number-crunching circuits. In KSA, conveys are registered quick by processing
them in parallel at the cost of expanded.
The entire working of KSA[8] can be effectively understood by investigating it as far as
three particular parts are Pre preparing, Carry Look forward system and Post handling stages.
1.Pre processing: This step involves computation of generate and propagate signals
corresponding too each pair of bits in A and B. These signals are given by the logic equations
below:
pi = Ai xor Bi (1)
gi = Ai and Bi (2)
2.Carry look ahead network: This block differentiates KSA from other adders and is the
main force behind its high performance. This step involves computation of carries
corresponding to each bit. It uses group propagate and generate as intermediate signals which
are given by the logic equations below:
Pi,j = Pi,k+1 and Pk,j (3)
Gi,j = Gi,k+1 or (Pi,k+1 and Gk,j) (4)
3.Post processing: This is the final step and is common to all adders of this family (carry
look ahead). KSA structure [8] is shown in the Fig.9. It involves computation of sum bits.
Sum bits are computed by the logic given below:
Si = pi xor Ci-1 (5)

61
Fig.8.Eight Bit Parallel Prefix Structure
D. SHIFT AND ADDER MULTIPLIER:
The Multipliers utilized as a part of the FFT and FIR formats are Shift and Add Multiplier
and Baugh Wooley Multiplier.
The general engineering of the move and include multiplier is appeared in the figure 10
beneath for a 32 bit increase. Contingent upon the estimation of multiplier LSB bit, an
estimation of the multiplicand is included and aggregated. At each clock cycle the multiplier
is moved one piece to one side and its esteem is tried. On the off chance that it is a 0, then
just a move operation is performed. In the event that the esteem is a 1, then the multiplicand
is added to the gatherer and is moved by one piece to one side.
Fig.9. Multiplier Circuit
After all the multiplier bits have been tested the product is in the accumulator. The
accumulator is 2N (M+N) in size and initially the N, LSBs contains the Multiplier. The delay
is N cycles maximum.
E. BAUGH WOOLEY MULTIPLIER:
This is speediest increase strategy utilized for both marked and unsinged numbers. Baugh-
Wooley Two's compliment Signed multipliers is the best known calculation for marked
augmentation since it amplifies the normality of the multiplier and enable all the halfway
items to have positive sign bits. Baugh–Wooley strategy was produced to configuration
coordinate multipliers for Two's compliment numbers. When increasing two's compliment
numbers specifically, each of the incomplete items to be included is a marked number. In this
manner every fractional item must be sign reached out to the width of the last item to frame a
right entirety by the Carry Save Adder (CSA) tree. As per Baugh-Wooley approach, a

62
proficient strategy for adding additional sections to the bit network recommended to abstain
from having manage the contrarily weighted bits in the incomplete item framework.
Fig.10. Baugh Wooley Hardware Multiplier.
Baugh-Wooley Multiplier is utilized for both unsigned and s.igned number duplication.
Marked Number operands which are spoken to in 2's supplemented shape. Halfway Products
are balanced with the end goal that negative sign move to last stride, which thus boost the
normality of the duplication cluster.
Baugh-Wooley Multiplier works on marked operands with 2's supplement portrayal to
ensure that the indications of every single incomplete item are positive.The fundamental
preferred standpoint baugh wooley multiplier is quick increase strategy and utilized for both
marked and unsigned numbers. Baugh-Wooley0schemes turn into a range expending when
operands are more prominent than or equivalent to 32 bits.In this as opposed to subtraction
operation it utilizes 2 supplement.
Fig.11.Eight Bit Parallel Prefix Structure
Here are using fewer steps and also lesser adders. Here a0, a1, a2, a3& b0, b1, b2, b3 are
the inputs. I am getting the outputs that are p0, p1... p7. As I am using pipelining resister in
this architecture ,so it will take less time to multiply large number of 2’s compliment but
less than 32 bit. Above 32 bit Modified Baugh-Wooley Multiplier is used.

63
VI.LOOP BACK ALGORITHM
• Existing Existing 8 point FFT engineering is outlined utilizing butterfly graph and it
requires more adders and multipliers for 3 organizes in calculation.
• Carry Propagation adders and multipliers utilized as a part of existing engineering
requires more territory and deferral will be more.
• In proposed outline of various DSP layout a wide range of adders, for example,
convey select adders, parallel prefix adders and multipliers, for example, baugh
wooley and move and viper are utilized which decrease zone and in addition power
and postponement
• By lessening the quantity of stages in FFT and FIR design range will be diminished so
the circle back calculation is utilized
• Loop Back technique is proposed for math operations in SOC and DSP's for more
adaptable and fast number juggling rationale operations.
Fig.12. Block Diagram of Loop Back Algorithm
In this algorithm as shown in the figure 12 Iteration count gets the number of stages of
the FFT operation and selection switch is nothing but a mux which selects the input on the
register. Processing element is the FFT and FIR templates. Registers are used to store the
output of each stage from the processing element. [11] proposed a principle in which another
NN yield input control law was created for an under incited quad rotor UAV which uses the
regular limitations of the under incited framework to create virtual control contributions to
ensure the UAV tracks a craved direction. Utilizing the versatile back venturing method,
every one of the six DOF are effectively followed utilizing just four control inputs while
within the sight of un demonstrated flow and limited unsettling influences.
VII. SIMULATION RESULTS
Model Sim is a verification and simulation tool for VHDL, Verilog, System Verilog, and
mixed language designs. Before synthesize process we need to verify our design to check
every variables and logics that is loaded properly. Model sim is used for system level
verification where we can debug our modules through data’s obtained from waveform.
Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs,
which enables the developer to compile their designs, perform timing analysis, examine RTL
diagrams, simulate a design's reaction to different stimuli, and configure the target device
with the programmer.

64
Fig.13. Area Analysis of FFT with loop back
Fig.14. Power Analysis of FFT with loop back
Fig.15. RTL View of FFT with loop back
From the Figure 15 it shows that FFT with Loop Back is completed with single
butterfly stage as it has usually three butterfly stages so it reduces the no.of elements are
reduced hence area is decreased compared to existing FFT architecture.
Fig.16. Simulation Result of FFT with loop back

65
Fig.17. Area Analysis of FIR with loop back
Fig.18. Power Analysis of FIR with loop back
Fig.19. RTL View of FIR with loop back
VIII. CONCLUSION
From the Figure 15 it shows that FFT with Loop Back is completed with single butterfly
stage as it has usually three butterfly stages so it reduces the no. of elements are reduced
hence area is decreased compared to existing FFT architecture. In brief, an efficient DSP
architecture using Loop Back algorithm enables fast chaining of additive and multiplicative
operations is introduced. From the result analysis it is clear that the area can be reduced by
optimizing the architecture and incorporating the parallel adders and Baugh Wooley
multiplier.
TABLE I
COMPARISON TABLE OF FFT ARCHITECTURE

66
TABLE 2
COMPARISON TABLE OF FIR ARCHITECTURE
From the above Table I and Table II plainly demonstrates the quantity of components for
existing is more contrasted with the proposed calculation, With the Loop back calculation
territory of processors is diminished. As indicated by the investigation of energy both static
and dynamic power zone is expanded so that the warm power is expanded With the circle
back calculation control decreased which streamline the energy of the processor.
We separate from past deals with adaptable computational unit utilizing expansion and
subtraction it takes in additional equipment. Proposed Architecture shapes in Loop Back a
productive plan of DSP Acceleration and enhancing the zone, vitality utilization and decrease
the equipment. It abuses the consolidated components of the proposed units and empowers
quick calculations, high operation densities and propelled information reusability.
REFERENCES
[1] Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis, and Kiamal Pekmestzi “Flexible DSP Accelerator
Architecture Exploiting Carry-Save Arithmetic”., in IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 1, JANUARY 2016
[2] Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, and Costas E. Goutis,“A High Performance
datapath for Synthesizing DSP Kernels,” in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF
INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2015
[3] Linu M Jiji, Ragimol, "Embedded Implementation of Efficient Accelerator Architecture",2016 International
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[11] Christo Ananth,"A NOVEL NN OUTPUT FEEDBACK CONTROL LAW FOR QUAD ROTOR
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