IBM experts Girish and Chandu presented about A2O Core implementation on FPGA as part of JNTU A 2 DAYS Workshop . They covered the features of A2O core , how this core can be infused in FPGA

1. A2O core
implementation
on FPGA
Chandu Y & Girish Gopala Kurup
Logic Design
IBM Hardware Development Lab, Bangalore
IBM Hardware Development Lab

2. Background on A2O
´ A2O is developed using IBM Power ISA(Instruction Set Architecture)
´ Power ISA is RISC load/store architecture with multiple registers including
General Purpose Registers(GPU), Vector Scalar Register(VSR),Floating Point
Registers(FPR) , VRs, Condition Registers
´ Power ISA supports both Harvard architecture(split for data and instruction
caches) and Von Neumann architecture
´ It supports both big and Little-endian, 32 bit and 64 bit addressing, Memory
operation are strictly load/store, but allow for out-of-order execution
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3. POWER ISA books
Power ISA specs are divided into five parts called BOOKS
´ Book l - User Instruction Set Architecture – base instruction set
´ Book II - Virtual Environment Architecture – storage model
´ Book III - Operating Environment Architecture – Exceptions, Interrupts,
memory management
´ Book lll-S - supervisor instruction for the GPR/server implementation
´ Book lll-E - supervisor instruction for embedded applications
´ Book VLE - Variable Length Encoded Instruction Architecture
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4. Power Architecture Format
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5. POWER ISA Compliancy
´ A supporting/ compliant design must :
- Support Base architecture (never optional)
´ Support atleast one of the compliancy subsets:
- ACS: AIX compliancy subset
- LCS: Linux compliancy subset
- SFFS: Scalar fixed-point+ Floating-point compliancy subset
- SFS: Scalar Fixed-point compliancy subset
´ May utilize the combination of hardware and firmware
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6. POWER ISA overview
´ General: Byte reverse instructions, Vector integer multiply/Divide/Modulo
instructions, 128 bit Binary integer operations, VSX(vector scalar extension)
scalar minimum/maximum/compare- Quad precision
´ SIMD: VSX 32 byte storage Access operations, SIMD permute- class
operations, Bit-Manipulation operations VSX load/store Rightmost element
operations, VSX Mask manipulation operations, VSX PCV generate
operations for expand/compress
´ Pause/ wait reserve
´ Copy/ paste extensions
´ Hypervisor interrupt location control
´ Instruction Prefix support: 88 and modifying opcodes
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7. Prefix Architecuture
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8. A2O core organization
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RTL, documentation and FPGA environment available as
OpenPOWER
https://github.com/openpower-cores/a2o
Applications
-Artificial Intelligence
-Autonomous Driving
-Security

9. A2O POWER Processor Core
´ Design optimized for single thread performance over throughput
´ Balanced performance and power with modular design, VHDL RTL
A20 Design Feature
´ 64-bit PowerISA v2.07Book lll-E, 2Way SMT(Simultaneous Multi-Threading), 4W
fetch,2W dispatch,4W issue
´ Out-order dispatch/execution ,branch prediction(10K BHT)
´ L1:32KB 4Way IC, 32KB 8Way DC,64B line, Single cycle access, Stride prefetcher
´ 32-entry completion Buffer, 16-Entry LSQ(L/S quadword Instruction)
´ Modular design(1.MMU: 512 x 4 TLB, 4TB physical addressability(Memory
Management)
2.AXU :tightly coupled accelerator interface, 16B L/S
3. Microcode engine)
´ Full Support for both big – and little-endian byte ordering
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10. FPGA Build Process
´ The build process is made with reference to TCL, the scripts pick up the logic(Verilog RTL)
and build complete design
Step-1: checkout the git from https://github.com/openpower-cores/a2o
Step-2: define a variable VIVADO with the invoke of the vivado tool in
(VIVADO=<path> for linux)
Step-3:all the build need to be done inside build/ip_user with respective directory
Step-4: cat readme for all the directory, build RTL using TCL and follow(rev
Step-5:Once all the module are build, move to bd directory , followed by readme.md. Build
the complete design
Step-6:bring up the vivado gui interface and run the synthesis with the options
Step-7: The following would generate a bitstream for the FPGA
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11. IBM Hardware Development Lab

12. FPGA Board Design
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13. ´ ISA : https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf
´ ISA and Power10 : https://www.youtube.com/watch?v=imzUxijnv7M
´ Power10 : https://www.youtube.com/watch?v=27VRdI2BGWg
´ A2O : https://www.youtube.com/watch?v=Bz3tFvKTLxg
https://static.sched.com/hosted_files/openpowerna2020/39/Bill%20Flynn.pdf
https://www.youtube.com/watch?v=2IshMgIGCR4
´ A2I : https://www.youtube.com/watch?v=DshEFxTZd6I
´ https://github.com/openpower-cores/a2i - A2I (VHDL)
´ A2I user manual : https://wiki.alcf.anl.gov/parts/images/c/cf/A2.pdf
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Reference

14. Thank You!!!!!!!
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