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ZYNQ BRAM Implementation

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Vincent Claes
Vincent Claes

Howto Implement an AXI BRAM controller in Xilinx ZYNQ FPGAs Also included is a small tutorial about the C compilation process

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Vincent Claes
• Dual port memory with seperate Read/Write port • Can be excellent for FIFO implementation • Multiple blocks can be cascaded to create larger memory • Dual or single‐port memory • http://allaboutfpga.com/block‐ram‐and‐distributed‐ram‐in‐xilinx‐ fpga/ • Using On‐Chip Memory is faster then using Off‐Chip Memory, but On  Chip Memory is smaller in size then for instance Off‐Chip DDR Vincent Claes
• Configurable Logic Blocks configured as Distributed RAM • Single and Dual port • Cascaded LUTs to increase RAM size • Synchronous write and Synchronous/Asynchronous Read Vincent Claes
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• Double click on axi_bram_ctrl_0 block on Diagram Vincent Claes
• AXI BRAM  Controller; uses  AXI4 not AXI4 LITE  because BRAM can  provide higher  bandwidth and  the controller can  support burst transactions Vincent Claes
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• Number of jobs as high  as possible on your system Vincent Claes
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• Enabling the option “Include bitstream” allows us to program the FPGA from within the Xilinx SDK application Vincent Claes
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• Click Next >  Vincent Claes
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Vincent Claes Source  Code • IDE • .c file Pre‐ processor • Expanded  source  code Compiler • Assembly  Code • .s file Assembler • Object  code • .obj file Linker • Executable File • .elf file https://people.cs.pitt.edu/~xianeizhang/notes/Linking.html
Vincent Claes • gcc –E test.c –o test
Vincent Claes • gcc –S test.c –o test
Vincent Claes • objdump ‐s ‐‐disassamble test > test.dump
Vincent Claes • https://en.wikipedia.org/wiki/Executable_and_Linkable_Format • https://linux‐audit.com/elf‐binaries‐on‐linux‐understanding‐and‐ analysis/ •
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Vincent Claes BRAM DDR
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Vincent Claes
• vincent[at]cteq.eu • https://www.linkedin.com/in/vincentclaes/ • You can contact me for IoT, Embedded Systems (HW, SW, FPGA, ARM,  …) and ML/AI Projects (R and Python) • https://github.com/pxltech Vincent Claes

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