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Karnataka State Open University

(KSOU) was established on 1st June 1996 with the assent of H.E. Governor of Karnataka

as a full fledged University in the academic year 1996 vide Government notification

No/EDI/UOV/dated 12th February 1996 (Karnataka State Open University Act – 1992).

The act was promulgated with the object to incorporate an Open University at the State level for
the introduction and promotion of Open University and Distance Education systems in the

education pattern of the State and the country for the Co-ordination and determination of
standard of such systems. Keeping in view the educational needs of our country, in general, and
state in particular the policies and programmes have been geared to cater to the needy.

Karnataka State Open University is a UGC recognised University of Distance Education Council
(DEC), New Delhi, regular member of the Association of Indian Universities (AIU), Delhi,
permanent member of Association of Commonwealth Universities (ACU), London, UK, Asian
Association of Open Universities (AAOU), Beijing, China, and also has association with

Commonwealth of Learning (COL).

Karnataka State Open University is situated at the North–Western end of the Manasagangotri
campus, Mysore. The campus, which is about 5 kms, from the city centre, has a serene
atmosphere ideally suited for academic pursuits. The University houses at present the
Administrative Office, Academic Block, Lecture Halls, a well-equipped Library, Guest House

Cottages, a Moderate Canteen, Girls Hostel and a few cottages providing limited
accommodation to students coming to Mysore for attending the Contact Programmes or Term-
end examinations.

MC0062-1.1 Introduction to Number Systems
Introduction to Number Systems

The binary numbering system and the representation of digital codes with binary representation
are the fundamentals of digital electronics. In this chapter a comprehensive study of different
numbering systems like decimal, binary, octal and hexadecimal, are carried out. The conversion
and representation of a given number in any numbering system to other and a detailed analysis of
operations such as binary addition, multiplication, division and subtraction is introduced. Binary
subtraction can be carried out with the help of adder circuits using complementary number
system is been introduced. Special codes like BCD codes are introduced.

Objectives:

By the end of this chapter, reader is expected

• To have the complete understanding of the meaning and usefulness of numbering system.
• To carry the arithmetic operations such as addition, subtraction, multiplication and
division on binary, octal and hexadecimal numbers.
• To convert a given number converted to the different formats.

To explain the Usefulness of complementary numbering system in arithmetic, Binary coded
decimal (BCD) numbering systems.

MC0062-1.2 The Decimal Number System
The Decimal Number System

The Decimal Number System uses base 10 and represented by arranging the 10 symbols i.e. 0
through 9, where these symbols were known as digits. The position of each symbol in a given
sequence has a certain numerical weight. It makes use of a Decimal point.
The decimal number system is thus represented as a weighted sum representation of symbols.
Table 1.1 represents the weight associated with the symbol in decimal numbering system.

…. 10000 1000 100 10 1 • 0.1 0.01 0.001 ….
…. 104 103 102 1 0
10 10 Decimal point 10-1 10-2 10-3 ….

Table 1.1: Weights associated with the position in Decimal numbering system.

Example : 835.25 = 8 x 102 + 3 x 101 + 5 x 100 + 2 x 10-1 + 5 x 10-2

= 8 x 100 + 3 x 10 + 5 x 1 + 2 x 0.1 + 5 x 0.01

= 800 + 30 + 5 + 0.2 + 0.05

= 835.25

The left most digit, which has the highest weight, is called the most significant digit, and the right
most digit, which has the least weight, is called the least significant digit. The digits to the right
side of the decimal point are known as fractional part and the digits to the left side of the
decimal point are known as integer part.

Any number of zeros can be inserted to the left of most significant digit of integer part and to the
right side of the least significant digit of fractional part, which does not alter the value of the
number represented.

Self Assessment Question 1:

Represent the following decimal numbers with the associated weights

a) 1395 b) 7456 c) 487.46 d) 65.235

MC0062-1.3 The Binary Numbering System
The Binary Numbering System

The Binary Number System uses base 2 and represented by 0 and 1, these are known as bits also
as Binary Digits. The position of each bit in a given sequence has a numerical weight. It makes
use of a Binary point.
Thus binary number system can be represented as a weighted sum of bits. Table 1.2 represents
the weight associated in binary numbering system.

Equivalent weight in
…. 16 8 4 2 1 • 0.5 0.25 0.125 ….
decimal
Binary
Binary Powers …. 24 23 22 21 20 2-1 2-2 2-3 ….
point

Table 1.2: Weights associated with the position in Binary numbering system.

Example: 101.11(2) = 1 x 22 + 0 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2


Represent the following decimal numbers with the associated weights

a) 11001.111(2) b) 11.101(2) c) 11011(2) d) 0.11101(2)

Counting in Binary

Counting in binary is analogous to the counting methodology used in decimal numbering
system. The symbols available are only 0 and 1. Count begins with 0 and then 1. Since all the
symbols are exhausted start with combining two-bit combination by placing a 1 to the left of 0
and to get 10 and 11. Similarly continuing placing a 1 to the left again 100, 101, 110 and 111 are
obtained. Table 1.3 illustrates the counting methodology in binary systems.

Decimal Count Binary Count 5 bit notation
0 0 00000
1 1 00001
2 10 00010
3 11 00011
4 100 00100
5 101 00101
6 110 00110
7 111 00111
8 1000 01000
9 1001 01001
10 1010 01010
11 1011 01011
12 1100 01100
13 1101 01101
14 1110 01110
15 1111 01111
16 10000 10000
17 10001 10001
18 10010 10010
19 10011 10011
20 10100 10100
21 10101 10101
22 10110 10110

23 10111 10111
24 11000 11000
25 11001 11001
26 11010 11010
27 11011 11011
28 11100 11100
29 11101 11101
30 11110 11110
31 11111 11111

Table 1.3: illustrations for counting in Binary

Binary to Decimal Conversion

Weighted Sum Representation: A Binary Number is represented with its associated weights. The
right most bit, which has a value 20 = 1, is known to be Least Significant Bit (LSB). The weight
associated with each bit varies from right to left by a power of two. In the fractional binary
number representation, the bits are also placed to the right side of the binary point and the
equivalent decimal weights for the bit location are shown in Table 1.2. The value of a given
binary number can be determined as the weighted sum of individual weights.

Example: 101.11(2) = 1 x 22 + 0 x 21 + 1 x 20 + 1 x 2-1 + 1 x 2-2

= 1 x 4 + 0 x 1 + 1 x 1 + 1 x 0.5 + 1 x 0.25

= 4 + 0 + 1 + 0.5 + 0.25

= 5.75(10)

1101(2) = 1 x 23 + 1 x 22 + 0 x 21 + 1 x 20

= 1x8+1x4+0x2+1x1

= 8+4+0+1

= 13(10)

0.111(2) = 0 x 20 + 1 x 2-1 + 1 x 2-2 + 1 x 2-3

= 0 x 1 + 1 x 0.5 + 1 x 0.25 + 1 x 0.125

= 0 + 0.5 + 0.25 + 0.125

= 0.875(10)


Convert the following binary numbers to decimal

a.) 1010(2) b.) 11.101(2) c.) 1011110001(2) d.) 1.11101(2)

Decimal to Binary Conversion

A given number, which has decimal form, are represented in binary in two ways.

• Sum of Weight Method
• Repeated Division Method
• Repeated Multiplication Method

Sum of Weight Method

Table 1.2 represents the weights associated with individual bit position. The weight associated
with a bit increases by a power of two for the each bit placed to the left. For the bit positions to
the right of binary point the weight decrease by a power to two from left to right.

Find out all Binary weight values, less than the given decimal number. Determine a set of binary
weight values when added should sum up equal to the given decimal number.

Example: To find out binary equivalent of 43, Note that Binary values which are less than 43 are
20 = 1, 21 = 2, 22 = 4, 23 = 8, 24 = 16, 25 = 32.

43 (10) = 32 + 8 + 2 + 1 = 25 + 23 + 21 + 20

i.e. The set of weights 25, 23, 21, 20 when summed up equals to the given decimal number 43.
By placing a 1 in the appropriate weight positions 25, 23, 21 and 20 and a 0 in the other positions,
a equivalent binary representation can be obtained.

25 24 23 22 21 20

1 0 1 0 1 1 (2) = 43 (10)

Example: To find out binary equivalent of 0.625 (10) = 0.5 + 0.125 = 2-1 + 2-3
= 0.101 (2)

Example: to find the binary equivalent of 33.3125 (10)

33 (10) = 32 + 1 = 25 + 20 = 1 0 0 0 0 1 (2)

0.3125 (10) = 0.25 + 0.0625 = 2-2 + 2-4 = 0 . 0 1 0 1 (2)

33.3125 (10) = 1 0 0 0 0 1 . 0 1 0 1 (2)


Represent the following decimal numbers into binary using sum of weight method.

a) 1101.11(2) b) 111.001(2) c) 10001.0101(2)

Repeated Division Method

Repeated division method is the more systematic method usually used in whole number
decimal to binary conversion. Since binary number system uses base – 2, given decimal number
is repeatedly divided by 2 until there is a 0 quotient. While division is carried out the
remainders generated at each division, i.e. 0 or 1, are written down separately. The first
remainder is noted down as LSB in the binary number and the last remainder as MSB.

Example: Write the binary equivalent of 29 (10) and 45 (10).

Repeated Multiplication

Repeated multiplication method is the more systematic method usually used in fraction part of
decimal number in decimal to binary conversion. Since binary number system uses base – 2,
given fraction is repeatedly multiplied by 2 until there is a 0 fraction part left. While
multiplication is carried out the integer parts generated at each multiplication, i.e. 0 or 1, are
written down separately. The first integer part thus generated is noted down as first fractional
bit in the binary number and the subsequent integers generated are placed left to right.

Example: Write the binary equivalent of 0.625 (10) and 0.3125 (10).

Example: Write the binary Equivalent of 17.135

Therefore 17.135 (10) = 1 0 0 0 1 . 0 0 1 0 …… (2)


Represent the following decimal numbers into binary using repetitive divisions and
multiplication method.

a) 1101.11(2) b) 111.001(2) c) 10001.0101(2

MC0062-1.4 The Octal Numbering System
The Octal Numbering System

The Octal Number System uses base 8 and uses symbols 0, 1, 2, 3, 4, 5, 6 and 7, these are known
as Octal digits. The position of each bit in a given sequence has a numerical weight. It makes use
of a Octal point.
Thus binary number system can be represented as a weighted sum of digits. Table 1.2 represents
the weight associated in binary numbering system.

in decimal
… 4096 512 64 8 1 • 0.125 0.015625 … …
Equivalent weight
Octal
… 84 83 82 81 80 8-1 8-2 … …
point

Table 1.4: Weights associated with the position in Octal numbering system.

Example: 710.16 (8) = 7 x 82 + 1 x 81 + 0 x 80 + 1 x 8-1 + 6 x 8-2


Give the weighed sum representation for the following octal numbers.

a) 734.52(8) b) 1234.567(8) c) 345.1271(8)

Counting in Octal

Counting with octal number system is analogous to the counting methodology used in decimal
and in binary numbering system. The symbols available are from 0 to 7. Count begins with 0
then 1 and till 7. Since all the symbols are exhausted start with combining two-digit
combination by placing a 1 to the left of 0 to get 10, 11, 12 … 17. Similarly, continuing placing a
2, 3 …and 7. Again place 1 to the left again 100, 101, 102…107, 110….170, 200 … 270 etc.

Octal to Decimal Conversion

Weighted Sum Representation: An Octal Number is represented with its associated weights as
shown in Table 1.4. The right most value, has a value 80 = 1, is known to be Least Significant
Digit. The weight associated with each octal symbol varies from right to left by a power of eight.
In the fractional octal number representation, the bits are placed to the right side of the octal
point. The value of a given octal number thus can be determined as the weighted sum.

Example:

234.32 (8) = 2 x 82 + 3 x 81 + 4 x 80 + 3 x 8-1 + 2 x 8-2

= 2 x 64 + 3 x 8 + 4 x 1 + 3 x 0.125 + 2 x 0.015625

= 128 + 24 + 4 + 0.125 + 0.03125

= 156.15625 (10)

65 (8) = 6 x 81 + 5 x 80

=6x8+5x1

= 48 + 5

= 53 (10)

0.427 (8) = 4x 8-1 + 2 x 8-2 + 7 x 8-3

= 4 x 0.125 + 2 x 0.015625 + 7 x 0.001953125

= 0.544921875 (10)

Decimal to Octal Conversion




Table 1.4 represents the weights associated with individual symbol position in octal numbering
system. Find out all octal weight values, less than the given decimal number. Determine a set of
binary weight values when added should sum up equal to the given decimal number.

Example: To find out binary equivalent of 99, Note that octal values which are less than 99 are
80 = 1, 81 = 8, 82 = 64.

99 (10) = 1 x 64 + 4 x 8 + 3 x 1 �

= 1 x 82 + 4 x 81 + 3 x 80

= 1 4 3 (8)


Represent the following decimal numbers into octal using sum of weight method.

a) 789.45 b) 654 c) 0.678 d) 987.654


Repeated division method is the more systematic method usually used in whole number decimal
to octal conversion. Since Octal number system has base – 8, given decimal number is repeatedly
divided by 8 until there is a 0 quotient. While division is carried out the remainders generated at
each division, are written down separately. The first remainder is noted down as Lease
Significant Digit (LSD) in the binary number and the last remainder as Most Significant Digit
(MSD).

Example: Write the binary equivalent of 792 (10) and 1545 (10).


Repeated multiplication method is the more systematic method usually used for the fractional
part of decimal to octal conversion. Given fraction of decimal number is repeatedly multiplied by
8 until there is a 0 fraction part left. While multiplication is carried out the integer parts
generated at each multiplication, are written down separately. The first integer part thus
generated is noted down as first fractional bit in the octal number and the subsequent integers
generated are placed left to right.
Example: Write the binary equivalent of 0.3125 (10).

Example: Write the binary Equivalent of 541.625 (10)

Therefore 541.625 (10) = 1035.5 (8)


Represent the following decimal numbers into octal using repetitive multiplication and division
method.

a) 789.45 b) 654 c) 0.678 d) 987.654

Octal to Binary Conversion

There is a direct relation between the bases of Octal and Binary number systems. i.e. 8 = 23.
Which indicates that one symbol of octal can be used to replace one 3-bit representation in
binary system. There are totally 8 combinations with 3-bit binary representation from 000 to 111,
which can be mapped octal symbols 0 to 7.

Octal Digit Binary Bit
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111

Table 1.5: Octal number and equivalent 3-bit Binary representation

To convert a given octal number to binary, simply replace the octal digit by its equivalent 3-bit
binary representation as shown in Table 1.5.

Example: 4762.513 (8) = 4762.513

= 100
111
110
010 . 101
001
011
(2)

Therefore 4762.513 (8) = 100111110010.101001011 (2)


Represent the following octal numbers into binary.

a.) 735.45(8) b.) 654(8) c.) 0.674(8) d.) 123.654(8)

1.4.5 Binary to Octal Conversion

To represent a given binary number in octal representation is also a straight forward conversion
process. Given binary number is clubbed into a group of three bits towards left from the octal
point and grouped towards right from the octal point. Additional 0’s, if required, can be added
to the left of leftmost bit of integer part and to the right of rightmost bit in the fractional part,
while grouping.

Example: 1011001.1011 (2) = 001
011
001 . 101
100 (2)

= 1 3 1 . 5 4 (8)

Therefore 1011001.1011(2) = 131.54(8)

Note: Additional 0’s were used while grouping 3-bits.

Example: 101111.001 (2) = 101
111 . 001
(2)

= 5 7 . 1 (8)

Therefore 101111.001 (2) = 57.1 (8)


Represent the following binary numbers into octal.

a) 1101.11(2) b) 10101.0011(2) c) 0.111(2) d) 11100(2)

MC0062-1.5 The Hexadecimal Numbering
System
The Hexadecimal Numbering System

The Hexadecimal Number System uses base 16 and uses alpha-numeric symbols 0, 1, 2, 3, 4, 5,
6, 7, 8, 9 and A, B, C, D, E, F. It uses ten decimal digits and six numeric symbols. Therefore base-
16 is referred for hexadecimal numbering system. Unless like decimal, binary and octal systems
which were used in weighted number representation, hexadecimal numbering system is used
to replace 4-bit combination of binary. This justifies the usage of hexadecimal numbering
system in microprocessors, soft-computations, assemblers, and in digital electronic
applications.

Counting in hexadecimal numbering system is similar way to the counting methodology used in
decimal, binary and in octal numbering systems as discussed earlier in this chapter.

Hexadecimal to Binary Conversion

There is a direct relation between the bases used in Hexadecimal and Binary number systems. i.e.
16 = 24. Which indicates that one symbol of hex numbering can be used to replace one 4-bit
representation in binary system. There are totally 16 combinations with 4-bit binary
representation from 0000 to 1111, which can be mapped hex symbols 0 to 9 and A to F.

Octal Digit Binary Bit
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101

6 0110
7 0111
8 1000
9 1001
A 1010
B 1011
C 1100
D 1101
E 1110
F 1111

Table 1.6: Hexadecimal number and equivalent 4-bit Binary representation

To convert a given hexadecimal number to binary, simply replace the hex-digit by its equivalent
4-bit binary representation as shown in Table 1.6.

Example: 1A62.B53 (16) = 1 A 6 2 . B 5 3(16)

= 0001
1010
0110
0010 . 1011
0101
0011(2)

Therefore 1A62.B53 (16) = 0001101001100010.101101010011 (2)

Example: 354.A1 (16) =3 5 4. A 1 (16)

0011 0101 0100 . 1010 0001 (2)

Therefore 354.A1 (16) = 001101010100.10100001 (2)


Represent the following hexadecimal numbers into binary.

a) 8AC8.A5(16) b) 947.A88(16) c) A0.67B(16) d) 69AF.EDC(16)

Binary to Hexadecimal Conversion

To represent a given binary number in hexadecimal representation is a straight forward
conversion process. Binary number given is clubbed into a group of 4-bits starting form the
hexadecimal point towards left and towards right. Additional 0’s, if required, can be added to
the left of leftmost bit of integer part and to the right of rightmost bit in the fractional part,
while grouping. Equivalent hexadecimal symbol is placed for a 4-bit binary group to have the
conversion.

Example: 1011001.1011 (2) = 0101
1001 . 1011
(2)

= 5 9 . B (16)

Therefore 1011001.1011 (2) = 59.B (16)

Note: Additional 0’s were used while grouping 4-bits.

Example: 101111.001 (2) = 0010
1111 . 0010 (2)

= 2 F . 2 (16)

Therefore 101111.001 (2) = 2F.2 (16)

Note: Hexadecimal to Octal Conversion can be done by first converting a given Hexadecimal
number to binary and then converting the resultant binary to octal system. Similarly given octal
number can be converted to hexadecimal by converting first to the binary system and then to
hexadecimal system.


Represent the following binary numbers into Hexadecimal.

a.) 1101.11(2) b.) 10101.0011(2) c.) 0.111(2) d.) 11100(2)

Hexadecimal to Decimal Conversion

Hexadecimal numbers can be represented with their associated positional weights as indicated
in Table 1.7. Positional weights increases by a power of 16 towards left of the hexadecimal
point and decrease by a power of 16 towards right.

Equivalent
weight in …. 4096 256 16 1 • 0.0625 0.00390625 ….
decimal
…. 163 162 161 160 Hexadecimal 16-1 16-2 ….

point

Table 1.7: Weights associated with the position in hexadecimal numbering system.

Hexadecimal to Octal Conversion

Weighted Sum Representation: Hexadecimal Number is represented with its associated weights
as shown in Table 1.4. The right most value, has a value 80 = 1, is known to be Least Significant
Digit. The weight associated with each octal symbol varies from right to left by a power of eight.
In the fractional octal number representation, the bits are placed to the right side of the octal
point. The value of a given octal number thus can be determined as the weighted sum.

Example: 234.32 (8) = 2 x 82 + 3 x 81 + 4 x 80 + 3 x 8-1 + 2 x 8-2

= 2 x 64 + 3 x 8 + 4 x 1 + 3 x 0.125 + 2 x 0.015625

= 128 + 24 + 4 + 0.125 + 0.03125

= 156.15625 (10)

65 (8) = 6 x 81 + 5 x 80

=6x8+5x1

= 48 + 5

= 53 (10)

0.427 (8) = 4x 8-1 + 2 x 8-2 + 7 x 8-3

= 4 x 0.125 + 2 x 0.015625 + 7 x 0.001953125

= 0.544921875 (10)


Represent the following hexadecimal numbers into octal numbers.


Decimal to Octal Conversion





Table 1.4 represents the weights associated with individual symbol position in octal numbering
system. Find out all octal weight values, less than the given decimal number. Determine a set of
binary weight values when added should sum up equal to the given decimal number.

Example: To find out binary equivalent of 99, Note that octal values which are less than 99 are
80 = 1, 81 = 8, 82 = 64.

99 (10) = 1 x 64 + 4 x 8 + 3 x 1 �

= 1 x 82 + 4 x 81 + 3 x 80

= 1 4 3 (8)


Repeated division method is the more systematic method usually used in whole number decimal
to octal conversion. Since Octal number system has base – 8, given decimal number is repeatedly
divided by 8 until there is a 0 quotient. While division is carried out the remainders generated at
each division, are written down separately. The first remainder is noted down as Lease
Significant Digit (LSD) in the binary number and the last remainder as Most Significant Digit
(MSD).


Repeated multiplication method is the more systematic method usually used for the fractional
part of decimal to octal conversion. Given fraction of decimal number is repeatedly multiplied
by 8 until there is a 0 fraction part left. While multiplication is carried out the integer parts
generated at each multiplication, are written down separately. The first integer part thus
generated is noted down as first fractional bit in the octal number and the subsequent integers
generated are placed left to right.

Integer Part
0.625 X 8
0.625 (10) = 0.5 (8) 5 0.0

Therefore 541.625 (10) = 1035.5 (8)


Represent the following hexadecimal numbers into octal.


MC0062-1.6 Binary Arithmetic
Binary Arithmetic

Let us have a study on how basic arithmetic can be performed on binary numbers.

Binary Addition

There are four basic rules with Binary Addition

0(2) + 0(2) = 0(2)

0(2) + 1(2) = 0(2) Addition of two single bits result into single bit

1(2) + 0(2) = 1(2)

1(2) + 1(2) = 10(2) Addition of two 1’s resulted into Two bits

Example: perform the binary addition on the followings

11 1111 1 1 1

011(2) 3(10) 1101(2) 13(10) 11100(2) 28(10)

+ 011(2) + 3(10) + 0111(2) + 07(10) + 10011(2) + 19(10)
110(2) 6(10) 10100(2) 20(10) 101111(2) 47(10)

Binary Subtraction

There are four basic rules associated while carrying Binary subtraction

0(2) – 0(2) = 0(2)

1(2) – 1(2) = 0(2) �

1(2) – 0(2) = 1(2)

0(2) – 1(2) = invalid there fore obtain a borrow 1 from MSB and perform binary
subtraction

10(2) – 1(2) = 1(2) �

Note: In last rule it is not possible to subtract 1 from 0 therefore a 1 is borrowed from immediate
next MSB to have a value of 10 and then the subtraction of 1 from 10 is carried out

Example: perform the binary subtraction on the followings

11 11

011(2) 3(10) 1101(2) 13(10) 11100(2) 28(10)

– 011(2) – 3(10) – 0111(2) – 07(10) – 10011(2) – 19(10)

000(2) 0(10) 0110(2) 06(10) 01001(2) 09(10)

Binary Multiplication

There are four basic rules associated while carrying Binary multiplication

0(2) x 0(2) = 0(2)

0(2) x 1(2) = 0(2) �

1(2) x 0(2) = 0(2)

1(2) x 1(2) = 1(2) �

Note: While carrying binary multiplication with binary numbers the rule of shift and add is made
used similar to the decimal multiplication. i.e. multiplication is first carried out with the LSB of
the multiplicand on the multiplier bit by bit basis. While multiplying with the MSB bits, first the
partial sum is obtained. Then result is shifted to the left by one bit and added to the earlier result
obtained.

Example: perform the binary multiplication on the followings

011(2) 3(10) 1101(2) 13(10)

x 1(2) x 1(10) x 11(2) x 03(10)
1101(2)
011(2) 3(10)
1101 (2)
100111(2) 39(10)

Binary Division

The binary division is similar to the decimal division procedure

Example: perform the binary division

101(2) 10.1(2)
1111 1111.0
11 110
11 110
001 0011

000 000

11 110

11 110
00 000

Complementary numbering systems: 1’s and 2’s Complements

1’s complement of a given binary number can be obtained by replacing all 0s by 1s and 1s by 0s.
Let us describe the 1’s complement with the following examples

Examples: 1’s complement of the binary numbers

Binary Number 1’s Complement
1101110 0010001
111010 000101
110 001
11011011 00100100

Binary subtraction using 1’s complementary Method:

Binary number subtraction can be carried out using the method discussed in binary subtraction
method. The complementary method also can be used. While performing the subtraction the
1’s complement of the subtrahend is obtained first and then added to the minuend. Therefore
1’s complement method is useful in the sense subtraction can be carried with adder circuits of
ALU (Arithmetic logic unit) of a processor.

Two different approaches were discussed here depending on, whether the subtrahend is smaller
or larger compared with minuend.

Case i) Subtrahend is smaller compared to minuend

Step 1: Determine the 1’s complement of the subtrahend

Step 2: 1’s complement is added to the minuend, which results in a carry generation known as
end-around carry.

Step 3: From the answer remove the end-around carry thus generated and add to the answer.

Example: Perform the subtraction using 1’s complement method

Binary Subtraction Binary Subtraction

(usual method) ( 1’s complement method)
11101(2) 11101(2)

– 10001(2) + 01110(2) 1’s complement of 10001
1 01011(2) end-around carry generated
01100(2)
+ 1(2) add end-around carry
01100(2) Answer

Case ii) Subtrahend is larger compared to minuend


Step 2: Add the 1’s complement to the minuend and no carry is generated.

Step 3: Answer is negative singed and is in 1’s complement form. Therefore obtain
the 1’s complement of the answer and indicate with a negative sign.



10001(2) 10001(2)

– 11101(2) + 00010(2) 1’s complement of 10001
– 01100(2) 10011(2) No carry generated. Answer is negative and is in 1’s complement form
– 01100(2) Answer

Binary subtraction using 2’s complementary Method:

2’s complement of a given binary number can be obtained by first obtaining 1’s complement
and then add 1 to it. Let us obtain the 2’s complement of the following.

Examples: 2’s complement of the binary numbers

Binary Number 2’s Complement
0010001

1101110 +1

0010010

000101
111010
+1

000110

001

110 +1

010

00100100

11011011 +1

00100101

Binary number subtraction can be carried out using 2’s complement method also. While
performing the subtraction the 2’s complement of the subtrahend is obtained first and then added
to the minuend.

Two different approaches were discussed here depending on, whether the subtrahend is smaller
or larger compared with minuend.

Case i) Subtrahend is smaller compared to minuend


Step 2: 2’s complement is added to the minuend generating an end-around carry.

Step 3: From the answer remove the end-around carry and drop it.



11101(2) 11101(2)

– 10001(2) + 01111(2) 2’s complement of 10001
1 01100(2) end-around carry generated
01100(2)
drop the carry
01100(2) Answer

Case ii) Subtrahend is larger compared to minuend


Step 2: Add the 2’s complement to the minuend and no carry is generated.

Step 3: Answer is negative singed and is in 2’s complement form. Therefore obtain the 2’s
complement of the answer and indicate with a negative sign.



10001(2) 10001(2)

– 11101(2) + 00011(2) 1’s complement of 10001
– 01100(2) 10000(2) No carry generated. Answer is negative and is in 1’s complement form
– 01100(2) Answer


Perform the following subtractions using 1’s complement and 2’s complement methods

a) 1101(2) – 1010(2) b) 10001(2) - 11100(2) c) 10101(2) - 10111(2

MC0062-1.7 Binary Coded Decimal (BCD)
Numbering system
Binary Coded Decimal (BCD) Numbering system

The BCD code is also known as 8421 code. It is a 4 bit weighted code representing decimal
digits 0 to 9 with four bits of binary weights (23, 22, 21, 20). Please note that with four bits the
possible numbers of binary combinations are 24 = 16, out of which only first 10 combinations
were used. The codes 1010, 1011, 1100, 1101, 1110 and 1111 are not used.

BCD or 8421 code Decimal Number
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7

1000 8
1001 9

A given decimal number can be represented with equivalent BCD number by replacing the
individual decimal digit with its equivalent BCD code.

Example:

348.16 (10) = 0011 0100 1000 . 0001 0110 (BCD)

18 (10) = 0001 1000 (BCD)

9357 (10) = 1001 0011 0101 0111 (BCD)

BCD Addition

BCD codes are the 4 bit binary weighted code representation of decimal numbers. The addition
operation carried on decimal can be represented with BCD addition. Since BCD does not uses all
16 combinations possible from 4-bit representation, while addition performed on BCD
numbers, may result into invalid code words. The rule to be followed while BCD were added
directly are given as

1. Add the given two BCD numbers using the addition rules for binary addition
2. If the resultant 4-bit binary is less than 9 then it is a valid BCD code
3. If a 4-bit sum is greater than 9 then it is an invalid BCD code
4. If there is carry generated while adding the two 4-bit numbers the result is an invalid
sum.
5. For both the cases discussed in 3 and 4 add a BCD equivalent of 6 i.e. 0110(2) so that sum
skips all six invalid states and results into a valid BCD number.

Example: few examples for the generation of valid BCD codes during BCD addition

0011 3 1000 0110 0111 867 0100 0101 0010 452

+ 0101 +5 + 0001 0011 0010 + 132 + 0100 0001 0110 + 416
1000 8 1001 1001 1001 999 1000 0110 1000 868

Example: few examples for the generation of invalid BCD codes during BCD addition

1000 8

+ 0111 +7

1111 Invalid BCD combination >9

+ 0110 Add 6
1 0101 Valid BCD number 15
1000 8

+ 1001 +9
1 0001 Invalid BCD combination , carry generated

+ 0110 Add 6
1 0111 Valid BCD number 17

Note: While carrying BCD addition as discussed in the examples above, if the answer has more
than one group of 4-bit combination, which is invalid (either invalid combination or due to carry
generation) 6 to be added to each group to get a valid BCD code.


Add the following BCD Numbers

a) 0100000 + 1001011 b) 01100100 + 00110011 c) 0111 + 0010 d) 1010 + 0111

Summary

• A binary number system has a base of two and consists of two digits (called bits) 1 and 0.
• A binary number is a weighted number with the weight of each whole number digit from
least significant (20) to most significant being an increasing positive power of two. The
weight of each fractional digit beginning at 2-1 is an increasing negative power of two.
• The 1’s complement of a binary number is derived by changing 1s to 0s and 0s to 1s
• The 2’s complement of a binary number is derived by adding 1 to the 1’s complement
• Binary subtraction can be accomplished by addition using the 1’s or 2’s complement
methods
• A decimal whole number can be converted to binary by using the sum-of-weights or by
repeated division by 2 method
• A decimal fraction can be converted to binary by using the sum-of-weights or by repeated
division by 2 method
• The octal number system has a base of eight and consists of eight digits (0 to 7)
• A decimal whole number can be converted to octal by using the repeated division-by-8
method
• Octal to binary conversion is accomplished by simply replacing each octal digit with its
three-bit binary equivalent. The process is reversed for binary-to-octal conversion
• The hexadecimal number system has a base of sixteen and consists of 16 digits and
characters 0 through 9 and A to F
• One hexadecimal digit represents a four-bit binary number and its primary usefulness is
simplifying bit patterns by making then easier to read

• BCD represents each decimal digit by a four-bit binary number. Arithmetic operations
can be performed in BCD.
• The Main feature of the Gray-code is the single-bit change going from one number in
sequence to the next

Terminal Questions

1. Convert the following binary numbers to decimal
1. 11.001(2)
2. 1100(2)
3. 1111(2)
4. 1011.101(2)
5. 0.1101(2)
2. Convert the following decimal numbers to binary using sum-of weight and repeated
division methods
1. 40.345(10)
2. 143.7(10)
3. 467(10)

1. Convert the following octal number to decimal
1. 73.24(8)
2. 276(8)
3. 0.625(8)
4. 57.231(8)
2. Convert the octal numbers in question 3 into binary format
3. Convert the decimal numbers in question 2 into octal format
4. Convert the binary numbers in question 1 into octal format
5. Give the equivalent BCD representation for the decimal numbers given in question 2
6. Perform the BCD addition
1. 1001(2) + 0110(2)
2. 01010001(2) + 01011000(2)
3. 0111(2) + 0101(2)
4. 0101011100001(2) + 011100001000(2)
7. Perform the 1’s and 2’s complement to realize the binary subtraction.
1. 10011(2) – 10101(2)
2. 10010(2) – 11001(2)

1111000(2) – 1111111(2)

Unit 3 Combinational Logic

This unit mainly focuses on realization of combinational logic using basic gates, reduced
representation of combinational logic using basic gates, specific truth table realization, universal

properties of NOR and NAND gates, canonical logic forms, sum of products (SOP) and product
of sum(POS) form representation.

MC0062(A)3.1 Introduction
Introduction

In unit 2, logic gates were studied on an individual basis and in simple combinations. When logic
gates where connected together to produce a specified output for certain specified combinations
of input variables, with no storage involved, the resulting network is called combinational logic.

In combinational logic, the output level is at all times dependent on the combination of input
levels. The chapter mainly focuses on realization of combinational logic using basic gates,
reduced representation of combinational logic using basic gates, specific truth table realization,
universal properties of NOR and NAND gates, canonical logic forms, sum of products (SOP) and
product of sum(POS) form representation.

Objectives:

By the end of this chapter, reader should know

• How to simplify the combinational logic expressions using Boolean rules and laws and
with the application of Demorgan’s theorem.
• How to realize the simplified expressions using basic logic gates.
• How to represent the logic expressions with the canonical forms such as sum of products
and product of sum forms.
• What are Universal gates and its application in the realization of simplified logic
functions?
• What are Timing diagrams and the concept of synchronization
• How to realize the combinational circuits from the specified truth table.

MC0062(A)3.2 Realization of switching
Realization of switching functions using logic gates

A given logic function can be realized with the combination of basic gates. Boolean laws and
rules are used to simplify and simplified realization of the same function with the basic gates are
shown here.

Example: Realize the given function using basic gates. Use Boolean rules
and laws to simplify the logic function and realize the minimized function using basic gates.

Solution:

Direct realization: �

Simplifying using Boolean Algebra:

Example: Realize the logic expression using basic gates.

Solution: Direct realization of the expression

Example: A logic function if defined by . Give the basic gate realization.
Simplify the logic function and represent with basic gates.

Solution: Direct realization of the function

Simplifying the expression using Boolean Laws

Self Assessment Question: Use Boolean algebra to simplify the logic function and realize the

given function and minimized function using discrete gates.

Solution: i) Direct realization of the function

ii) Simplified realization of the function

MC0062(A)3.3 Canonical Logic Forms
Canonical Logic Forms

The form of the Boolean expression does determine how many logic gates are used and what
types of gates are needed for the realization and their interconnection. The more complex an
expression, the more complex the circuit realization will be. Therefore an advantage of simplify
an expression is to have the simple gate network.

There are two representations in which a given Boolean expressions can be represented.

• Sum of Product form (SOP)
• Product of Sum form (POS)

Sum of Products Form

In Boolean algebra the product of two variables can be represented with AND function and sum
of any two variable can be represented with OR function. Therefore AND and OR functions are
defined with two or more input gate circuitries.

Sum of products (SOP) expression is two or more AND functions ORed together. The ANDed
terms in a SOP form are known as minterms.

Example:

Here in the first example the function is having 4 minterms and the second example has 3
minterms. One reason the sum of products is a useful form of Boolean expression, which is the
straightforward manner in which it can be implemented with logic gates. It is to be noted that the
corresponding implementation is always a 2-level gate network. i.e. the maximum number of
gates through which a signal must pass 2in going from an input to the output is two (excluding
inversions if any).

A most popular method of representation of SOP form is with the minterms. Since the minterms
are ORed, a summation notation with the prefix m is used to indicate SOP expression. If the
number of variables are used is n, then the minterms are notated with a numeric representation
starting from 0 to 2n.

Consider the above example, where the given logic expression can be represented in terms of

associated minterms. consists of 3 variables. Therefore minterms can be
represented with the associated 3-bit representation. Representation of minterms with 3-bit

binary and equivalent decimal number can be noted. , , ,

.

There fore the logic function can b given as

Self Assessment Question: implement the SOP expression given by or

Product of Sum Form

Product of Sum (POS) expression is the ANDed representation of two or more OR functions.
The ORed terms in a POS form are known as maxterms.

Example:

Here in the first example the function is having 4 maxterms and the second example has 3
maxterms. This form is also useful in the straightforward implementation of Boolean expression
is with logic gates. It is to be noted that the corresponding implementation is always a 2-level
gate network. i.e. the maximum number of gates through which a signal must pass 2in going
from an input to the output is two (excluding inversions if any).

Similar to SOP representation, a most popular method of representation of POS form is with the
maxterms. Since the maxterms are ANDed, a product notation with the prefix M is used. If the
number of variables are used is n, then the maxterms are notated with a numeric representation
starting from 0 to 2n.

Consider the above example, where the given logic expression can be represented in terms of

associated maxterms. it consists of 3 variables. Therefore maxterms
can be represented with the associated 3 bit representation. Representation of maxterms with 3-

bit binary and equivalent decimal number can be noted. , ,

.

There fore the logic function can b given as

Self Assessment Question: implement the SOP expression given by or

.

MC0062(A)3.5 Timing Diagrams and
Synchronous Logic
Timing Diagrams and Synchronous Logic

In digital systems, a timing diagram shows the waveform appearing at several different points.
Timing diagram is plotted as a plot dependent of time axis (horizontal axis). All observed
waveforms were plotted with time axes are aligned. Therefore, it is possible at a particular
instant to determine the state of each waveform. The timing diagram mainly assists the study of
propagation delay in the gate circuitry.

A clock waveform is a rectangular pulse having HIGH and LOW representations. The basic
gates were studied in unit II with digital inputs. Consider these gates were studied with one of the
input is being digital input and the other being a clock waveform. The gates are said to be pulsed
or clocked. The study of gate circuitry with respect to the timing pulses is known as synchronous
logic circuits.

Gate Circuitry with timing pulses.

• NOT Gate

• AND Gate

Output of an AND gate is HIGH only when all inputs are HIGH at the same time.

• OR Gate

The output of an OR gate is HIGH any time at least one of its inputs is HIGH. The output is LOW
only when all inputs are LOW at the same time.

• NAND Gate

The output of a NAND gate is LOW only when all inputs are HIGH at the same time.

• NOR Gate

The output of a NOR gate is LOW any time at least one of its inputs is HIGH. The output is HIGH
only when all inputs are LOW at the same time.

Example: Determine the output waveform for the combinational circuit shown with the
indicated input waveforms.

MC0062(A)3.6 Realization of Combinational
Realization of Combinational circuits from the truth table

The Logic functions were represented with the truth tables as discussed in unit II. To realize the
given logic functions, write down the combination of all logic functions in SOP form. A truth
table gives the logic entries for the all possible combination of inputs related to the output. The
output logic is TRUE for a specific input combination is represented with an entry ‘1′ and the
logic FALSE with an entry ‘0′.

Example: Design a logic circuit to implement the operations specified in the following truth
table.

Inputs Output
a b c f
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

Solution: From the truth table the function can be given in terms of minterms

Summary

• There are two basic forms of Boolean expressions: the sum-of-products and the product-
of-sum
• Boolean expressions can be simplified using the algebraic method and are realizable
using discrete gates
• Any logic function can be represented with equivalently using a truth table.
• Truth table simplification can be done using Sum-of-product realization or with product
of sum realization
• Demorgan’s theorems are used to represent the function only with universal gates

Terminal Questions:

1. Realize the given function using basic gates. Use Boolean rules
and laws to simplify the logic function and realize the minimized function using basic
gates.

2. Realize the logic expression using basic gates.
3. Use Boolean algebra to simplify the logic function and realize the given function and

minimized function using discrete gates.
4. Implement the following SOP expression

1.

2.

3.

4.
5. Use Boolean algebra to simplify the logic function and realize the given function and
minimized function using discrete gates.

1.
2.

6. Implement the following SOP expressions with discrete gates

1.

2.

3.
7. Give the NAND realization for the logic expressions given in question number 3 and 4.
8. Design a logic circuit to implement the operations specified in the following truth table.

Inputs Output
a b c f
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Introduction

A given logic function can be realized with minimal gate logic. Boolean algebra and laws were
of great help to reduce the given expression into a minimal expression. But the simplification
process of the expression is being not a systematic method, it is not sure that the reduced
expression is the minimal expression in real sense or not.

In this chapter different combination logic minimization methods were discussed. The most
preferred method is being the use of Karnaugh Map or also known as K – map. Here a basic
structure of K – map is dealt with two, three and four variable. Other method used is Qune –
McClusky method.

Objectives

By the end of this chapter, reader should be able to explain

• the concept of Karnaugh map and simplification of logic expression using Karnaugh
Map.
• How to group the adjacent cells in K-Map with two, three and four variable maps and to
solve the logic functions
• How logic expressions are simplified using Quine McClusky method
• What are the multiple output functions and how to simplify and to realize the same.

MC0062(A)4.2 Karnaugh Map or K – Map
Karnaugh Map or K – Map

The Karnaugh map provides a systematic procedure in the simplification of logic expression. It
produces the simplest SOP expression if properly used. An user is required to know the map
structure and associated mapping rules.

Karnaugh Map consists of an arrangement of cells. Each adjacent cells represents a particular
combination of variables in the product form. For an ‘n’ number of variables the total number of
combinations possible are 2n, hence Karnaugh Map consists of 2n cells.

For example, with two input variables, there are four combinations. Therefore a four cell map
must be used.

Format of a two-variable Karnaugh – Map is shown in Figure 4.1. For the purpose of illustration
only the variable combinations are labeled inside the cells. In practice, the mapping of the
variables to a cell is such that the variable to the left of a row of cells applies to each cell in that
row. And the variable above a column of cells applies to each cell in that column.

Similarly three variable and four variable Karnaugh Maps were shown in the Figure 4.2. A three
variable map consists of 23 = 8 cells and a four variable map consists of 24 = 16 cells. The value
of the minterms are indicated within the cell. Note that in a Karnaugh Map, the cells are arranged
such a way that there is only a one bit or one variable change between any two adjacent cells.
Karnaugh maps can also be used for five, six or more variables.

MC0062(A)4.3 Plotting a Boolean expression
Plotting a Boolean expression

Given a logic function get its sum – of – product (SOP) realization. Place 1 in each cell
corresponding to the term obtained in the logic function. And 0 in all other empty cells.

Example: Plot a two variable logic function

Figure 4.3: three variable and four variables Karnaugh Map.

Self Assessment Question: Plot a three variable logic function in a K – map

Self Assessment Question: Plot a Four variable logic function in a K – map

MC0062(A)4.4 Logic expression
simplification
Logic expression simplification with grouping cells

Let us discuss the simplification procedure for the Boolean expressions. The procedure being
same irrespective of the dimensionality of K – map. A four variable K – map is used for the
discussion on grouping cells for expression minimizing process.

Grouping of adjacent cells are done by drawing a loop around them with the following
guidelines or rules.

• Rule 1: Adjacent cells are cells that differ by only a single variable.
• Rule 2: The 1s in the adjacent cells must be combined in groups of 1, 2, 4, 8, 16 so on
• Rule 3: Each group of 1s should be maximized to include the largest number of adjacent
cells as possible in accordance with rule 2.
• Rule 4: Every 1 on the map must be included in at least one group. There can be
overlapping groups, if they include non common 1s.

Simplifying the expression:

• Each group of 1s creates a product term composed of all variables that appear in only one
form within the group
• Variables that appear both uncomplemented and complemented are eliminated.
• Final simplified expression is formed by summing the product terms of all the groups.

Example: Use Karnaugh Map to simplify the expression
Solution:

Example: reduce the following expression using Karnaugh Map

Solution:

Example: Using Karnaugh Map, Implement the simplified logic expression specified by the
truth table.

Inputs Output
a b c f
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

Solution:

Example: A logic circuit has three inputs and one output terminals. Output is high when two or
more inputs are at high. Write the truth table and simplify using Karnaugh Map.

Inputs Output
a b c f

0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

Solution:

Simplified expression

Self Assessment Question:

1. Reduce the following expression using K – Map and implement using universal gate

1.

2.
2. Reduce using the K-map

1.
2.
3.

MC0062(A)4.5 Quine McClusky Method

Quine McClusky Method

Quine McClusky method is known as tabular method, a more systematic method of minimizing
expressions of larger number of variables. Therefore its an edge over the disadvantage of
Karnaugh Map method were it supports a maximum of six variable. Qunie McClusky method is
very suitable for hand computation as well as for the soft program implementation.

Prime implicants

Solution of logical expression with Quine McClusky method involves in the computation of
prime implicants, from which minimal sum should be selected.

The procedure for the minimization of a logic expression is done as follows.

• Arrange all minterms in groups of the same number of 1s in their binary representations.
Start with the least number of 1s present in the number and continuing with increasing
number of 1s.
• Now compare each term of the lowest index group with every term in the succeeding
group. Whenever the two terms differ by one bit position, the two terms were combined
with (-) used in place of differing position.
• Place a tick mark next to the every term used while combining.
• Perform the combining operation till last group to complete the first iteration.
• Compare the terms generated with same procedure with dashed line mapping the dashed
line in two terms under comparison.
• Continue the process till no further combinations are possible.
• The terms which are not ticked constitute the prime implicants.

Prime implicant chart

The Prime implicant chart is a representation giving the relationship between the prime
implicants and the minterms constituting the logic expression. The prime implicant chart gives an
idea to have a set of minimum number of prime implicants which cover all minterms. Thus the
number of minimal set of prime implicants may be more than one which cover all minterms. To
find a subset of prime implicants which are essential part to cover all minterms or which are
found in all such subsets which covers the given minterms, are known as essential prime
implicants.

Thus the simplified expression for a given logic function consists of all essential
prime implicants and one or more prime implicants. In Prime implicant chart have all prime
implicants found in row wise and all minterms in column wise. Put a tick mark against the
minterms which are covered by individual prime implicants. Find the minterms which are
covered by only one prime implicant. These prime implicants will be the essential prime
implicants. After finished with finding all essential prime implicants, find the set of prime
implicants necessary to cover all other minterms.

Example: Obtain the set of prime implicants for

Column 1 Column 2 Column 3
Min
Binary
terms
Designation
a b d a b d a b d
c c c
0 0 0 –
(0,1) √
Grou 0 0 0 0 √ – 0 0 – V
0 (0,1,8,9)
p0 – 0 0 0
(0,8) √
0 0 0 1 √ – 0 0 1
1 (1,9) √
Grou
p1 1 0 0 0 √ 1 0 0 –
8 (8,9) √
0 1 1 – √
(6,7)
0 1 1 0 √
6
Grou – 1 1 0 √ (6,7,14,15 – 1 1 – U
(6,14)
p2 1 0 0 1 √ )
9
1 – 0 1 X
(9,13)
0 1 1 1 √ (7,15) – 1 1 1
7 √
Grou 1 1 0 1 √ (13,15) 1 1 – 1
13 W
p3
1 1 1 0 √ (14,15) 1 1 1 –
14 √
Grou 1 1 1 1 √
15
p4

It is found that U, V, W and X are prime implicants. Now to find essential prime implicants from
Prime implicant chart.

√ √ √ √ √ √ √ √
Prime Implicants
Minterms 0 1 6 7 8 9 13 14 15
↓
U 6,7,14,15 X X X X
V 0,1,8,9 X X X X
W 13,15 X X

X 9,13 X X

In the column corresponding to minterms 0, 1, 6, 7, 8 there are only one entries and the prime
implicants covering them are U and V. Therefore U and V are considered as essential prime
implicants. Other than the above minterms they cover minterms 14 and 15 too. But minterm 13 is
not covered by these two essential prime implicants. Therefore along with U and V either W or
X can be used to represent the simplified Boolean expression.

Where �

Therefore the simplified logic expression can be given as

or

Example: Obtain the set of prime implicants for

Column 1 Column 2 Column 3
Min
Binary
terms
Designation
a c a b c d a b c d
b d
(1,3) 0 0 – 1 √ (1,3,5,7) 0 – – 1 Y
0 0
1 0 1 √
(1,5) 0 – 0 1 √ (1,5,9,13) – – 0 1 X
Grou 0 1
2 0 0 √
p1 (1,9) – 0 0 1 √ (2,3,6,7) 0 – 1 – W
1 0
8 0 0 √
(2,3) 0 0 1 – √ (8,9,12,13 1 – 0 – V
)

(2,6) 0 – 1 0 √

(8,9) 1 0 0 – √

(8,12) 1 – 0 0 √

(3,7) 0 – 1 1
√
0 1
3
0 1 √ (5,7) 0 1 – 1
√
0 1 0 √
5
1 (5,13) – 1 0 1
√
Grou 0 1 1 0 √ (5,7,13,15 – 1 – 1 U
6
p2 (6,7) 0 1 1 – )
√
1 0 0 1 √
9
(9,13) 1 – 0 1
√
1 1 0 0 √
12
(12,13 1 1 0 –
√
)
0 1 (7,15) – 1 1 1 √
7 1 1 √
Grou
p3 1 0 (13,15 1 1 – 1 √
13 1 1 √
)
Grou 1 1
15 1 1 √
p4

It is found that U, V, W, X and Y are prime implicants. Now to find essential prime implicants
from Prime implicant chart.

√ √ √ √ √ √ √ √ √ √
Prime Implicants
Minterms 1 2 3 5 6 7 8 9 12 13 15
↓
U 5,7,13,15 X X X X
V 8,9,12,13 X X X X
W 2,3,6,7 X X X X
X 1,5,9,13 X X X X
Y 1,3,5,7 X X X X

In the column corresponding to minterms 2, 6, 8 and 15 there are only one entries and the
prime implicants covering them are U, V and W. Therefore U, V and W are considered as
essential prime implicants. Other than the above minterms these essential prime implicants
cover additional minterms 3, 5, 7, 9, 12 and 13 too. But the minterm is not covered by the
essential prime implicants. Therefore along with U, V and W either X or Y can be used to cover
all minterms and represents the simplified Boolean expression.

Where

Therefore the simplified logic expression can be given as

or

Self Assessment Question: Obtain the set of prime implicants for the following expression

MC0062(A)4.6 Multiple Output functions
Multiple Output functions

Till now the single valued expressions were realized using Boolean rules and simplification with
Karnaugh Map methods. In practical case the problems are involved with the design of more
than one output with the given inputs.

• Individual logic expression is simplified. Separate K – maps or Quine McClusky method
are used for simplification.

• Both the expression uses same inputs and allowed to have same common minterms in
addition to the specific minterms for two.

Example: Simplify the given logic expressions with the given three inputs.

Solution:

Or

Case i.) Output is with

Case ii.) Output is with

Case ii) has a common term . Therefore realization requires lesser number of gates

Case i.) Output is with

Case ii) Output is with

Example: Minimize and implement the following multiple output functions

and

Solution: Note that the realization of multiple function involves SOP realization for function f1
and POS realization for function f2. K – map realization of functions for POS can be done by

having alternate SOP representation.

Self Assessment Question: Minimize the following multiple output function using K – map

and

Summary

• Boolean expressions can be simplified using the algebraic method or the Karnaugh map
method.
• There are two basic forms of Boolean expression the sum of product form and product of
sum forms.
• SOPs can be solved with minterm entries into the K-map with 1s for the respective terms
• Grouping of the terms were defined with predefined logic. Grouping of two, four, eight
or sixteen cells can be done with the entries 1s.
• Simplified logic expression is written in SOP form and is realized with simple gate
circuitry
• POS from can also be solved with K-map
• Quine Mcclusky is an other method to simplify the logic expression with possible more
number of entries used.
• Essesntial prime implicants are found using prime implicant chart.
• Combinational logic expressions with multiple output function are realized using basic
gagtes.

Terminal Questions:

1. Reduce the following expression using K – Map and implement using universal gate

a.

b.

2. Reduce using the K-map

a.

b.

c.

3. Obtain the set of prime implicants for the following expression

a.

b.

4. Minimize the following multiple output function using K – map

a.

b.

5. Minimize the following multiple output function using K – map

a. and

b.

Unit 6 Latches and Flip Flops

This unit has more clear and complete coverage on latches and flip flops. The edge triggered,
master-slave flip flops were discussed. More emphasis is been given on D and JK flip-flops.

Introduction

Usually switching circuits are either combinational or sequential type. The switching circuits
studied till now are the combinational circuits whose output level at any instant of time
dependent on the present inputs because these circuits have no memory or storage. Where as in
sequential circuits the logic used is such that output depends not only on the present inputs but
also on the previous input/outputs. Thus concept of requirement of memory units in the logic is
to be studied.

A simple memory unit is the flip-flop. A flip-flop can be thought as an assembly of logic gates
connected such a way that it permits the information to be stored. Usually flip-flops used are
memory elements stores 1 bit of information over a specific time. Flip-flops forms the
fundamental components of shift registers and counters.

Objectives:

By the end of this chapter, reader should be able to explain

• The concept of basic Latch
• Active low and High concept used in Latches.
• What are the gated latches?
• What are the flip-flops and the concept of edge triggering
• Concept of the use of asynchronous inputs like PRESET and CLEAR.
• Concept of Master and Slave J-K flip-flop.

MC0062(A)6.2 Latches The S-R Latch
Latches: The S-R Latch

The latch is a bi-stable device. The term bi-stable refers with respect to the output of the device
that can reside in either of two states and a feedback mechanism is used. These are similar to the
flip-flops in that even flip-flops are bi-stable devices. The difference between the two is in the
method used for changing their output state.

It is known as SET-RESET (S-R) latch. It has two inputs labeled as S and R and two outputs
labeled as indicating a HIGH or 1 and indicating a LOW or 0. The two outputs and

are complementary to each other. The figure 6.1 shows logic symbol and the table 6.1 gives the
truth table of a S-R latch.

Figure 6.1: S-R Latch Logic Symbol

Inputs Output
Comments
S R
0 0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 ? ? Invalid

Table 6.1: Truth table of S-R Latch

From table 6.1 when SET input or S is HIGH or 1, output SETs or becomes 1 (inturn
becomes 0) and when RESET input or R is HIGH output RESETs or becomes 0 (inturn
becomes 1). Thus the name S-R latch. If both the inputs S and R are LOW or 0 then the output
retain the previous state or there is no change in the output state compared to the previous state.
If both the inputs are HIGH or 1, then the output of the latch is unpredictable or indicates invalid
state.

Active HIGH S-R Latch (NOR gate S-R Latch)

An NOR gate active high S-R latch can be constructed and is shown in figure 6.2 which has two
cross connected or coupled NOR gate circuitry.

Figure 6.2 active HIGH S-R Latch

Case i.) Assume the latch output is initially SET, = 1 and = 0. if the inputs are S = 0 and R
=0. The inputs of G1 are 0 and 0 therefore output retains at = 1. The inputs of G2 are 0 and 1

therefore its output is 0. Similarly if = 0 and = 1 initially and if the inputs are S = 0 and R

=0. The inputs of G2 are 0 and 0 therefore its output retains at = 1. The inputs of G1 are 0 and 1
therefore its output is 0.

Therefore when S = 0 and R = 0 the output of the latch retains the previous state without
any change, or no change in the output.

Case ii.) Assume the latch output is initially SET, = 1 and = 0 and if the inputs are S = 1 and

R =0 are applied to the latch. The inputs of G2 are 1 and 1, therefore its output is 0. The inputs

of G1 are 0 and 0 therefore its output is 1. Similarly if = 0 and = 1 initially and if the inputs

are S = 1 and R = 0. The inputs of G2 are 1 and 0 therefore its output = 0. The inputs of G1 are
0 and a 0 therefore output is 1.

Therefore when S = 1 and R = 0 the output of the latch SETs.

Case iii.) Assume the latch output is initially SET, = 1 and = 0 and if the inputs are S = 0 and
R =1 are applied to the latch. The inputs of G1 are 1 and 0, therefore its output is 0. The inputs

of G2 are 0 and 0 therefore its output is 1. Similarly if = 0 and = 1 initially and if the inputs
are S = 0 and R = 1. The inputs of G1 are 1 and 1 therefore its output is 0. The inputs of G2 are

0 and a 0 therefore output is 1.

Therefore when S = 0 and R = 1 the output of the latch RESETs.

Case iv.) If the inputs are S = 1 and R =1 the corresponding outputs are = 0 and =0
which is an invalid combination

The operation of the active-HIGH NOR latch can be summarized as follows

1. SET = 0 and RESET = 0: has no effect on the output state from its previous state.

2. SET = 1 and RESET = 0: always sets the output = 1 and =0

3. SET = 0 and RESET = 1: always resets the output = 0 and = 1
4. SET = 1 and RESET = 1: the condition tries to set and reset the output of the latch at the
same time or output is unpredictable. This state is referred as invalid state.

Active Low S-R Latch ( NAND Gate S-R Latch)

A NAND gate active high S-R latch can be constructed and is shown in figure 6.3 which has two
cross connected or coupled NAND gate circuitry.

Figure 6.3: active LOW S-R Latch

Inputs Output
Comments
S R
0 0 ? ? Invalid
0 1 1 0 SET
1 0 0 1 RESET
1 1 No change


The operation of the active-LOW NAND latch can be summarized as follows

1. SET = 0 and RESET = 0: the condition tries to set and reset the output of the latch at the
same time or output is unpredictable. This state is referred as invalid state.

2. SET = 0 and RESET = 1: always sets the output = 1 and =0
3. SET = 1 and RE

4. SET = 0: always resets the output = 0 and = 1
5. SET = 1 and RESET = 1: has no effect on the output state from its previous state.

Active HIGH NAND latch can be implemented whose circuit diagram is shown in figure 6.4 and
its truth table is shown in table 6.3

Figure 6.4: active HIGH S-R Latch

Inputs Output
Comments
S R

0 0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 ? ? Invalid



1. What do you mean by latch?

Explain the working of NAND gate based latch operation.

MC0062(A)6.3 Gated Latches
Gated Latches

The latches described in section 6.2 are known as asynchronous latches. The term asynchronous
represents the output changes the state any time with respect to the conditions on the input
terminals. To enable the control over the latch output gated latches are used. A control pin or an
enable pin EN is used which controls the output of the latch. The latches with the output
controlled with an enable input are known as gated latch or synchronous latch or flip-flop.

Gated S-R Latches

When pin EN is HIGH the input S and R controls the output of the flip-flop. When EN pin is
LOW the inputs become ineffective and no state change in the output of the flip-flop. Since a
HIGH voltage level on the EN pin enables or controls the output of the latch, gated latches of
these types are also known as level triggered latches or flip-flops.

The logic symbol and the truth table of the gated latch are shown in figure 6.5 and table 6.4 and
the logic diagram of gated S-R flip-flop is shown in figure 6.6.

Figure 6.5: S-R Latch Logic Symbol

Fig. 6.6: Gated Latch or Flip-flop

Inputs Output Comments
EN
S R

0 0 High No change
0 1 High 0 1 RESET
1 0 High 1 0 SET
1 1 High ? ? Invalid

Table 6.4: Truth table of gated S-R Latch

Figure 6.7: Waveform of gated S-R latch

Gated D-Latch or D-flip-flop

The S-R flip-flop makes use of four input combinations and in many applications S = R = 0 and
S = R = 1 are never used. This represents that S and R are always complement to each other. The
input R can be obtained by inverting the input S.

The concept of D flip-flop has only one input data pin D along with the control logic over latch
i.e EN pin. With the enable pin EN is HIGH and D = 1, we have S = 1 and R = 0 which SETs the
input. With the enable pin EN is HIGH and D = 0, we have S = 0 and R = 1 which RESETs the
input.

The logic symbol and the truth table of the gated D-latch are shown in figure 6.8 and table 6.5
and the logic diagram of gated S-R flip-flop is shown in figure 6.9.

Figure 6.8: Gated D Latch Logic Symbol

Fig 6.9: Gated D-Latch or D-flip-flop

Input Output
EN Comments
D
0 High 0 RESET
1 High 1 SET

Table 6.5: Truth table of gated D-Latch or D-flip-flop

Figure 6.10: Waveform of Gated D-Latch


1. What do you mean by gated latch?

Explain the working of gated D-latch.

MC0062(A)6.4 Edge triggered Flip-Flops
Edge triggered Flip-Flops

The logic systems or digital systems operate either synchronously or asynchronously. In
asynchronous systems when one or more input changes the output of the logic system changes.
In synchronous systems output changes with respect to a control or enable signal usually these
signals are known as clock signal.

A flip-flop circuit which uses the clock signal is known as clocked flip-flops. Many system
output changes occur when clock makes its transition. Clock transitions are defined as positive
transition when clock output changes from 0 to 1 and negative transition when clock output
changes from 1 to 0. The system outputs make changes during either of these transitions are
known as edge triggered systems. Edge triggering is also known as dynamic triggering.

Flip-flops whose output changes during positive transition of the clock are known as positive
edge triggered flip-flop and the flip-flops which change its output during negative transition of
the clock are known as negative edge triggered flip-flop.

Positive edge triggering is indicated by a triangle at the clock terminal and negative edge
triggering is indicated by a triangle with a bubble at the clock terminal. There are three basic
types of edge-triggered flip-flops. S-R flip-flop, J-K flip-flop and D flip-flops.

Edge triggered S-R Flip-Flop (S-R FF)

Figure 6.11 and figure 6.12 indicates the positive edge triggered and negative edge triggered S-R
flip-flops. Figure 6.13 gives the simplified circuitry of edge triggered S-R FF. The S and R
inputs are known as synchronous control inputs. Without a clock pulse these inputs cannot
change the output state. The table 6.6 and table 6.7 give the truth table for S-R FF for positive
and negative edge triggering.

Fig. 6.13: edge triggered S-R flip-flop

Inputs Output
Clock Clk Comments
S R

0 0 ↑ No change

0 1 ↑ 0 1 RESET
1 0 ↑ 1 0 SET
1 1 ↑ ? ? Invalid

Table 6.6: Truth table for positive edge triggered S-R flip-flop

Inputs Output
Clock Clk Comments
S R

0 0 ↓ No change
0 1 ↓ 0 1 RESET
1 0 ↓ 1 0 SET
1 1 ↓ ? ? Invalid

Table 6.7: Truth table for negative edge triggered S-R flip-flop

Figure 6.14: waveforms for positive edge triggered S-R flip-flop

Edge triggered D-Flip-Flop (D-FF)

Figure 6.11 and figure 6.12 indicates the positive edge triggered and negative edge triggered D
flip-flops. Figure 6.15 gives the simplified circuitry of edge triggered D FF. There is only one
input D. Without a clock pulse the input cannot change the output state. The table 6.8 and table
6.9 give the truth table for D-FF for positive and negative edge triggering.

Figure 6.15: edge triggered D-FF

Input Clock Output
Comments
D Clk
0 ↑ 0 RESET
1 ↑ 1 SET

Table 6.8: Truth table for positive edge triggered D- flip-flop

Input Output
Clock Clk Comments
D
0 ↓ 0 RESET
1 ↓ 1 SET

Table 6.9: Truth table for negative edge triggered D- flip-flop

Figure 6.16: waveforms for negative edge triggered D- flip-flop

Edge triggered J-K Flip-Flop (J-K FF)

Figure 6.11 and figure 6.12 indicate the positive edge triggered and negative edge triggered J-K
flip-flops. Figure 6.17 gives the simplified circuitry of edge triggered J-K FF. These are similar to
S-R FFs except that J-K FFs has no invalid state. Therefore J-K FFs are versatile and mostly used
FFs. Without a clock pulse the inputs J and K cannot change the output state. The table 6.10 and
table 6.11 give the truth table for J-K FF for positive and negative edge triggering.

Figure 6.17: edge triggered J-K FF

1. When J = 0 and K = 0: no change of state when a clock pulse is applied
2. When J = 0 and K = 1: output resets on positive/negative going edge of the clock pulse applied.
3. When J = 1 and K = 0: output sets on positive/negative going edge of the clock pulse applied.
4. When J = 1 and K = 1: output toggles between two states 0 and 1 for every positive/negative
going edge of the clock pulse applied.

Inputs Output
Clock Clk Comments
J K

0 0 ↑ No change
0 1 ↑ 0 1 RESET
1 0 ↑ 1 0 SET
1 1 ↑ Toggle

Table 6.10: Truth table for positive edge triggered J-K flip-flop

Table 6.11: Truth table for negative edge triggered J-K flip-flop

Figure 6.23: waveforms for negative edge triggered J-K flip-flop


1. What do you mean by level triggered FF and an edge triggered FF.

Explain the working of positive and negative edge triggered J-K flip-flop.

MC0062(A)6.5 Asynchronous inputs
PRESET and CLEAR
Asynchronous inputs: PRESET and CLEAR

Edge triggered or synchronous FFs were studied in section 6.3 and 6.4 were the S-R, D and J-K
inputs are called as synchronous inputs. The effect of these signals on the output is
synchronised with the clock pulse or the control pulse.

ICs consistis of one or more asynchronous inputs which work independently of the synchronous
and clock inputs. These asynchronous inputs are used to control the output of a given flip-flop
to PRESET (priorly set to 1) or to CLEAR (priorly set to 0). Usually active low PRESET (PRE pin)
and active low CLEAR (CLR pin) are used. Figure 6.19 gives the logic symbol of J-K FF with active
LOW PRESET and active LOW CLEAR pins and the truth table 6.12 gives its function.

Figure 6.19: negative edge triggered J-K FF with active low PRESET and CLEAR

Figure 6.20: Logic diagram of edge triggered J-K FF with active low PRESET and CLEAR

1. PRE = 0 and CLR = 0 not used
2. PRE = 0 and CLR = 1 is used to PRESET or SET the output to 1.
3. PRE = 1 and CLR = 0 is used to CLEAR or RESET the output to 0.

PRE = 1 and CLR = 1 is used to have clocked or edge triggered operation of FF.

MC0062(A)6.6 Master-Slave J-K Flip Flop
Master-Slave J-K Flip Flop

Master-slave FFs were developed to make the synchronous operation more predictable. A known
time delay is introduced between the time that the FF responds to a clock pulse and the time

response appears at its output. It is also known as pulse triggered flip-flop due to the fact that the
length of the time required for its output to change state equals the width of one clock pulse.

A master-slave FF actually consists of two FFs. One is known as master and the other as slave.
Control inputs are applied to the master FF prior to the clock pulse. On the rising edge of the
clock pulse output of the master is defined by the control inputs. The falling edge of the clock
pulse, the state of the master is transferred to the slave and output of the slave are taken as and

. Note that the requirement in the master-slave that the input must be held stable while clock is
HIGH. Figure 6.21 indicates the logic diagram of J-K master slave FF. Truth table is shown in
table 6.12

Figure 6.21: Logic diagram of JK Master Slave FFs

Table 6.12: Truth table for negative edge triggered J-K flip-flop

Figure 6.22: waveforms for master slave J-K flip-flop

T – Flip-Flop

The concept of J-K flip-flop with both J = 1 and K = 1 leads the output to toggle between the two
possible states 0 and 1. Thus the concept of Toggle flip-flop or T flip-flop is to have both J = 1
and K = 1 all time or connect both J and K to HIGH all time and apply the clock pulse. Figure
6.23 shows the logic block diagram of the T – flip-flop. The table 6.13 shows the truth table of T
– flip-flop.

Table 6.13: Truth table of T flip-flop

Self Assessment Question

• Explain the working of Toggle flip flop
• Give the timing diagram of the toggle flop flop

Summary

• Latches are bistable elements whose state normally depends on asynchronous inputs.

• Edge triggered flip-flops are bistable elements with synchronous inputs whose state
depends on the inputs only at the triggering transition of a clock pulse.
• Changes in the output of the edge triggered flip-flops occur at the triggering transition of
the clock.
• Pulse triggered or master-slave flip-flops are bistable elements with synchronous inputs
whose state depends on the inputs at the leading edge of the clock pulse, but whose
output is postponed and does not reflect the internal state until the trailing clock edge.
• The synchronous inputs should not be allowed to change while the clock is HIGH.

Terminal Question

1. What is latch and Flip flop
2. Explain the difference between synchronous and asynchronous latches
3. Describe the main features of gated S-R latch and edge triggered S-R flip-flop operations.
4. Explain the concept of toggling in J-K FF.
5. Describe the operation of master – slave concept of JK flip flop.

MC0062(A)6.6 Master-Slave J-K Flip Flop
Master-Slave J-K Flip Flop

Master-slave FFs were developed to make the synchronous operation more predictable. A known
time delay is introduced between the time that the FF responds to a clock pulse and the time
response appears at its output. It is also known as pulse triggered flip-flop due to the fact that the
length of the time required for its output to change state equals the width of one clock pulse.

A master-slave FF actually consists of two FFs. One is known as master and the other as slave.
Control inputs are applied to the master FF prior to the clock pulse. On the rising edge of the
clock pulse output of the master is defined by the control inputs. The falling edge of the clock
pulse, the state of the master is transferred to the slave and output of the slave are taken as and

. Note that the requirement in the master-slave that the input must be held stable while clock is
HIGH. Figure 6.21 indicates the logic diagram of J-K master slave FF. Truth table is shown in
table 6.12

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