Assembly language programming(unit 4)


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Assembly language programming(unit 4)

  1. 1. Assembly Language Programming Unit 4
  2. 2. Introduction <ul><li>Machine Language Programming </li></ul><ul><li>One way to write a program is to assign a fixed binary pattern for each instruction and represent the program by sequencing these binary patterns. </li></ul><ul><li>Such a program is called a Machine language program or an object program </li></ul>
  3. 3. Eg: <ul><li>0011 1110 ; LOAD A Register with </li></ul><ul><li>0000 0101 ; Value 5 </li></ul><ul><li>0000 0110 ; LOAD B Register with </li></ul><ul><li>0000 0110 ; Value 10 </li></ul><ul><li>1000 0000 ; A <- A + B </li></ul><ul><li>0011 1010 ; store the result </li></ul><ul><li>0110 0100 ; into the memory location </li></ul><ul><li>0000 0000 ; whose address is 100 </li></ul><ul><li>0110 0110 ; halt processing </li></ul>
  4. 4. <ul><li>Use of symbols in programming to improve the readability. </li></ul><ul><li>Giving symbolic names for each instruction. </li></ul><ul><li>These names are called mnemonics and a program written using these symbols are called as Assembly Language Program . </li></ul>Assembly Language Programming
  5. 5. Eg: <ul><li>LOAD A, 5 ; load A reg with 5 </li></ul><ul><li>LOAD B, 10 ; load B reg with 10 </li></ul><ul><li>ADD A, B ; A = A + B </li></ul><ul><li>LOAD (100), A ; save the result in location 100 </li></ul><ul><li>HALT ; halt processing </li></ul>
  6. 6. Features of ALP <ul><li>For using Assembly language, the programmer needs to know the internal Architecture of the Microprocessor. </li></ul><ul><li>The Assembly language written for one processor will not usually run on other processors. </li></ul><ul><li>An assembly language program cannot be executed by a machine directly, as it not in a binary form. </li></ul>
  7. 7. <ul><li>An Assembler is needed in order to translate an assembly language (source pgm) into the object code executable by the machine. </li></ul><ul><li>Unlike the other programming languages, assembly language is not a single language, but rather a group of languages. </li></ul><ul><li>Each processor family (and sometimes individual processors within a processor family) has its own assembly language. </li></ul>
  8. 8. Comparison of Assembly language with High level languages <ul><li>Assembly languages are close to a one to one correspondence between symbolic instructions and executable machine codes. </li></ul><ul><li>Assembly languages also include directives to the assembler, directives to the linker, directives for organizing data space, and macros. </li></ul><ul><li>Assembly language is much harder to program than high level languages. The programmer must pay attention to far more detail and must have an intimate knowledge of the processor in use. </li></ul>
  9. 9. <ul><li>High level languages are abstract. Typically a single high level instruction is translated into several (sometimes dozens or in rare cases even hundreds) executable machine language instructions. </li></ul><ul><li>Modern object oriented programming languages are highly abstract </li></ul>
  10. 10. <ul><li>But high quality assembly language programs can run much faster and use much less memory and other resources than a similar program written in a high level language. </li></ul><ul><li>Speed increases of 2 to 20 times faster are fairly common, and increases of hundreds of times faster are occasionally possible. </li></ul><ul><li>Assembly language programming also gives direct access to key machine features essential for implementing certain kinds of low level routines, such as an operating system kernel or microkernel, device drivers, and machine control. </li></ul>
  11. 11. <ul><li>  High level programming languages are much easier for less skilled programmers to work in and for semi-technical managers to supervise. </li></ul><ul><li>High level languages allow faster development times than work in assembly language, even with highly skilled programmers. </li></ul><ul><li>Development time increases of 10 to 100 times faster are fairly common. </li></ul><ul><li>Programs written in high level languages (especially object oriented programming languages) are much easier and less expensive to maintain than similar programs written in assembly language (and for a successful software project, the vast majority of the work and expense is in maintenance, not initial development). </li></ul>
  12. 12. Advantages:- <ul><li>Performance : An expert Assembly language programmer can often produce code that is much smaller and much faster than a high level language programmer can. For some applications speed and size are critical. Eg:- code on a smart card, code in a cellular telephone, device drivers, BIOS routines etc. </li></ul><ul><li>2. Access to the Machine : Procedures can have complete access to the Hardware (Not possible in High level language) </li></ul><ul><li>eg: low level interrupt and trap handlers in OS </li></ul>
  13. 13. <ul><li>1 . Labels :Begins from column1. Should start with a letter. After the letter a combination of letters and numbers may be used. Restricted by most assemblers from 6 to 8 characters. Use is to identify opcodes and operands. Are needed on executable statements, so that the statement can be branched to. </li></ul>Format of Assembly program LABEL OPCODE OPERAND COMMENTS
  14. 14. <ul><li>2. Opcode : Symbolic abbreviations for operation codes or comment to the Assembler. Specifies how data are to be manipulated, which is residing within a microprocessor register or in the main memory. Eg: MOV, LD, ADD </li></ul><ul><li>3. Operand : use to specify the addresses or registers used by the operands by the Machine instructions. Operands may be Registers, memory location, constants etc. </li></ul><ul><li>4. Comments : prefixed by ; for documentation </li></ul>
  15. 15. <ul><li>NEXT: ADD AL,07H ; ADD 07H to AL register </li></ul>LABEL OPCODE OPERAND COMMENTS Eg
  16. 16. 8086 CPU ARCHITECTURE <ul><li>The microprocessors functions as the CPU in the stored program model of the digital computer. </li></ul><ul><li>Its job is to generate all system timing signals and synchronize the transfer of data between memory, I/O, and itself </li></ul><ul><li>The microprocessor also has a S/W function. </li></ul><ul><li>It must recognize, decode, and execute program instructions fetched from the memory unit. </li></ul><ul><li>This requires an Arithmetic-Logic Unit (ALU) within the CPU to perform arithmetic and logical (AND, OR, NOT, compare, etc) functions . </li></ul>16 –bit processor
  17. 17. <ul><li>8086 is Intel’s first 16-bit microprocessor designed in 1978 </li></ul><ul><li>Here the 16 bit means that its ALU, its internal registers, and most of its instructions r designed to work with 16-bit binary words. </li></ul><ul><li>8086 has a 16 bit data bus , so it can read data from or write data to memory either 16 bits or 8 bits at a time. </li></ul><ul><li>8086 has a 20-bit address bus, can access up to 1MB(2 20 ) ie, 1,048,576 memory locations. </li></ul><ul><li>16 bit word will b stored in 2 consecutive memory locations. </li></ul><ul><li>Packaged in a 40 pin Integrated Circuit </li></ul>
  18. 18. 8086 Internal Architecture
  19. 19. <ul><li>Divided into 2 functional units </li></ul><ul><li>BIU(Bus Interface Unit) and </li></ul><ul><li>EU(Execution Unit) </li></ul><ul><li>BIU fetches instructions, reads data from memory and I/O ports and writes data to memory I/O ports. It handles all transfers of data and addresses on the buses for the Execution Unit(EU). </li></ul><ul><li>Execution Unit(EU) e xecutes instructions that have already been fetched by the BIU; tells BIU where to fetch instructions or data from, decodes and executes instructions. </li></ul>
  20. 20. <ul><li>BIU and EU function independently </li></ul><ul><li>BIU interfaces 8086 to outside world </li></ul><ul><li>BIU provides all external bus operations </li></ul><ul><li>BIU contains segment registers, instruction pointer, instruction queue and address generation/bus control circuitry to provide functions such as fetching and queuing of instructions and bus control </li></ul>
  21. 21. <ul><li>BIU’s instruction queue is FIFO (First In First Out) group of Registers in which up to 6 bytes of instruction code are pre fetched from memory ahead of time. This is called as pipelining </li></ul><ul><li>This is done in order to speed up program execution by overlapping instruction fetch with execution. </li></ul><ul><li>BIU has four 16-bit Segment Registers </li></ul><ul><li>Code Segment(CS), Data Segment(DS), Stack Segment(SS) and the Extra Segment(ES) Register </li></ul>
  22. 22. Register Structure <ul><li>8086 has thirteen 16 bit registers and 9 flags. </li></ul>
  23. 26. <ul><li>SP :All PUSH and POP operations derive their address from SP. </li></ul><ul><li>It points to the current top of the stack. </li></ul><ul><li>BP : within one stack there may b several data areas. </li></ul><ul><li>This register can b used to hold the offset of the base of a data area in the current stack segment. </li></ul><ul><li>SI & DI :there r certain string operations provided by 8086. </li></ul><ul><li>Eg: MOV a string of bytes or word from one area to another. </li></ul><ul><li>SI and DI r used implicitly, in such instructions. </li></ul><ul><li>Eg:A string move instruction MOVS, SI points to the source string byte to b moved and DI points to the corresponding destination byte. </li></ul>
  24. 27. <ul><li>IP Instruction Pointer – is a 16 bit register and points to the next instruction to be executed within the current code segment. </li></ul><ul><li>It is automatically updated by the 8086 as program execution proceeds. </li></ul><ul><li>Flag register in the EU holds the status flags typically after an ALU operation. </li></ul>
  25. 28. Flag Register Carry Flay- set carry out of MSB Parity Flag-set if res. has even Auxiliary carry for BCD Zero flag-set if res. is 0 Sign Flag=MSB of res TrapFlag Interrupt Enable Flag String Direction Flag Overflow Flag
  26. 29. All Registers
  27. 30. Segment Registers <ul><li>Within the 1 MB of memory space the 8086 defines four 64K-byte memory blocks called the code segment, stack segment, data segment, and extra segment . </li></ul><ul><li>Each of these blocks of memory is used differently by the processor. </li></ul><ul><li>The code segment holds the program instruction codes. </li></ul><ul><li>The data segment stores data for the program. </li></ul><ul><li>The extra segment is an extra data segment (often used for shared data). </li></ul><ul><li>The stack segment is used to store interrupt and subroutine return addresses. </li></ul>CS,SS, DS,ES
  28. 31. Extra Segment Stack Segment Data Segment Code Segment 00500 006FF 00700 007FF 00900 0098F 00990 00A00 0050 0070 0090 0099 Unused Area CS DS SS ES Memory Segmentation in 8086
  29. 32. <ul><li>The four segment registers (CS, DS, ES, and SS) are used to &quot;point&quot; at location 0 (the base address) of each segment. </li></ul><ul><li>This is a little &quot;tricky&quot; because the segment registers are only 16 bits wide, but the memory address is 20 bits wide. </li></ul><ul><li>The BIU takes care of this problem by appending four 0's to the low-order bits of the segment register. </li></ul><ul><li>In effect, this multiplies the segment register contents by 16. </li></ul>
  30. 33. Address Formation <ul><li>How the 20-bit address is formed? </li></ul><ul><li>Assume that the IP contains 0080H. </li></ul><ul><li>This means that the next instruction byte is located at address 0080H within the current code segment. </li></ul><ul><li>The 20 bit adrs of this instruction is formed as follows: </li></ul><ul><li>CS*16+IP=00500+0080=00580H. </li></ul><ul><li>Thus the actual adrs of the instruction is transformed to the 20-bit addresses using an appropriate segment register. </li></ul><ul><li>This adrs transformation is known as relocation . </li></ul><ul><li>As the segment registers r used for relocation of adrses, they r also called segment relocation registers. </li></ul>
  31. 34. Addressing Modes <ul><li>The way in which an operand is specified is called the Addressing Mode . </li></ul><ul><li>The 8086 processor supports: </li></ul><ul><li>Register AM </li></ul><ul><li>Immediate </li></ul><ul><li>Direct </li></ul><ul><li>Indirect mode through Base registers </li></ul><ul><li>Indirect mode through Index registers </li></ul><ul><li>Indirect mode through Sum of Base and Index Registers </li></ul>
  32. 35. <ul><li>Relative mode through Base Register </li></ul><ul><li>Relative mode through Index Register </li></ul><ul><li>Relative mode through Base and Index Register. </li></ul><ul><li>Implied Addressing mode </li></ul>
  33. 36. <ul><li>Simplest of all addressing modes </li></ul><ul><li>Specifies the source operand, destination operand or both to be contained in an 8086 register. </li></ul><ul><li>Transfers a copy of a byte or word from source register to destination register </li></ul><ul><li>eg:- MOV AX, BX </li></ul><ul><li>ADD AX, BX </li></ul>1.Register Addressing mode
  34. 37. 2.Immediate Addressing mode <ul><li>Transfers immediate byte or word of data into the destination Register </li></ul><ul><li>E.g.: MOV AX, 0FAH </li></ul><ul><li> ADD BX, 4 </li></ul>
  35. 38. 3.Direct Addressing mode <ul><li>Address of the operand is directly specified in the instruction itself. </li></ul><ul><li>Moves a byte or word between a memory location and a register </li></ul><ul><li>E.g.: MOV [1234H], AX </li></ul><ul><li>Suppose DS contains 1000H </li></ul><ul><li>EA is DS X 10H + 1234H = 10000H + 1234H </li></ul><ul><li> = 11234H </li></ul>
  36. 39. 4.Indirect Mode through Base Registers <ul><li>Memory location is specified by Base Registers. </li></ul><ul><li>E.g.: MOV [BX], CX </li></ul>5.Indirect Mode through Index Registers <ul><li>Memory location is specified by Index Registers </li></ul><ul><li>E.g.: MOV [SI], CX </li></ul>
  37. 40. 6.Indirect Mode through Sum of Base and Index Registers <ul><li>Memory location specified by sum of Base and index Registers </li></ul><ul><li>E.g.: MOV [BX+SI], CX </li></ul>7.Relative mode through Base Register <ul><li>Memory location addressed by Base register plus a displacement </li></ul><ul><li>E.g.: MOV [BX+4], CX </li></ul>
  38. 41. 8.Relative mode through Index Register <ul><li>Memory location addressed by Index register plus a displacement </li></ul><ul><li>E.g.: MOV [SI+4], CX </li></ul>9.Relative mode through Base and Index Register <ul><li>Memory location addressed by Base and index register plus a displacement </li></ul><ul><li>E.g.: MOV ARRAY[BX+SI],DX </li></ul>
  39. 42. 10.Implied Addressing mode <ul><li>Instructions using this mode have no operands. </li></ul><ul><li>E.g.: CLC ; clears the carry flag to zero </li></ul>
  40. 43. <ul><li>Can b classified as shown: </li></ul><ul><li>1. Data Transfer Instructions </li></ul><ul><li>2. Arithmetic Instructions </li></ul><ul><li>3. Bit Manipulation Instructions </li></ul><ul><li>4. String Instructions </li></ul><ul><li>5. Program Execution Transfer Instructions. </li></ul><ul><li>6. Processor Control Instructions. </li></ul>8086 Instruction Set
  41. 44. 1.Data-transfer Instructions <ul><li>MOV : copy byte or word from specified source to destn. MOV AX, BX </li></ul><ul><li>PUSH : copy specified word to top of the stack. PUSH BX </li></ul><ul><li>POP : copy word from TOS to specified location. POP CX </li></ul><ul><li>PUSHA/POPA : copy all registers to stack and copy words from stack to all regs. </li></ul><ul><li>XCHG : Exchange byte or word. </li></ul><ul><li>XCHG DX, AX </li></ul>A. General purpose byte or word instructions
  42. 45. <ul><li>IN :copy a byte or word from specified byte to accumulator. IN AL, 028h </li></ul><ul><li>OUT :copy a byte or word from accumulator to specified port. OUT 028h,AL </li></ul>B. Simple I/O port transfer instructions
  43. 46. <ul><li>LEA : Load Effective Address of operand to specified register. LEA BX, START. </li></ul><ul><li>LDS : Load DS register and other specified register from memory. </li></ul><ul><li>LES : Load ES register and other specified register from memory. </li></ul>C. Special Address transfer Instructions
  44. 47. <ul><li>LAHF : Load (Copy to) AH with the low byte of the flag register. </li></ul><ul><li>SAHF : Store (copy) AH register to low byte of flag register. </li></ul><ul><li>PUSHF : copy flag register to TOS </li></ul><ul><li>POPF : copy word at TOS to flag register. </li></ul>D.Flag transfer instructions
  45. 48. 2.Arithmetic Instructions <ul><li>ADD : Add specified byte to byte or specified word to word. ADD AX, BX </li></ul><ul><li>ADC : add byte+ byte+ carry flag or word+ word+ carry flag . </li></ul><ul><li>INC : increment specified byte or specified word by 1.INC AX </li></ul><ul><li>AAA : ASCII Adjust after Addition </li></ul><ul><li>DAA : Decimal (BCD) adjust after addition </li></ul>A. Addition Instructions
  46. 49. <ul><li>SUB :subtract byte from byte or word from word. SUB AX, BX </li></ul><ul><li>SBB : Subtract byte and carry flag from byte or word and carry flag from word. </li></ul><ul><li>DEC : Decrement the specified byte or specified word by 1. </li></ul><ul><li>NEG : Negate-invert each bit of a specified byte or word and add 1(2’s complement). </li></ul><ul><li>CMP : compare 2 specified bytes or 2 specified words. </li></ul><ul><li>AAS : ASCII Adjust after Subtraction. </li></ul><ul><li>DAS : Decimal (BCD) adjust after subtraction </li></ul>B. Subtraction Instructions
  47. 50. <ul><li>MUL : Multiply unsigned byte by byte or unsigned word by word. </li></ul><ul><li>IMUL : Multiply signed… </li></ul><ul><li>AAM : ASCII Adjust after multiplication </li></ul>C. Multiplication instructions
  48. 51. <ul><li>DIV : Divide unsigned word by byte or unsigned double word by word </li></ul><ul><li>IDIV : Divide Signed… </li></ul><ul><li>AAD : ASCII Adjust before division. </li></ul><ul><li>CBW : Fill upper byte of word with copies of sign bit of lower byte. </li></ul><ul><li>CWD : fill upper word of double word with sign bit of lower word. </li></ul>D. Division Instructions
  49. 52. 3. Bit Manipulation Instructions <ul><li>NOT : Invert each bit of a byte or word </li></ul><ul><li>AND :AND each bit in a byte or word with the corresponding bit in another byte or word. </li></ul><ul><li>OR : OR… </li></ul><ul><li>XOR : XOR… </li></ul><ul><li>TEST : AND operands to update flags , but don’t change operands. </li></ul>A. Logical Instructions
  50. 53. <ul><li>SHL/SAL : Shift bits of word or byte left, put Zeros in LSB </li></ul><ul><li>SHR : Shift bits of word or byte right, put 0s in MSBs. </li></ul><ul><li>SAR : Shift bits of word or byte right , copy old MSB into new MSB. </li></ul>B. Shift Instructions
  51. 54. <ul><li>ROL : Rotate bits of byte or word left, MSB to LSB and to CF. </li></ul><ul><li>ROR: Rotate bits of byte or word right, LSB to MSB and CF. </li></ul><ul><li>RCL : Rotate bits of byte or word left, MSB to CF and CF to LSB. </li></ul><ul><li>RCR : Rotate bits of byte or word right, LSB to CF and CF to MSB. </li></ul>C. Rotate Instructions
  52. 55. 4. String Instructions <ul><li>A String is a series of bytes or a series of words in sequential memory locations. </li></ul><ul><li>A String often consists of ASCII character codes. </li></ul><ul><li>B- used to indicate that a string of bytes is to b acted upon. </li></ul><ul><li>W- used to indicate that a string of words is to b acted upon </li></ul>
  53. 56. <ul><li>REP : An instruction prefix. Repeat following instruction until CX=0. </li></ul><ul><li>REPE/REPZ : Repeat instruction until CX=0 or ZF<>1. </li></ul><ul><li>REPNE/REPNZ : Repeat instruction until CX=0 or ZF=1. </li></ul><ul><li>MOVS/MOVSB/MOVSW : move byte or word from 1string to another </li></ul><ul><li>COMPS/COMPSB/COMPSW : compare 2 strings byte/word </li></ul><ul><li>INS/INSB/INSW : input string byte or word from port. </li></ul>
  54. 57. <ul><li>OUTS/OUTSB/OUTSW : output string byte/word to port </li></ul><ul><li>SCAS/SCASB/SCASW : scan a string , compare a string byte with a byte in AL or a string word with a word in AX. </li></ul><ul><li>LODS/LODSB/LODSW : load string byte into AL or string word into AX. </li></ul><ul><li>STOS/STOSB/STOSW : store byte from AL or word from AX into string </li></ul>
  55. 58. <ul><li>CALL : call a procedure (sub program), save return address on stack </li></ul><ul><li>RET : return from procedure to calling program </li></ul><ul><li>JMP : go to specified address to get next instruction </li></ul>4. Program Execution transfer instructions A. Unconditional transfer
  56. 59. <ul><li>JA/JNBE : jump on above or jump on not below or equal </li></ul><ul><li>JC : jump on carry </li></ul><ul><li>JE/JZ : jump on equal or zero. </li></ul><ul><li>JO : jump on overflow…etc </li></ul>B. Conditional transfer
  57. 60. <ul><li>LOOP : Loop through a series of instructions until CX=0. </li></ul><ul><li>LOOPE/LOOPZ : Loop thru a seq. of instructions while ZF=1 and CX<>0. </li></ul><ul><li>LOOPNE/LOOPNZ : Loop thru a seq. of instructions while ZF=0 and CX<>0. </li></ul><ul><li>JCXZ : jump to specified adrs if CX=0 </li></ul>C. Iteration control instructions
  58. 61. <ul><li>INT : Interrupt pgm execution, call service procedure. </li></ul><ul><li>INTO : Interrupt pgm execution if OF=1. </li></ul><ul><li>IRET : Return from interrupt service procedure to main program. </li></ul>D. Interrupt instructions
  59. 62. 6.Processor Control Instructions <ul><li>STC : set CF to 1 </li></ul><ul><li>CLC : clear CF to 0. </li></ul><ul><li>CMC : complement CF </li></ul><ul><li>STD : set Direction Flag DF to 1(decrement string pointers) </li></ul><ul><li>CLD : clear DF to 0. </li></ul><ul><li>STI : set Interrupt enable flag to 1(enable INTR interrupt). </li></ul><ul><li>CLI : clear interrupt enable flag to 0 (disbale INTR interrupt) </li></ul>A. Flag set/clear Instructions
  60. 63. <ul><li>HLT : Halt (do nothing) until interrupt or reset. </li></ul><ul><li>WAIT : wait ( do nothing) until signal on the TEST pin is low. </li></ul><ul><li>ESC : escape to external coprocessor such as 8087 or 8089 </li></ul><ul><li>LOCK : an instruction prefix. Prevents another processor from taking the bus while adjacent instruction executes. </li></ul>B. External Hardware synchronization instructions
  61. 64. <ul><li>NOP : no action except fetch and decode. </li></ul>C. No operation instructions
  62. 65. 8086 Pin out Diagram
  63. 66. Min/Max mode operation
  64. 67. <ul><li>Minimum mode is one of the two different hardware modes of the Intel 8086 processor. </li></ul><ul><li>Mode selection is accomplished by how the chip is hard-wired in the circuit. </li></ul><ul><li>Specifically, pin #33 (MN/MX) is used to select the mode. </li></ul><ul><li>If it is wired to voltage (+5V) ,it is in MIN mode. </li></ul><ul><li>Changing the state of pin #33 changes the function of certain other pins. </li></ul><ul><li>Mode cannot be changed by software. </li></ul><ul><li>The minimum mode of operation is for small systems. </li></ul><ul><li>The 8086 is operated in MIN mode in systems such as SDK-86(System Design Kit) where it is the only microprocessor on the system bus </li></ul>Minimum mode operation
  65. 68. <ul><li>The pins that are available exclusively in the minimum mode are ( bold indicates active low ) </li></ul><ul><li>24-Interrupt Acknowledge – INTA- is a response to the INTR pin. </li></ul><ul><li>25-Address Latch Enable – ALE - indicates the 8086 adrs/data bus contains adrs infrmn. </li></ul><ul><li>26-Data Enable - DEN –external data bus buffers </li></ul><ul><li>27-Data Transmit/Receive - DT/ R- shows processors data bus is txing or rxing. </li></ul><ul><li>28-Status Line - M/ IO -selects memory or I/O </li></ul><ul><li>29-Write – WR- indicates that the 8086 is outputting data to memory or I/O devices. </li></ul><ul><li>30-Hold Acknowledge – HLDA-indicates the processor entered in a HOLD state </li></ul><ul><li>31-Hold – HOLD-it requests a DMA. </li></ul>
  66. 69. <ul><li>MAXIMUM mode is for large applications such as multiprocessing. </li></ul><ul><li>For MAX mode pin 33 should b wired to ground . </li></ul><ul><li>When MN/ MX is connected to ground the 8086 treats pin 24-33 in MAX mode. </li></ul>Maximum mode operation
  67. 70. The pins that are available exclusively in the maximum mode are <ul><li>24,25-QS1, QS0-Que Status -shows the status of the internal instruction queue. </li></ul><ul><li>26,27,28-s0,s1,s2-the status pins indicates the function of the current bus cycle. This signals r normally decoded by the 8288 bus controller. </li></ul><ul><li>29- LOCK- is used to lock peripherals of the system. </li></ul><ul><li>30,31- RQ/GT1,RQ/GT0- Request/Grant pin request DMA during max. mode operation. </li></ul>
  68. 71. INTEL 80386 –a 32 bit processor <ul><li>Intel’s 32-bit processor </li></ul><ul><li>Provides memory management , multitasking support , pipelined architecture , address translation caches , and a high-speed bus interface in a single chip </li></ul><ul><li>8 general purpose 32-bit registers </li></ul><ul><li>Processor can handle 8-bit, 16-bit and 32-bit data types (operands) </li></ul><ul><li>Can access up to 4 GB of main memory </li></ul><ul><li>Separate 32-bit data and address pins and generate a 32-bit physical address </li></ul>
  69. 72. <ul><li>Highly pipelined, can perform instruction fetching, decoding, execution, and memory management functions in parallel </li></ul><ul><li>On-chip memory management and protection hardware translates logical addresses to physical addresses </li></ul><ul><li>Supports virtual memory, paging </li></ul>
  70. 73. Control Unit Data Unit Protection Test Unit Segment Register Segment translators TLB Page translator decoder Instruction queue Prefetch queue prefetcher biu Decode unit Prefetch unit Page unit Execution unit Segment unit Internal architecture of 80386
  71. 74. Internal Architecture <ul><li>Includes 6 functional units that operate in parallel </li></ul><ul><li>1 . Bus interface unit: </li></ul><ul><li>Interfaces between the 80386 with memory and I/O. </li></ul><ul><li>Based on internal requests for fetching instructions and transferring data from the code prefetch unit, the 80386 generates the address, data, and control signals for the current bus cycles. </li></ul>
  72. 75. <ul><li>2.Code prefetch unit: </li></ul><ul><li>Prefetches instructions when the BIU is not executing bus cycles. </li></ul><ul><li>It then stores them in a 16-byte instruction queue for execution by the instruction decode unit. </li></ul><ul><li>3.Instruction decode unit: </li></ul><ul><li>Translates instructions from the prefetch unit queue into microcodes. </li></ul><ul><li>The decoded instructions are then stored in an instruction queue (FIFO) for processing by the execution unit. </li></ul>
  73. 76. <ul><li>4. Execution unit: </li></ul><ul><li>Processes the instructions from the instruction queue. </li></ul><ul><li>It contains a control unit, a data unit and a protection test unit. </li></ul><ul><li>Control unit contains microcode and parallel hardware for fast multiply, divide and EA calculation. </li></ul><ul><li>Data unit includes an ALU, 8 general-purpose registers, and a 64-bit barrel shifter for performing multiple bit shifts in one clock. It carries out data operations requested by the control unit </li></ul><ul><li>Protection test unit checks for segmentation violations under the control of the microcode </li></ul>
  74. 77. <ul><li>5 . Segmentation unit: </li></ul><ul><li>Translates logical addresses into linear addresses at the request of the execution unit </li></ul><ul><li>6.Paging unit . </li></ul><ul><li>Translated linear address is sent to the paging unit. </li></ul><ul><li>Upon enabling of the paging mechanism, the 80386 translates these linear addresses into physical addresses. </li></ul>
  75. 78. 80386 registers
  76. 79. <ul><li>General registers: EAX EBX ECX EDX </li></ul><ul><li>Segment registers: CS DS ES FS GS SS </li></ul><ul><li>Index and pointers: ESI EDI EBP EIP ESP </li></ul><ul><li>Indicator: EFLAGS </li></ul>
  77. 80. <ul><li>General registers </li></ul><ul><li>General registers are the mostly used. They all can be broken down into 16 and 8 bit registers. </li></ul><ul><li>32 bits : EAX EBX ECX EDX </li></ul><ul><li>16 bits : AX BX CX DX </li></ul><ul><li>8 bits : AH AL ,BH BL, CH CL, DH DL </li></ul><ul><li>EAX, AX, AH, AL : Accumulator register. It is used for I/O port access, arithmetic, etc. </li></ul><ul><li>EBX, BX, BH, BL : Base register. It is used as a base pointer for memory access. </li></ul><ul><li>ECX, CX, CH, CL : Counter register. It is used as a loop counter and for shifts. </li></ul><ul><li>EDX, DX, DH, DL : Data register. It is used for I/O port access, arithmetic, some interrupt calls. </li></ul>
  78. 81. <ul><li>Segment registers </li></ul><ul><li>Segment registers hold the segment address of various items. </li></ul><ul><li>They are only available in 16 bit values. Some of them are critical for the good execution of the program: </li></ul><ul><li>CS : Holds the Code segment in which your program runs. Changing its value might make the computer hang. </li></ul><ul><li>DS : Holds the Data segment that your program accesses. Changing its value might give erroneous data. </li></ul><ul><li>ES, FS, GS : These are extra segment registers available for far pointer addressing like video memory. </li></ul><ul><li>SS : Holds the Stack segment your program uses. Sometimes has the same value as DS. Changing its value can give unpredictable results, mostly data related. </li></ul>
  79. 82. <ul><li>Indexes and pointers </li></ul><ul><li>Indexes and pointers are the offset part of an address. </li></ul><ul><li>They have various uses but each register has a specific function. </li></ul><ul><li>They are some times used with a segment register to point to a far address (in a 1Mb range). </li></ul><ul><li>ES: EDI DI : Destination index register Used for string, memory array copying and setting and for far pointer addressing with ES </li></ul><ul><li>DS: ESI SI: Source index register Used for string and memory array copying </li></ul><ul><li>SS: EBP BP: Stack Base pointer register Holds the base address of the stack </li></ul><ul><li>SS: ESP SP : Stack pointer register . Holds the top address of the stack </li></ul><ul><li>CS: EIP IP: Index Pointer. Holds the offset of the next instruction .It can only be read </li></ul>
  80. 83. <ul><li>The EFLAGS register The EFLAGS register hold the state of the processor. </li></ul><ul><li>It is modified by many instructions and is used for comparing some parameters, conditional loops and conditional jumps. </li></ul><ul><li>Each bit holds the state of specific parameter of the last instruction. </li></ul>
  81. 84. 80386 Addressing modes <ul><li>80386 provides 11 addressing modes: </li></ul><ul><li>Register Operand Mode : Instructions operate on register operands. These registers can be 8-bit, 16-bit or 32-bit registers </li></ul><ul><li>E.g.: MOV EAX, EBX </li></ul><ul><li>DEC ECX (decrements ECX by 1) </li></ul><ul><li>Immediate Operand Mode : Immediate operand is given in the instruction itself </li></ul><ul><li>E.g.: MOV EDX,5167810FH </li></ul>
  82. 85. <ul><li>In the remaining modes, the operand is located in a memory segment. Memory operand address in these modes is calculated using segment selector and offset values </li></ul><ul><li>Direct Mode : The operand’s effective address is included as part of the instruction as 8, 16, or 32 bit displacement </li></ul><ul><li>E.g.: MOV [12567H], EAX </li></ul><ul><li>Register Indirect Mode : The offset is stored either in any of the general purpose registers or in ESI, EDI, EBX </li></ul><ul><li>E.g.: MOV [EBX], ECX </li></ul>
  83. 86. <ul><li>Based Mode : The contents of a Base register are added to a displacement to obtain the operands effective address </li></ul><ul><li>E.g.: MOV [EDX+16], EBX </li></ul><ul><li>Indexed Mode : The contents of an Index register are added to a displacement to obtain the operand’s effective address </li></ul><ul><li>E.g.: MOV [ESI+4], EBX </li></ul><ul><li>Based Indexed Mode : The operand is stored at a location whose address is calculated by adding the contents of any of the base registers with the contents of index registers </li></ul><ul><li>E.g.: MOV [ESI+EDX], EBX </li></ul>
  84. 87. <ul><li>Based Indexed Mode with Displacement : In this mode the offset of the operand is calculated by adding an 8-bit or 16-bit or 32-bit immediate displacement with the contents of a base register and an index register </li></ul><ul><li>E.g.: MOV [EBX] [EBP+0F247822AH], ECX </li></ul><ul><li>Scaled Indexed Mode : Contents of an Index register are multiplied by a scale factor that may be added to a displacement to obtain the operand’s effective address. Valid scale factors are 1,2,4 and 8 </li></ul><ul><li>E.g.: MOV START[EBX * 8], ECX </li></ul>
  85. 88. <ul><li>Based Scaled Indexed Mode : Contents of an index register are multiplied by a scale factor and then added to Base register </li></ul><ul><li>E.g.: MOV [EBX + 2 * ESI], AX </li></ul><ul><li>Based Scaled Indexed Mode with displacement : contents of index register are multiplied by scale factor and the result is added to base register and displacement </li></ul><ul><li>E.g.: MOV [ESI * 8][EBP + 60H], ECX </li></ul>
  86. 89. Pseudo instructions (Assembler Directives) <ul><li>Pseudo instructions are instructions entered into the source code along with the assembly language. </li></ul><ul><li>They do not get translated into object code but are used as special instructions to the assembler to perform some special functions. </li></ul><ul><li>The assembler will recognize pseudo instructions that assign memory space, assign addresses to labels, format the pages of the source code and so on. </li></ul><ul><li>They are usually placed in the op-code field. If any labels or data are required by the pseudo instruction, they are placed in the label or operand field as necessary. </li></ul>
  87. 90. <ul><li>Some common pseudo instructions are: </li></ul><ul><li>ORG-ORIGIN: This is used, when it is necessary to place the program in a particular location in memory. As the assembler is translating the source code, it keeps an internal counter that keeps track of the address for the machine code. </li></ul><ul><li>Eg: ORG 2000H-tells the assembler to set the location counter to 2000H </li></ul><ul><li>ASSUME : is used to tell the assembler the name of the logical segment it should use for a specified segment. </li></ul><ul><li>Eg: ASSUME CS:CODE –tells the assembler that the instructions for a program are in a logical segment named CODE. </li></ul><ul><li>in instruction MOV AX,[BX], after it reads ASSUME DS: DATA, it will know that the memory location referred to by [BX] is in the logical segment DATA. </li></ul>
  88. 91. <ul><li>3. EQU-EQUATE : The EQU instruction is used to assign the data value or address in the operand field to the label in the label field. </li></ul><ul><li>eg:- TEN EQU 10 </li></ul><ul><li>NINE EQU 9 </li></ul><ul><li> ORG 1000 </li></ul><ul><li> MOVE AL,TEN </li></ul><ul><li> ADD AL,NINE </li></ul><ul><li>4. DB-Define Byte: is used to declare a byte-type variable. </li></ul><ul><li>Eg: Temp DB 42H- tells the assembler to reserve 1 byte of memory for a variable named Temp and to put the value 42H in that memory location when the program is loaded into RAM to be run. </li></ul><ul><li>5. DW-Define Word : FIRSTNO DW 437AH </li></ul><ul><li>STORAGE DW 100 DUP(0)-reserve an array of 100 words of memory and initialize all 100 words with 0000. </li></ul><ul><li> STORAGE DW 100 DUP(?)- reserve an array of 100 words of memory but leave the word uninitialized. </li></ul>
  89. 92. <ul><li>6. END -is put after the last statement of a program to tell the assembler that this is the end of the program module. The assembler will ignore any statement after an END directive. </li></ul>
  90. 93. MASM : The Microsoft Macro Assembler <ul><li>The Microsoft Macro Assembler (abbreviated MASM ) is an assembler for the X86 family of microprocessors. </li></ul><ul><li>It was originally produced by Microsoft for development work on their MS-DOS, and was for some time the most popular assembler available for that operating system. </li></ul><ul><li>It supported a wide variety of macro facilities and structured programming idioms, including high-level constructions for looping, procedure calls and alternation (therefore, MASM is an example of a high-level Assembler). </li></ul>
  91. 94. <ul><li>Later versions added the capability of producing programs for the Windows operating systems that were released to follow on from MS-DOS. </li></ul><ul><li>MASM is one of the few Microsoft development tools for which there was no separate 16-bit and 32-bit versions </li></ul>
  92. 95. MACROS <ul><li>If we need to use a group of instructions several times throughout a program, there are 2 ways which avoid having to write the group of instructions each time we want to use it. </li></ul><ul><ul><li>Use separate procedure </li></ul></ul><ul><ul><li>Use Macro </li></ul></ul>
  93. 96. <ul><li>When the repeated group of instructions is too short or not appropriate to be written as a procedure , we use macro. </li></ul><ul><li>A MACRO is a group of instructions we bracket and give a name to the start of the our program. </li></ul><ul><li>Each time we call the macro in our program, the assembler will insert the defined group of instructions in place of the call. </li></ul><ul><li>Ie, The assembler generates machine codes for the group of instructions each time the macro is called. </li></ul>
  94. 97. <ul><li>Replacing the macro with the instructions it represents is called macro expansion. </li></ul><ul><li>Here the generated codes are right in-line with the rest of the program. </li></ul><ul><li>Therefore, using macro avoids the overhead time involved in calling and returning from a procedure. </li></ul><ul><li>One drawback of macro is each time generating in-line code causes more memory consumption. </li></ul>
  95. 98. <ul><li>Mainly 3 parts: </li></ul><ul><li>MACRO header (MACRO) </li></ul><ul><li>Text or Body </li></ul><ul><li>Pseudoinstructions marking the end of the instruction (e.g.:- ENDM) </li></ul>
  96. 99. <ul><li>e.g.:- Without Macro’s With Macro’s </li></ul><ul><li>MOV EAX, P SWAP MACRO </li></ul><ul><li>MOV EBX, Q MOV EAX, P </li></ul><ul><li>MOV Q, EAX MOV EBX, Q </li></ul><ul><li>MOV P, EBX MOV Q, EAX </li></ul><ul><li> MOV P, EBX </li></ul><ul><li>MOV EAX, P ENDM </li></ul><ul><li>MOV EBX, Q </li></ul><ul><li>MOV Q, EAX SWAP </li></ul><ul><li>MOV P, EBX SWAP </li></ul>
  97. 100. <ul><li>When an assembler encounters a macro definition, it saves it in a Macro definition Table for subsequent use. </li></ul><ul><li>From that point, whenever the name of macro appears on opcode, the assembler replaces it by the macro body. </li></ul><ul><li>The use of a macro name as an opcode is called a macro call and replacement by macro body is called macro expansion </li></ul><ul><li>Macro expansion occurs during the Assembly process and not during execution of the program. </li></ul>
  98. 101. <ul><li>Macro’s with parameters </li></ul><ul><li>Without Macro’s With Macro’s </li></ul><ul><li>MOV EAX, P CHANGE MACRO P1, P2 </li></ul><ul><li>MOV EBX, Q MOV EAX, P1 </li></ul><ul><li>MOV Q, EAX MOV EBX, P2 </li></ul><ul><li>MOV P, EBX MOV P2, EAX </li></ul><ul><li> MOV P1, EBX </li></ul><ul><li>MOV EAX, P ENDM </li></ul><ul><li>MOV EBX, Q </li></ul><ul><li>MOV Q, EAX CHANGE P, Q </li></ul><ul><li>MOV P, EBX CHANGE R, S </li></ul>