1) The document describes 4 digital logic elements to be implemented: a) a gated RS latch structurally, b) a negative edge-triggered JK flip-flop behaviorally, c) a negative edge-triggered D flip-flop with asynchronous reset and synchronous enable behaviorally, and d) a positive edge-triggered D flip-flop structurally using a master-slave configuration of D latches. 2) It then describes a testbench that should instantiate and test the 4 elements in parallel by driving their outputs. The testbench should use two clocks - a slow clock and a fast clock, and an 8-bit counter driven by the fast clock to control the test cases.

1. 1) Write modules for the following state elements
a) Gated RS-latch (Structural)
b) Negative edge-triggered JK Flip-Flop (Behavioral)
c) Negative edge-triggered D-Flip-Flop with asynchronous reset and synchronous enable
(Behavioral)
d) A positive edge-triggered D-Flip-Flop implemented structurally in the Master-Slave pattern
using D-latches (each D-latch, Behaviorally implemented).
2) Write a single testbench that goes through sufficient input patterns to showcase the behavioral
differences of the above using the following paradigms. Assume that the R and K inputs of
elements a. and b. are the same, as are the J and S inputs. Similarly, assume that the D input is
the same for c. and d. Write a testbench that instantiates state elements a. through d. and tests
them in parallel, driving their outputs to its outputs.
Testbench paradigms:
a) Clock generation via
reg clkSlow; reg clkFast;
always
#7 clkSlow = ~clkSlow;
always
#2 clkFast = ~clkFast;
b) Use a behavioral unconditional modulo up-counter with reset to keep track of time:
reg [7:0] count; always@(posedge clkFast) begin
if (reset)
count <= 8’h00;
else
count <= count +8’h01;
end
c) Use clkSlow as the clock for all clocked/gated logic elements from task 1. Use the counter
driven by clkFast and comparators to force events to happen at a specific time in the test case or
directly connect bits of count to inputs.
Solution
1)Gated RS-latch (Structural):
module rslatch(
input clk,S,R,

2. output Q,Q_not
);
wire top1, bot1, Qback, notQback;
nand G1(top1,S, clk );
nand G2(bot1,clk, R );
nand G3(Qback,top1, notQback );
nand G4(notQback,Qback, bot1 );
assign Q = Qback;
assign Q_not = notQback;
endmodule
b)Negative edge-triggered JK Flip-Flop (Behavioral):
module jkff(
input J,K,CLK,
output Q,Q_not
);
reg Q;
reg Q_not;
always @(negedge clk)
if(J == 1 && K == 0)
begin
Q = 1;
Q_not=0;
end
Negative edge-triggered D-Flip-Flop with asynchronous reset and synchronous enable:
else if(J == 0 && K == 1)
begin
Q = 0;
Q_not =1;
end
else if(J == 1 && K == 1)
begin
Q = ~Q;
Q_not = ~Q_not;
end
else
begin

3. Q = Q ;
Q_not = Q_not;
end
endmodule
c)Negative edge-triggered D-Flip-Flop withasynchronousreset and synchronous enable
module d_ff(
input clk,rst,en,d,
output Q,Q_not
);
always@(negedge clk,posedge rst )
begin
if ((!rst_n)&en)
q <= 1'b0;
else
q <= d;
end
endmodule