This document summarizes the design and implementation of a 64-bit ALU on an FPGA. The aims were to design a 64-bit ALU that can perform 14 distinct operations using VHDL, capture the design using software tools, verify it through simulation, and test the synthesized design on an FPGA board. Block diagrams and flow charts illustrate the top-level design, instruction selection, and VHDL source code flow. Test results demonstrate arithmetic, logical, and shift operations working as intended. Recommendations include adding multiplication and division capabilities. The conclusion discusses how FPGAs allow modeling, simulating, and reliably implementing complex digital designs in an efficient way.

1. *DESIGN AND
IMPLEMENTATION OF
FPGA BASED 64-BIT ALU
*BY SAIDU, ABUBAKAR MOHAMMED
*(08/05/04/007)
*supervised by Engr.(Dr.) C U Ngene

2.  In the present day technology, there is an immense need for developing
Suitable communication interfaces for real time embedded systems in a
Lesser time and at an efficient cost such as the ALU and other parts of
the CPU.
 HDL like VHDL and Verilog offers lots of resources that can be
manipulated and Utilized To achieve these goals.
 ALU is one of the most important component of a processor, it is usually
designed first so that the rest of the processor parts will be implemented
to feed operands and control codes to it for arithmetic and logic
operations.
 FPGA allows an IC to be configured by a customer using any of the HDL’s
to describe (model) and verify(simulate) the design before translating
into actual hardware
*background

3. *Aims and objectives
AIM
 The main aim of this project is to design and implement an FPGA Based
64-ALU that performs 14 distinct Operations using VHDL.
OBJECTIVES
 To design an FPGA based 64-bit ALU that performs 14 operations.
 To capture the design using VHDL and Xilinx ISE software.
 To carry out verification of the design using ISIM software.
 To synthesize and implement the design on Xilinx SPARTAN 3E kit.
 To test the design.

4. Top level design block diagram
*Block diagram

5. *Instructions selection
N0 Instruction code
C_in RESULT OPERATION
S3 S2 S1 S0
1 0 0 0 0 0 A + B Addition
2 0 0 0 0 1 A + B + 1 Addition with carry
3 0 0 0 1 0 A + (~B) Subtraction
4 0 0 0 1 1 A + (~B)+ 1 Subtraction with
borrow
5 0 0 1 0 0 A – 1 Decrement
6 0 0 1 0 1 A Transfer
7 0 0 1 1 0 A Transfer
8 0 0 1 1 1 A + 1 Increment
9 0 1 0 0 X A∙B AND
10 0 1 0 1 X A+B OR
11 0 1 1 0 X A⨁B XOR
12 0 1 1 1 X ~A Complement
13 1 0 0 X X LSR A Shift Right
14 1 0 1 X X LSL A Shift Left
instructions table

6. *Flow chart of source code

7. *Test and result
ADD = Arithmetic simulations

8. *Test and results
AND = Logic simulation

9. *Test and results
Left shift = shift simulation

10. *recommendation
In this project, the ALU was designed to perform only the
basic functions, Though that aim was achieved, but there
are still lots of other things that can be improved on Like:
 Mult. and Div.
 Timing and delays for issuing control and operands.
 Implementing the design on a higher version of the
Spartan 3E kit.

11. *conclusion
 In the project, an ALU which is capable of manipulating up to
64-bits of operands to output a result with an exception flag bit
Have been designed and implemented .
 The usefulness of this project is to show how complex and large
capacity digital designs can be simplified by using field programmable
gate arrays to describe (model) and verify (simulate) a required
behavior from a proposed design before translating it into
real hardware, hence resulting into reliability and cost efficiency
for manufacturers of digital devices

12. *Thank you!