3. Background
Introduction
CPU performance factors
Instruction count
? Determined by ISA and Compiler
CPI and Cycle time
? Determined by CPU hardware
Implementations Covered MIPS (Microprocessor without Interlocked
Pipelined Stages) implementations
A simplified version
An improved version by pipelining technique
Instructions covered for MIPS implementation
Memory reference: lw, sw
Arithmetic/logical: add, sub, and, or, slt
Control transfer: beq, j
ECE 374 U. Tida 3 / 38
4. Background
Instruction Execution Procedure
1 PC (program counter) → instruction memory, fetch instruction
2 Register numbers → register file, read
3 Instruction determines ALU to calculate:
Arithmetic/logic result
Memory address for load/store
Branch target address
4 Access data memory for load/store or write to register
5 PC ← target address or PC+4
ECE 374 U. Tida 4 / 38
6. Background
CPU Overview
We cannot join wires together and expect it to select whatever we
need by itself.
Use multiplexer to select between data
ECE 374 U. Tida 6 / 38
8. Background Logic Design
Logic Design Basics
Binary Encoded Information
Two states: Low voltage = 0 and High voltage = 1. (Traditional
method)
One wire per bit
Multi-bit data encoded on multi-wire buses
Combinational Element
Operate on data continuously
Output is a function of input
State (Sequential Element
Store information for a certain period
ECE 374 U. Tida 8 / 38
9. Background Logic Design
Typical Combinational Elements
Given a set of inputs, it always produces the same output
AND-gate
Y = A & B
Adder
Y = A + B
Multiplexer
Y = S ? I1 : I0
Arithmetic Logical Unit (ALU)
Y = F(A , B)
ECE 374 U. Tida 9 / 38
10. Background Logic Design
Sequential Element
Register: Stores data in a circuit
Clock signal determines when to update the stored value
Edge-triggered flip flop: update data when clk changes 0 to 1 =⇒
positive triggered (1 to 0 =⇒ negative triggered)
ECE 374 U. Tida 10 / 38
11. Background Logic Design
Sequential Element with write control
Register with write control
Only updates on clock edge when write control input is 1
ECE 374 U. Tida 11 / 38
12. Background Logic Design
Maximum clock speed
Combinational logic transforms data between clock edges
Longest delay for data to travel [input state element → combinational
logic → output state element] determines clock period
ECE 374 U. Tida 12 / 38
13. Datapath Design
Datapath Design Approach
Datapath design
Design of elements that process data and addresses (of data memory
and instruction memory) in the CPU
Consists of Registers, ALU, Mux’s, memories, ...
Approach
Let’s start with one set of instructions and include rest systematically
by refining the overall design of previous step.
Instruction-set Design Sequence we follow
1 R-format instructions
2 I-format instructions
3 J-format instructions
ECE 374 U. Tida 13 / 38
14. Datapath Design
Step 1: Instruction Fetch
Program Counter (PC) Register
Holds address of the current instruction
Increment by 4 after each fetch!
Common step for all instruction type execution
ECE 374 U. Tida 14 / 38
15. Datapath Design R-format
Datapath design for R-type instructions
Register format (R-format)
Instruction Fields:
op: operation code or opcode of an instruction.
rs: first source register number (READ)
rt: second source register number (READ)
rd: destination register number (WRITE)
shamt: shift amount
funct: function code
ECE 374 U. Tida 15 / 38
16. Datapath Design R-format
Step 2: Read registers
R-format instruction has two register addresses of a register file and
this information is used to read the two registers simulataneously!
ECE 374 U. Tida 16 / 38
17. Datapath Design R-format
Step 3: Perform operation
The register read in Step 2 will be given to the ALU to perform the
required opeartion!
ECE 374 U. Tida 17 / 38
18. Datapath Design R-format
Step 4: Write back result
ALU result will be stored in the destination register
RegWrite is a control signal that will be high almost at the end of
clock cycle!
ECE 374 U. Tida 18 / 38
19. Datapath Design I-format
Datapath design extension to include I-format instructions
Immediate format (I-format)
Instruction Fields:
op: operation code or opcode of an instruction. Determined by the
hardware control
rs: first source register number (READ)
rt: destination register number (READ (SW)/WRITE (LW))
constant: 16 bit size
address: 16 bit offset added to base address in rs
Different formats complicate decoding but allow 32-bit instructions
uniformly.
ECE 374 U. Tida 19 / 38
20. Datapath Design I-format
Step 2: Read registers
Two reads occur for sw instruction and only one read occurs for lw
instruction
ECE 374 U. Tida 20 / 38
21. Datapath Design I-format
Step 3: Address calculation
The register read in Step 2 will be given to the ALU to perform the
required opeartion!
ECE 374 U. Tida 21 / 38
28. Control circuitry
ALU operation
Utilize it for
1 Addition in Load/Store instructions for memory address calculation
2 Subtraction in branch if equal (beq) instruction
3 Operation depending on funct field for R-type instructions!
ALU operation (4-bit) Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR
ECE 374 U. Tida 28 / 38
29. Control circuitry
ALU control
ALU operation (4-bits) are set depending on opcode and funct bits
Since there are only 4 different opcodes possible i.e., lw, sw, beq and
R-type, we can assume 2 ALUOp bits derived from opcode
We will design a combination logic circuits based on truth table to
obtain ALU operation bits
inst ALUOp Operation funct ALU function ALU operation
lw 00 load word XXXXXX add 0010
sw 00 load word XXXXXX add 0010
beq 01 branch if equal XXXXXX subtract 0110
R-type 10
add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set on less than 101010 set on less than 0111
ECE 374 U. Tida 29 / 38
30. Control circuitry
Main control circuit from instruction register
Control signals are derived from instruction register!
ECE 374 U. Tida 30 / 38
32. Datapath and control: Processor
Datapath and control of R-type instruction
ECE 374 U. Tida 32 / 38
33. Datapath and control: Processor
Datapath and control of load instruction
ECE 374 U. Tida 33 / 38
34. Datapath and control: Processor
Datapath and control of branch-on-equal instruction
ECE 374 U. Tida 34 / 38
35. Datapath and control: Processor
How about Unconditional Jump (j)?
Jump uses word address
Update PC with concatenation of
? Top 4-bit of old PC
? 26-bit jump address
? 00 (multiply by 4)
Need an extra control signal decoded from opcode
ECE 374 U. Tida 35 / 38
36. Datapath and control: Processor
Datapath and control with Jumps added
ECE 374 U. Tida 36 / 38
37. Datapath and control: Processor
Performance metric and issues
Longest delay determines clock period
Critical path: load instruction
? Instruction memory → Register file → ALU → Data memory →
Register file
What happens if the frequency of load instruction is low?
We can improve performance by pipelining (will be covered in next
lecture series!)
Sincere suggestion: Revise the lecture slides, clear doubts, practice many
problems, prepare to become a computer engineer!
ECE 374 U. Tida 37 / 38
38. What have we learnt today?
1 Background
Logic Design
2 Datapath Design
R-format
I-format
3 Control circuitry
4 Datapath and control: Processor
ECE 374 U. Tida 38 / 38
