CA unit IV 26 8-2020

13-11-2020 1Dr. K.K. THYAGHARAJAN, RMD ENGINEERING COLLEGE
Contact E-mail:
acdean@rmd.ac.in
kkthyagharajan@yahoo.com
kkthyagharajan@gmail.com
Dr. K.K. THYAGHARAJAN
Professor & Dean (Academic)
Department of Electronics and Communication Engineering
RMD ENGINEERING COLLEGE
Please visit the blog https://thyagharajan.blogspot.com/
to download the presentation.
You can also view the video in YouTube
Memory Organization
Click on the links given below to view videos
https://youtu.be/GuC7sZEw-uM
https://youtu.be/LroA8T-_vqs
https://youtu.be/CU1wx8EZmvc
https://youtu.be/zYADaZ5sfY0

Contact E-mail: acdean@rmd.ac.in kkthyagharajan@yahoo.com kkthyagharajan@gmail.com
Memory Organization
MEMORY HIERARCHY
This part of the video explains about the memories used at different levels of the Computer Systems and discuses the terms used in memory
access

Memory Organization
 Memory hierarchy is a structure which indicates how the memories are used at different levels (their
locations in the computer system) based on speed and size.
 SRAM – Static RAM – content stored (data) will be lost if power goes off
 DRAM - Dynamic RAM - should be refreshed periodically otherwise content will be lost.
 Level 0 – highest level ; Level 4 – lowest level
Memory Hierarchy
Secondary Memory Optical Disk & Magnetic Tape
Registers
& primary Cache
(CPU) – SRAM - Level 0
Secondary Cache - SRAM - Level 1
Main Memory - DRAM - Level 2
Secondary Memory - Magnetic Disk - Level 3
Secondary Memory - Optical Disk & Magnetic Tape - Level 4
Cost
High
Speed
High
Small Size
Large
Size

Memory Organization
 SRAMs are faster than DRAMs
 Faster memories are smaller and more expensive - e.g. Cache
 RAM (Random Access Memory ) is used as main memory
 Secondary memory is used to store large volume of data or programs
Memory Hierarchy
 Only one word (32 bits or 4 bytes) will be transferred between CPU and Cache at a time
 Only small blocks of data can be transferred between Cache and Main memory
 Larger blocks of data will be transferred between Main memory and Secondary
memories
 Data can be transferred only to the immediate lower level or immediate upper level

Memory Organization
Hit: If the data requested by the processor is available at the upper level of memory
(cache) then it is called hit
Miss: If the data requested by the processor is not available at the upper level of
memory then it is called miss
Data Transfer – Terms used
Hit Rate or Hit Ratio: It is the fraction of the memory access found in the upper level of memory
Miss Rate: It is the fraction of the memory access not found in the upper level of memory.
Miss Rate = 1- Hit Rate
Hit Time: It is the time taken to access the upper level of memory + the time needed to decide
whether the access is hit or miss
Miss Penalty: It is the time required to bring a data block from the lower level to the
corresponding block in the upper level + the time taken to deliver this block to the processor

Memory Technologies
SRAM Technology, DRAM technology, Flash memory technology and Disk memory technology
o SRAM (Static Random Access Memory) : It is an integrated circuit .
o The data stored in this memory will be lost if power goes off.
o Same data lines (single access port) will be used for reading and writing.
o Access time (read / write time) for reading and writing will be different.
o It uses 6 to 8 transistors per bit
o Its accessing speed is higher than that of DRAM.
 DRAM (Dynamic Random Access Memory) : It stores the data as a charge on the capacitor.
 So it requires only a single MOSFET and a small capacitor and hence smaller in size.
 Since the capacitor may not hold charge(data) for longer time , the memory cell (data bit) should be refreshed periodically.
 The memory is arranged as memory banks and each bank has many rows and columns .
 DDR – Double data rate RAMs – These memories are transferring data on both rising edge and falling edge of the clock.

Memory Technologies
SRAM Technology, DRAM technology, Flash memory technology and Disk memory technology
o Flash Memory: It is a EEPROM (Electrically Erasable Programmable Read Only Memory).
o It uses different low voltage for reading and slightly higher voltages for writing operations.
o So normally if programs are stored then they are only read.
o If the memory is to be written again all the blocks should be erased and again it should be written using higher voltage.
 Disk Memory: Its surface is divided into concentric circles called tracks and each track is divided into sectors.
 There will be 512 sectors per track and each sector can store 4KB data.
 The drive has a spindle which rotates at 5400 to 15000 rpm. It also has a movable arm and a read/write head.
 The time taken to move the head to the particular track is called seek time
 The time taken to move the head to the particular sector in the track is called rotational delay or rotational latency
 The time taken to transfer a block of data is called transfer time

CACHE MEMORY ORGANIZATION
This video explains about
cache memory, its
Organization and its Uses

 Main memory is divided in to many blocks. Each block has fixed number of consecutive
locations
 When the CPU wants to read a specific location (word) in that block, first it checks the
cache for availability of that word. If it is not available , the complete block will be transferred
from the main memory to the cache. Only , block transfer will be done between cache and
main memory
 CPU reads only from that cache. Reading from cache is faster.
CACHE MEMORY
Single Cache Three Level Cache Organization

Cache principle of locality: cache pre-fetches a small block of the data (or program) from main memory instead
of a single word
Principle of Temporal locality: The current instruction may be needed again soon (e.g. instruction in a loop)
Principle of Spatial locality : The adjacent instruction (or data) to the current instruction may be needed soon, so
it will be put in the cache. Almost all programs exhibit this locality because instructions are executed in sequence.
Principle of temporal locality – Example
Loop: lw $s1, 0($s2) #load word from memory
addi $s2,$s2, 04 # get the address of the next word
bne $s1, $0, Loop #add until the last word (i.e. 0 )
Principal of Spatial locality - Example
lw $s1, 0($s2) #load word from memory
addi $s2,$s2, 04 # get the address of the next word
X1
X3
X2
X1
X3
X4
X2
Fig.1. Cache before X4 Fig.2.
Fig. 1. shows the position of the cache when CPU requests data X4.
No reference address is available for X4 and hence it is a miss.
Now the data X4 is brought from the main memory and put into
cache.

kkt
Cache Main
Memory
o Cache contains ‘C’ lines.
o Each line contains a block of ‘K’ words. (1 word = 4 bytes)
o Each block is identified by its line number (index) and a tag
Block 0
Block 1
Block C-1
1. Cache contains two parts cache tag memory (tag) &
cache data memory (blocks)
2. Tag contains portion of the address of the block available
in the main memory.
3. The block contains the required word.
Tag Index
22 bits 10 bits
If there are 32 bits for addressing the main memory, then the address structure for cache
is as given below.
Index is used to point specific block in the cache
Tag is used to point a specific page (size is equal to the size of cache) in the main memory
No two blocks in the same line have same tag field.

 Assume that the Cache has 8 blocks. So it requires 3 bits to address all blocks (23 =8).
 Assume that the main memory has 32 blocks. This requires 5 bits to address all the 32 blocks (25 =32)
 So the main memory has 4 pages (page size is equal to the total size of the cache) and to address these pages 2 bits are used
 A valid bit (v) can be added to cache block. If this bit is 1 then cache contains a valid data and it is a hit otherwise if this
is 0, the cache does not contain a valid data it is a miss.
 Cache gives the address in the form Tag : index
Fig. 1. Initial state of the
cache after power on
10
Fig. 2. Processor requests a word
from cache whose address is 10110
It is not available in cache in fig.1.
1011010
Y
Fig. 3 After handling a miss address
11010 It is not available in cache
in fig.1 &2.
11010
Memory block

Consider the example given above. Let us see how
all the blocks in the main memory occupy /
replace the block spaces in the cache.
The table shows the actions for each memory
request.
Cache uses the address in the form
Tag : index
Since there are 8 blocks, the lower order three bits
in the address gives the block number (index)
Tag : Index
Observation: Since there are only eight blocks, any address with difference 8 will share the same block. For example
blocks 26 & 18 (difference 26-18=8) share the same block (010). So when reference 18 (8th entry in table) is to be stored
in the cache, reference 26 (2nd entry) should be removed and then 18 is stored in that place.
Recently referenced word (18) replaces less recently referenced word (26) – Temporal locality

Cache increases the speed of accessing data at the cost of extra memory. Let us calculate the number of bits used by cache.
If ‘n’ is the number of bits used to address the total number of blocks in the cache (i.e. number of bits used for index)
Total number of blocks in the cache = 2n
Valid field size = bit used for valid or not valid state = 1
If m = number of bits used to address the number of words in a block
Number of bits used in a block = number of words in a block x 32 = 2m x 32
Since 32 –bit words are used in the cache , it has 4 bytes per word, these can be accessed using 2 bits (22 = 4)
Tag field size = 32 – (n+m+2)
32 is the number of bits used for addressing the main memory
Total number of bits needed for a cache = 2n x (block size + tag size + valid field size)
Total cache size = N = 2n x { 2m + [32- (n+m+2)] +1}
Example: How many bits are required for a direct mapped cache with 16 KB of data & 4-word blocks assuming 32 bit address
Solution: Total number of bits needed for a cache = 2n x (block size + tag size + valid field size)
Total number of blocks in the cache = 2n = Total cache size in words / block size in words
= (16 KB /4)/4 = 16 K words /16 = 1 K blocks = 210 ; So n=10 (Note: Cache size is given in bytes)
Block size = 4 words = 2m words = 22 words. So, m=2
Tag size = 32- (n+m+2) = 32-(10+2+2) = 18
Valid field size = 1 bit
Total number of bits needed for a cache = 210 x [(4x32) +18 +1] = 210 x [128 + 19] = 210 x 147 bits = 147 Kilo bits

MAPPING TECHNIQUES FOR CACHE MEMORY
This part of the video explains that how main memories are mapped
with cache memories

MAPPING TECHNIQUES FOR CACHE MEMORY
 Mapping technique specifies the correspondence between main memory blocks and
cache memory blocks
 The number of cache memory blocks are less than the number of main memory
blocks. So, we need mapping techniques.
Mapping
Techniques
Associative
Mapping
Set-
Associative
Fully
Associative
Direct
Mapping
Classification of Cache Memory Mapping Techniques

MAPPING TECHNIQUES FOR CACHE MEMORY – 1. DIRECT MAPPING
 In this method, each main memory block can be mapped to only one slot in the cache.
 But each slot in the cache may receive more than one block from the main memory. In
this case, the block received earlier will be replaced by the block received recently.
 If I is the cache block (line) number and J is the block address in the main memory
(these addresses start from 0 not from 1) then
I = J modulo (number of blocks in the cache)
Disadvantage of Direct Mapping: If the blocks are to be loaded from two different pages frequently , the main memory is to be
accessed again and again and the purpose of using cache will not be achieved.
This not a flexible method
Advantage of Direct Mapping: Cost is less, because the blocks can be mapped directly from the bits of the address

Example 1: A cache has 8 blocks. The main memory has 32 blocks. How will the main memory be mapped with the
cache?
Number of blocks in the cache = 8 = 23 So, number of bits used to address these blocks is 3
The first block in the main memory will be mapped with the block 000 in the cache, the second block is mapped
with block 001 in the cache and so on. The eighth block will be mapped with block 111 in the cache.
When 9th block is to be brought (block no=8, because address value starts at 0), since the cache has only 8 blocks,
this 9th block will replace the 000th block (slot) in the cache and in that place 9th block will be stored.
Here J=8 ; number of blocks in the cache =8
The cache block number I = J modulo (number of blocks in the cache) = 8 modulo 8 = 0 i.e. the first block. You
observe that the address of the first block in the cache is 000.

For any block address in the main memory, the corresponding
block address in the cache is modulo of number of blocks in the
cache.
For block 1 (block number starts at 0) in the main memory
(address is 00001, address always starts at 0), the block
assigned in cache is 1 (address is 1 i.e. 001) i.e. 1 modulo 8 = 1.
For block 9 in the main memory (address is 01001 = 9), the
block assigned in the cache is 1 (address is 001) i.e. 10 modulo
8 =2.
If you observe for both blocks in the main memory same single
block is assigned in the cache.
You can also observe that the lower three bits in the main
memory becomes the address in the cache
000
001
010
011
100
101
110
111
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

Example 2: The block I of the main memory
maps on to block J (J Modulo 128) of the cache.
Thus the main memory blocks 0, 128, 256 … are
to be loaded in the cache block 0. Blocks 1, 129,
257 … are to be loaded in block I and so on. There
are 4K blocks in the main memory. Assume that
each block stores 4 words i.e. 16 bytes.
Main Memory
Solution :
Each block stores 4 words = 4 X (4 bytes per word ) =
16 bytes = 24
→ we need 4 bits to access all bytes in the block
No. of blocks in the cache = 128 (modulo 128) = 27
→ 7 bits are required to address 127 blocks in the
cache
Number of blocks in the main memory = 4K = 22 x 210
= 212
→ 12 bits are required to address all block in the
main memory.
Number of bits to be used for tag field = 12-7 = 5 bits
Since the tag field is using 5 bits , 25 = 32 blocks of
the main memory share the same cache block. Tag
bits decide which one of the 32 blocks should be
loaded in the cache.
Tag Block word
Bits used in main
memory address
5 7 4
Cache
⁞≈ ≈
⁞≈ ≈
⁞≈ ≈
⁞≈ ≈
Page

Example 3: A cache has 128 blocks of 16 words each. The main memory has 64K words.
NB: 1 K = 1 Kilo = 1024 = 210
Solution:
Each word has 4 bytes (22) , so 16 words require 16 X 22 = 24 X 22 = 26 bytes
So, we need 6-bit address to access all bytes in a block
The size of the cache = 128 blocks = 27 → 7 bits are required to address any block in the cache
Number of blocks in the main memory = Size of the main memory (in words)/ size of the block (in words)
= 64K/16 = 4K= 212 blocks
So, main memory requires 12 address lines to point any block with in it.
Number of bits used for tag field = 12-7 = 5 bits
Tag Block word
Bits used in main memory
address
5 7 6

MAPPING TECHNIQUES FOR CACHE MEMORY – 2. ASSOCIATIVE MAPPING
Advantages: The main memory block can
be placed into any cache block.
Compared to direct mapping, blocks in the
cache are less frequently replaced. So time
spent on replacing the blocks is minimized
The memory address has only Tags & words
Disadvantage: Cost is high,
because, all tags in cache are to be
searched to determine whether a
block is in the cache. This is
associative searching
Main Memory
Example : A cache has 128 blocks of 4 words each.
The main memory has 4K blocks. How many bits are
required for tag field if associative mapping is used?
Solution:
Since each block has 4 (22 ) words and each word has 4
(22 ) bytes, we have 22 X 22 = 24 byes in a block. So 4 bits
are required to access each block.
Number of blocks in the main memory = 4K blocks
= 22 X 210 = 212 blocks
So, we need 12 bits to address each block in the main
memory.
In associative mapping all these 12 bits are used as tag
field. See the address mapping given in the bottom left
corner.
Tag word
Bits used in main memory address 12 4
Cache
⁞≈ ≈
⁞≈ ≈
⁞≈ ≈
⁞≈ ≈
Tag
Tag
Tag

MAPPING TECHNIQUES FOR CACHE MEMORY –3. SET ASSOCIATIVE MAPPING
Advantages: It is a combination of direct & associative
mapping techniques
Multiple choices are available for mapping memory block
Searching is to be done only in specific set , so hardware cost is
reduced
Contention problem of direct mapping is eased.
Disadvantage: Implementation cost
is more than direct mapping but
cheaper than fully associative mapping
Main Memory
o Cache blocks are grouped into sets and a block in the
main memory is mapped to any block in the specific set.
o I= J modulo (Number of sets in the cache)
o Where I is cache block number and
J is block address in main memory
o Example: Cache has 128 blocks, and 2 blocks per set
o So cache has 128/2 = 64 sets = 26 sets (numbered as
0 -63) and hence 6 bits are used to address the sets
.
o The main memory block 0, 64, 128 will occupy oth
set in the cache (i.e. 64 modulo 64 = 0)
o The main memory block 1, 65, 129 will occupy set 1
in the cache (i.e. 64 modulo 64 = 0)
o The tag bits of address must be associatively
compared to the tags of two blocks of the set to
check if desired block is present. – Two way
associative search
Tag Set word
Bits used in main memory address 6 6 4
Tag
Tag
Tag
Tag
Tag
Tag
Set 0
Set 1
Set 63
≈ ≈
≈ ≈
≈ ≈
≈ ≈

VIRTUAL MEMORY ORGANIZATION
Professor, ECE Department, RMD Engineering College
This part of the video explains how secondary memories are
mapped with main memories

 Virtual memory is a memory management technique in which the secondary memories (hard disk) can be
addressed as though it were part of the main memory.
 This technique uses main memory as cache for the secondary storage
Need for virtual memory:
Users can run applications larger than main memory
Multiple programs can share the main memory efficiently and safely
The programs available in secondary memory can be loaded anywhere in the main memory - Relocation
Working method: If a program is larger than the size of the main memory (physical memory or RAM) ,
then it is divided into pages. All these pages are stored in the secondary memory and the page which is to
be currently executed will be transferred to the main memory. Then next page will be transferred to the
main memory and execution continues.

 The address issued to access the secondary memory (e.g. hard disk) is called virtual or logical address. All
these addresses form the virtual address space.
 The addresses used to access the main memory is called the physical address and they form the physical
address space
 The logical address space is very large (1 TB hard disk in computers) compared to the physical address space.
(we have only 8GB or 16GB RAM)
 The larger virtual address is translated to physical memories’ smaller address. This is called address mapping
or address translation.
Since large number of programs are stored in the secondary memory (hard disk), all those programs have
to share the same main memory , CPU and I/O devices. So, these programs should not interfere by
reading from or writing into the areas of another program. This requires some protection mechanism.

• The address of the secondary storage (Virtual address) is broken
into virtual pages. Each page has a page number (bits 12-31= 20
bits) and offset (bits 0-11). Offset is the starting address of the
page.
• The address of the main memory (physical address) is also broken
into pages. This page size is same as that of the logical memory’s
page size. Each page has a page number (bits 12-29 = 18 bits) and
offset (bits 0-11).
• Page size in both main and secondary memories use 12 bits = 212
= 22 x 210 = 4KBytes. This size is common to both physical and
logical memories.
• Number of pages in the logical memory (20 bits) = 220
• Number of pages in the physical memory (18 bits) = 218

Virtual Page Number Page Offset
01131
Physical Page Number Page Offset
01129
Valid
bit
Page table
Virtual Address
Physical Address
12 bits
20 bits
18 bits
Page Table translates the 20 bit virtual
address to 18 bit physical address
Each program has its own page table and
the staring address of that table is given
by the page table register.
Page table is indexed with 20-bit page
number of the virtual address and
provides the corresponding 18-bit
physical page number
If valid bit is 0, page is not available or
page fault occurs
Page Table Register

• When all pages in the main memory are in use and if a new page
is to be loaded from the secondary memory then Least Recently
Used (LRU) page is replaced by the new one - This is called LRU
replacement scheme
• If valid bit is zero then page fault occurs. In such a case, the
operating system gets control, and it finds the page in the next
level of hierarchy (usually in disk) and decides where to place the
requested page in the main memory.
• Each time when the page is to be loaded from the secondary
memory into the main memory, the page table has to be
searched to know which page in the main memory is to be used.
This consumes more time. To speed up this process, Translation-
Lookaside Buffer (TLB) is used

Translation-Lookaside Buffer (TLB)
TLB is a cache that holds the address mappings used recently by the page table . So if the same page
is requested again page table need not be searched to get the translated address, it may be obtained
from this cache itself and this method is faster compared to getting address from the page table
The ‘tag’ entry in the TLB holds the virtual page number and the
data entry holds the corresponding physical page number.
TLB also includes a valid bit, a dirty bit and a reference bit.
On every reference or request , we lookup the virtual page number
in TLB,
If it is available it is ‘hit’ and that physical page number is used to
form the address and the corresponding reference bit is turned ON
If it is not available in the TLB then it is a ‘miss’ and the processor
loads that translation from the page table into TLB and then trying
to reference again. During this write (load) operation, the dirty bit
will be set to 1.
If the page is not present in the secondary memory, then TLB miss is
a true page fault and the processor invokes the operating system
using an exception.
Virtual Page No

BUS ARCHITECTURES and BUS ARBITRATION
This part of the video explains Internal Bus Architectures, the signals
used with Buses and Bus Arbitration

BUS ARCHITECTURES
Bus is a group of wires through which address/data/ control signals are transmitted.
If a group of wires transmit 32 bit address, then it is called 32-bit address bus.
All devices share the same address bus. Similarly they share a common data bus.
A control bus transmits all control signals (RD , WR, MEM etc.) to control the devices
Based on type of communication there are two types of Buses
1. synchronous bus: Each operation is synchronized with bus clock. Only devices which are faster than bus speed can be used
2. Asynchronous bus: The operations use handshake signals. Both faster and slower devices may be used
Simplified Illustration of a Bus

BUS ARCHITECTURES
 Valid address is put on the address
bus during the clock cycles T1, T2 and
T3
 Memory request (MREQ) and Read
(RD) signals are asserted low to initiate
memory read operation)
 The memory puts the data in the
data bus in the middle of T3 clock cycle
 MREQ and RD control signals are
asserted high to complete the read
operation
Synchronous Bus (Memory Read Operation):
Timing diagram for synchronous memory read
trtrrttrtrtrttTrailing Edge

BUS ARCHITECTURES
 For a memory read operation, a master
(CPU) puts address on the address bus and
asserts control signals (memory request
MREQ , read RD).
 After these lines settle, the CPU asserts
master synchronization (MSYN).
 This MSYN event triggers the memory
(slave) and make the memory to place data
on the data bus.
 The memory then asserts slave
synchronization (SSYN) signal when the
read operation is finished.
 The master de-asserts MSYN, which
signals the slave to de-assert SSYN.
 This method is full handshake methods
and no bus clock signal present
 Cause-and –effect line
Asynchronous Bus (Memory Read Operation):
Timing diagram for asynchronous memory read

BUS ARBITRATION
This part of the video explains the Bus Arbitration

Bus Arbitration
(a) Simple centralized bus arbitration
(b) centralized arbitration with priority levels
When many devices want to put address (data) on the same address (data) bus i.e. if more than
one devices want to be a master then bus arbitration problem arises
Devices 0 to n are sharing the same bus request line which is connected to an arbiter. When a device wants to be a
master it asserts the bus request line and the arbiter issue a bus grant. This bus grant line is daisy chained. The first
device receives the grant signal first, if it wants to be master it will not propagate the grant to the second device.
Otherwise it will pass the grant signal to the next device. Only the device which accepts the grant signal will use the
bus and the device which is closer to arbiter will get highest priority to use the buses
In this method more than one bus requests may be made by the devices. The devices which are connected to the
lower level number will get the higher priority than the devices connected to higher level numbers. So a device
which is far from the arbiter may also get grant signal first if it is connected to highest priority request line

(c) fully centralized bus arbitration
(d) decentralized bus arbitration
Each device has a separate bus request line and a grant receiving line. So, the priority can be
independently assigned by the arbiter. The above three methods use a centralized arbiter and hence
they are called as centralized bus arbitrations.
There is no central arbiter in this case. A device which wants to be bus master first asserts the bus request line and
then sends 0 (bus not granted) to the next higher numbered device on the daisy chain. Then it asserts the busy line
and de-asserts the bus request line. When the busy line is asserted no other device may issue bus request.
Centralized schemes (a,b,c) will work well for small number of devices. When more number of devices are to be used
decentralized method will be faster.

Internal Communication Methodologies
This part of the video explains the Communication
Methods used by I/O Devices

Programmed I/O Flowchart for Disk Data Transfer
Internal Communication Methodologies
Keyboard – slow input device
Memory – fast device
Three methods to communicate with I/O devices
1. Programmed I/O (Polling)
2. Interrupt-driven I/O
3. Direct memory access (DMA)
 In the flowchart – Enter indicates that the CPU enters into data transfer
operation. Continue indicates that the CPU continues with its other work
 In programmed I/O CPU checks the status of the disk (polling) to know
whether the disk is ready to transfer data. Polling wastes CPU time.
 Data is read by CPU first, then the CPU writes on the target device such as
main memory.

Interrupt Driven I/O Flowchart for Disk Data Transfer
In interrupt driven I/O the CPU will be doing its normal work.
When the disk is to be read / written, the CPU issues read or
write request to the disk and continues it work.
If the disk wants to transfer data, it asserts the interrupt line
of the CPU. The CPU invokes the interrupt service routine (ISR)
which reads from or write into the disk.
Reading or writing on the main memory happens only through
CPU.
When many devices and many interrupts are used priority can
be set either by the processor or by an interrupt controller
device.

Interrupt Driven I/O Flowchart for Disk Data Transfer
CPU
I/O
Device
Interrupt
request
Interrupt
Acknowledge
RET
Main
Program ISR
Interrupt

DMA Transfer from Disk to Memory Bypassing the CPU
 Used to transfer a block of data between main memory and disk bypassing the CPU.
 In the above diagram dashed (-) lines indicate the data transfer without DMA i.e. the
CPU reads the disk first then it writes the read data on the memory.
 In the above diagram direct connection between memory and disk is established for
DMA data transfer (thick line). So CPU bus lines are freed.
 DMA services are provided by a DMA controller, which itself is a specialized
processor. DMA controller takes the job of CPU i.e. it provides necessary addresses
and control signals to both memory and disk.
 Here address means the starting address of the block in the disk, starting address in
the main memory and the length of the block to be transferred
 The flow chart shows that when the data transfer is taking place, the CPU continues
execution of other processes. When DMA completes the DMA controller informs the
CPU through an interrupt.
 In cycle-stealing mode of the DMA controller, few bytes in the block will be
transferred, then the buses will be relinquished to the CPU, again few bytes will be
transferred and this continues until the complete block of the data is transferred

SERIAL BUS ARCHITECTURES
This part of the video explains Serial Bus Architectures used by I/O
Devices for Communication Between them

RS-232 Serial Bus
 The RS-232 standard commonly uses 9-pin and 25-pin
connectors, but uses others as well (see the figure).
 Pin 7 of 25-pin connector is GND, pin 2 sends data and pin 3 for
receiving data
 RS-232 is used for slow-bit-rate devices such as mice, keyboards,
and non-graphics terminals.
 Serial bus transfer is slow compared to parallel bus transfer
because in serial bus transfer, only one bit is transferred in each
clock cycle.
 But in parallel bus, 8 or 16 or 32 bits are simultaneously
transferred using parallel wires (parallel bus)
 Serial cable is using less number of wires compared to parallel
bus.

USB and Firewire
 Universal Serial Bus (USB) and IEEE 1394 (Firewire) are groups of standards
for interconnecting peripheral devices. USB 2.0 supports data transfer rates
up to 480 Mbps, with as many as 127 devices connected to a single host
controller through special hub devices in a tree-like manner.
 Firewire is similar to USB but has traditionally been faster, up to 800 Mbps. A
key advantage of Firewire is isochronous data transfer, in which a
continuous, guaranteed data transfer is supported at a predetermined rate.
This makes Firewire attractive for digital video and digital audio.
(left) USB hub; (middle) USB cable; (right) Firewire cable.

Secondary Storage Devices
This part of the video discusses some of the commonly
used Storage Devices

A Magnetic Disk with Three Platters

Organization of a Disk Platter with a 1:2 Interleave Factor

Master Control Block

Spiral Format for Compact Disk
• Unlike a magnetic disk in which all of the sectors on concentric tracks are lined up
like a sliced pie (where the disk rotation uses constant angular velocity), a CD is
arranged in a spiral format (using constant linear velocity). The speed of rotation is
adjusted so that the disk moves more slowly when the head is at the edge than
when it is at the center.

Magnetic Tape
A portion of a magnetic tape.

Digital Audio Tape (DAT)
• Digital audio tape (DAT) formatting supports high densities, on the order of 72 GB
for a small 73 mm × 54 mm profile. The read / write head is placed at an angle to
the tape as shown in the figure, allowing data to be criss-crossed over the same
area, using opposite polarities which maintains separation of the bits.

Redundant Arrays of Inexpensive Disks (RAID)
RAID level 0 – striped disk array without fault tolerance.
RAID level 1 – mirroring and duplexing.

RAID (Continued)
RAID level 2 – bit-level striping with Hamming Code ECC.
RAID level 3 – parallel transfer with parity.

RAID (Continued)
RAID level 4 – independent data disks with shared parity disk.
RAID level 5 – independent data disks with distributed parity blocks.

RAID (Continued)
RAID level 6 – independent data disks with two independent distributed parity schemes.
RAID level 7 – asynchronous cached striping with dedicated parity.

RAID (Continued)
RAID level 10 – very high reliability combined with high performance.
RAID level 53 – high I/O rates and data transfer performance.

Input / Output Devices
This part of the video discusses some of the commonly
used I/O Devices

Mouse and Trackball
A mechanical mouse (left), a three-button trackball (center), and an
optical mouse (right).

Joystick
•A joystick with a selection button and a rotatable rod:

ECMA-23 Keyboard Layout
• Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys are
frequently placed in the B row.

The Dvorak Keyboard Layout

Tablet with Puck

Touch Sensitive Pen-based Display
Pen-based personal digital assistants (PDAs) use a passive matrix in
which the pen can be anything that induces pressure on the screen.
Two transparent conducting layers are
placed on the screen, separated by
spacer dots. When the user applies
pressure to the top layer, as with a
stylus or simply a finger, the top and
bottom layers make contact. The
induced voltage at the edges varies
according to the position of the
stylus.

Laser Printer
• Schematic of a laser printer (adapted from [Tanenbaum, 1999]).

Cathode Ray Tube
• A CRT with a single electron gun:

Display Controller
• Display controller
for a 1024768
color monitor

Active Matrix Color Liquid Crystal Display

CA unit IV 26 8-2020

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