Chapter 6: Expansion Buses


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Chapter 6: Expansion Buses

  1. 1. Chapter 6 Expansion Buses
  2. 2. What is a bus? <ul><li>connects the parts of the CPU to each other. </li></ul><ul><li>link the CPU to various other components on the system board. </li></ul><ul><li>a pathway for bits representing data and instructions. </li></ul><ul><li>The number of bits that can travel simultaneously down a bus is known as the bus width. </li></ul>
  3. 3. Categories of buses <ul><li>System Buses </li></ul><ul><ul><li>connects the CPU to memory on the system board. </li></ul></ul><ul><li>Expansion Buses </li></ul><ul><ul><li>connects the CPU to slots on the system board. </li></ul></ul>
  4. 5. Processor bus <ul><li>the communication pathway between the CPU and immediate support chips. </li></ul><ul><li>used to transfer data </li></ul><ul><ul><li>between the CPU and the main system bus </li></ul></ul><ul><ul><li>between the CPU and an external memory cache. </li></ul></ul><ul><li>the purpose: </li></ul><ul><ul><li>to get information to and from the CPU at the fastest possible speed </li></ul></ul><ul><li>tied to the external processor pin connections </li></ul>
  5. 6. Memory Bus <ul><li>used to transfer information between the CPU and main memory--the RAM in system. </li></ul><ul><li>As a dedicated chipset that is responsible for transferring information between the processor bus and the memory bus. </li></ul><ul><li>The information that travels over the memory bus </li></ul><ul><ul><li>is transferred at a much slower rate than the information on the processor bus. </li></ul></ul><ul><li>The size of the memory bus: </li></ul><ul><ul><li>controls the amount of memory that the CPU can address directly. </li></ul></ul>
  6. 7. Address Bus <ul><li>a subset of the processor and memory buses. </li></ul><ul><li>used to indicate: </li></ul><ul><ul><li>what address in memory </li></ul></ul><ul><ul><li>what address on the system bus </li></ul></ul><ul><li>indicates precisely </li></ul><ul><ul><li>where the next bus transfer or </li></ul></ul><ul><ul><li>memory transfer will occur. </li></ul></ul>
  7. 8. Bus Architecture - Industry Standard Architecture (ISA)
  8. 9. Bus Architecture - Industry Standard Architecture (ISA) <ul><li>8 bit ISA Bus </li></ul><ul><ul><li>used in the original IBM PC computers. </li></ul></ul><ul><ul><li>called a Card/Edge connector. </li></ul></ul><ul><ul><li>An adapter card with 62 contacts on its bottom edge plugs </li></ul></ul><ul><ul><ul><li>into a slot on the motherboard that has 62 matching contacts. </li></ul></ul></ul><ul><ul><li>provides eight data lines and 20 addressing lines, enabling the slot to handle 1M of memory. </li></ul></ul>
  9. 10. Bus Architecture - Industry Standard Architecture (ISA) <ul><li>16 bit ISA Bus </li></ul><ul><ul><li>IBM introduced the 286 processor in 1984. </li></ul></ul><ul><ul><li>This processor had a 16-bit data bus, meant that </li></ul></ul><ul><ul><ul><li>communications between the processor and the motherboard as well as memory would now be 16 bits wide </li></ul></ul></ul><ul><ul><li>The introduction of the 286 chip posed a problem </li></ul></ul><ul><ul><li>IBM opted for the latter solution </li></ul></ul><ul><ul><ul><li>PC/AT was introduced with a set of expansion slots with 16-bit extension connectors. </li></ul></ul></ul>
  10. 11. Bus Architecture - Industry Standard Architecture (ISA) <ul><li>32 bit ISA Bus </li></ul><ul><ul><li>After 32-bit CPUs became available, </li></ul></ul><ul><ul><li>it was some time before 32-bit bus standards became available. </li></ul></ul>
  11. 12. Micro Channel Architecture (MCA) Bus
  12. 13. Micro Channel Architecture (MCA) Bus <ul><li>The introduction of 32-bit chips meant that the ISA bus could not handle the power of another new generation of CPUs. </li></ul><ul><li>IBM decided to build a new bus; </li></ul><ul><ul><li>the result was the MCA bus. </li></ul></ul>
  13. 14. Micro Channel Architecture (MCA) Bus <ul><li>MCA runs asynchronously with the main processor, </li></ul><ul><ul><li>meaning that fewer possibilities exist for timing problems among adapter cards plugged into the bus. </li></ul></ul><ul><li>An MCA system has no jumpers and switches </li></ul><ul><li>Through implementing bus mastering, the MCA bus provides significant performance improvements over the older ISA buses. </li></ul><ul><li>Each device is given a priority code to ensure that order is preserved within the system. </li></ul>
  14. 15. Micro Channel Architecture (MCA) Bus <ul><li>4 types of slots: </li></ul><ul><ul><li>16-bit </li></ul></ul><ul><ul><li>16-bit with video extensions </li></ul></ul><ul><ul><li>16-bit with memory-matched extensions </li></ul></ul><ul><ul><li>32-bit </li></ul></ul>
  15. 16. Extended Industry Standard Architecture (EISA Bus) <ul><li>was announced in September 1988 as a response to IBM's introduction of the MCA bus </li></ul><ul><li>developed primarily by Compaq </li></ul><ul><ul><li>taking over future development of the PC bus away from IBM. </li></ul></ul><ul><ul><li>gave the design away to other leading manufacturers. </li></ul></ul><ul><ul><li>formed the EISA Committee, a non-profit organization designed specifically to control development of the EISA bus. </li></ul></ul>
  16. 17. Extended Industry Standard Architecture (EISA Bus) <ul><li>provides 32-bit slots </li></ul><ul><li>enables manufacturers to design adapter cards that have many of the capabilities of MCA adapters, </li></ul><ul><li>supports adapter cards created for the older ISA standard. </li></ul><ul><li>permits greater system expansion with fewer adapter conflicts. </li></ul>
  17. 18. Extended Industry Standard Architecture (EISA Bus)
  18. 19. Extended Industry Standard Architecture (EISA Bus)
  19. 20. Extended Industry Standard Architecture (EISA Bus) <ul><li>adds 90 new connections (55 new signals) </li></ul><ul><ul><li>without increasing the physical connector size of the 16-bit ISA bus. </li></ul></ul><ul><li>The EISA adapter, however, has two rows of connectors. </li></ul><ul><ul><li>The first row is the same kind used in 16-bit ISA cards; </li></ul></ul><ul><ul><li>the other, thinner row extends from the 16-bit connectors. </li></ul></ul>
  20. 21. VESA Local Bus
  21. 22. VESA (Video Electronic Standards Associaion) Local Bus <ul><li>the most popular local bus design from its debut in August 1992 through 1994. </li></ul><ul><li>It was created by the VESA committee, a non-profit organization founded by NEC </li></ul><ul><ul><li>to further develop video display and bus standards. </li></ul></ul><ul><li>offers direct access to system memory at the speed of the processor itself. </li></ul><ul><li>can move data 32 bits at a time, </li></ul><ul><li>enabling data to flow between the CPU and a compatible video subsystem or hard drive </li></ul><ul><ul><li>at the full 32-bit data width of the 486 chip. </li></ul></ul>
  22. 23. VESA (Video Electronic Standards Associaion) Local Bus – Limitations: <ul><li>Dependence on a 486 CPU . </li></ul><ul><ul><li>tied to the 486 processor bus. </li></ul></ul><ul><ul><li>This bus is quite different from that used by Pentium processors (and probably from those that will be used by future CPUs). </li></ul></ul><ul><li>Speed limitations . </li></ul><ul><ul><li>provides for speeds of up to 66MHz on the bus </li></ul></ul><ul><ul><li>In practice, running the VL-Bus at speeds over 33MHz causes many problems, </li></ul></ul><ul><li>Electrical limitations . </li></ul><ul><ul><li>has very tight timing rules </li></ul></ul><ul><ul><li>designed for limited loading on the bus </li></ul></ul><ul><li>Card limitations . </li></ul><ul><ul><li>the number of VL-Bus cards is limited. </li></ul></ul>
  23. 24. Peripheral Component Interconnect (PCI) Bus
  24. 25. <ul><li>The PCI bus specification, released by Intel in June 1992 and updated in April 1993, </li></ul><ul><ul><li>redesigned the traditional PC bus by inserting another bus between the CPU and the native I/O bus by means of bridges. </li></ul></ul><ul><li>called a mezzanine bus </li></ul><ul><ul><li>adds another layer to the traditional bus configuration. </li></ul></ul><ul><li>uses the system bus to increase the bus clock speed </li></ul>Peripheral Component Interconnect (PCI) Bus
  25. 26. <ul><li>can operate concurrently with the processor bus </li></ul><ul><li>The CPU can be processing data in an external cache </li></ul><ul><ul><li>while the PCI bus is busy transferring information between other parts of the system </li></ul></ul>Peripheral Component Interconnect (PCI) Bus
  26. 27. System Resources <ul><li>the communications channels, addresses, and other signals </li></ul><ul><ul><li>used by hardware devices </li></ul></ul><ul><ul><li>to communicate on the bus. </li></ul></ul><ul><li>include the following: </li></ul><ul><ul><li>Memory addresses </li></ul></ul><ul><ul><li>IRQ (Interrupt ReQuest) channels </li></ul></ul><ul><ul><li>DMA (Direct Memory Access) channels </li></ul></ul><ul><ul><li>I/O Port addresses </li></ul></ul>
  27. 28. System Resources - IRQ (Interrupt ReQuest) channels <ul><li>used by various hardware devices to signal the motherboard that a request must be fulfilled. </li></ul><ul><li>represented by wires on the motherboard and in the slot connectors. </li></ul><ul><li>When a particular interrupt is invoked, </li></ul><ul><ul><li>a special routine takes over the system, </li></ul></ul><ul><ul><li>which first saves all the CPU register contents in a stack and </li></ul></ul><ul><ul><li>then directs the system to the interrupt vector table. </li></ul></ul><ul><ul><ul><li>contains a list of memory addresses that correspond to the interrupt channels. </li></ul></ul></ul><ul><ul><ul><li>Depending on which interrupt was invoked, the program corresponding to that channel is run. </li></ul></ul></ul>
  28. 29. System Resources - IRQ (Interrupt ReQuest) channels <ul><li>The pointers in the vector table point to the address of whatever software driver is used to service the card that generated the interrupt. </li></ul><ul><ul><li>For a network card, for example, the vector may point to the address of the network drivers that have been loaded to operate the card; </li></ul></ul><ul><ul><li>for a hard disk controller, the vector may point to the BIOS code that operates the controller. </li></ul></ul><ul><li>After the particular software routine finishes performing whatever function the card needed, the interrupt-control software </li></ul><ul><ul><li>returns the stack contents to the CPU registers, and </li></ul></ul><ul><ul><li>the system then resumes whatever it was doing before the interrupt occurred. </li></ul></ul><ul><li>Each time that a serial port presents a byte to your system, an interrupt is generated to ensure that the system reads that byte before another comes in. </li></ul><ul><li>Hardware interrupts are generally prioritized by their numbers; with some exceptions, the highest-priority interrupts have the lowest numbers. Higher-priority interrupts take precedence over lower-priority interrupts by interrupting them. As a result, several interrupts can occur in your system concurrently, each interrupt nesting within another. </li></ul>