nano materials

1. IEEE Nano 2003
Nanoelectronics: A Tutorial
Stephen M. Goodnick
Dept. Electrical Engineering, Arizona State
University

2. IEEE Nano 2003
OUTLINE
• Introduction
• Nano-Scale FETs
• Quantum Wells, Wires, Dots
• Quantum Coherent Devices
• Single Electron Devices
• Molecular Electronics
• Nanoelectronic Architectures
• Future Prospects

3. IEEE Nano 2003

4. IEEE Nano 2003
Nanotechnology/Nanoelectronics
• Nanotechnology is the design and construction of
useful technological devices whose size is a few billionths
of a meter
• Nanoscale devices will be built of small assemblies of
atoms linked together by bonds to form macro-molecules
and nanostructures
•Nanoelectronics encompasses nanoscale circuits and
devices including (but not limited to) ultra-scaled FETs,
quantum SETs, RTDs, spin devices, superlattice arrays,
quantum coherent devices, molecular electronic devices,
and carbon nanotubes.

5. IEEE Nano 2003
Motivation for Nanoelectronics
• Negative resistance devices, switches (RTDs,
molecular), spin transistors
• Single electron transistor (SET) devices and circuits
• Quantum cellular automata (QCA)
Limits of Conventional CMOS technology
• Device physics scaling
• Interconnects
Nanoelectronic alternatives?
Issues
• Predicted performance improves with decreased
dimensions, BUT
• Smaller dimensions-increased sensitivity to fluctuations
• Manufacturability and reproducibility
• Limited demonstration system demonstration
New information processing paradigms
• Quantum computing, quantum info processing (QIP)
• Sensing and biological interface
• Self assembly and biomimetic behavior

6. IEEE Nano 2003
OUTLINE
• Introduction
• Nano-Scale FETs
• Quantum Wells, Wires, Dots
• Quantum Coherent Devices
• Single Electron Devices
• Molecular Electronics
• Nanoelectronic Architectures
• Future Prospects

7. IEEE Nano 2003

8. IEEE Nano 2003
Moore’s Law driven by reduced
feature size

9. IEEE Nano 2003
Roadmap for silicon technology
Semiconductor Industry Association Roadmap for Semiconductors

10. IEEE Nano 2003
Nano-Scale CMOS
40 nm MOSFET

11. IEEE Nano 2003
1960 1970 1980 1990 2000 2010 2020
Minimum
geometries
(µm)
0.01
0.05
0.1
0.2
0.5
1
2
5
10
0.02
SIA road map
0.7 /Generation
Usual trend
0.688 /Generation
Wavelength
Scaling:
193
248
= 0.78
157
193
= 0.81
4K(Contact)
16K(Proximity)
64K(1:1Projection)
256K(10:1Projection)
1M (g-Line 5:1Projection)
16M (i-Line)
4M (g-Line)
256M
64M (i-Line, KrF-Eximer)
4G
16G
64G
1T
256G
1G
SIA
Road
m
ap
Moore’s Law
Moore’s Law
Brick Wall
Barrier
Optical
Lithography
EUV,
e-beam,
x-Ray
Time

12. IEEE Nano 2003

13. IEEE Nano 2003

14. IEEE Nano 2003

15. IEEE Nano 2003
SRC
International
Technology
Roadmap
for
Semiconductors
2000 Update
Lithography

16. IEEE Nano 2003

17. IEEE Nano 2003
Lyding et al., Appl. Phys. Lett. 64, 2010 (1994).
Joe Lyding and Karl Hess
Joe Lyding and Karl Hess
p
p-
-Si
Si
SiO
SiO2
2 SiO
SiO2
2
n-
n-
n+
n+
H H
CMOS STM
Reliability Issues: Deuterium Processing
Reliability Issues: Deuterium Processing
CMOS/STM Analogy
CMOS/STM Analogy

18. IEEE Nano 2003
Si/SiO2 interface
Roughness
0
1
2
1
10
100
1000
10000
0.0 1.0 2.0 3.0
Height (nm)
Frequency
∆ = 0.285 nm
0
1000
2000
0.0 1.0 2.0
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
Distance x (nm)
a(x)
Exponential Fit:
Λ =2.42 nm
Autocovariance
Function
a(x)=<s(x')s(x'-x)>
∆Λ=0.69nm-2

19. IEEE Nano 2003

20. IEEE Nano 2003

21. IEEE Nano 2003
FinFET

22. IEEE Nano 2003
Source: Gelsinger, 2001 ISSCC
CMOS Power/Speed Issues
f
V
C
P dd
ox
diss
2
=

23. IEEE Nano 2003
Nanotechnology and Charge Control Issues
Nanotechnology and Charge Control Issues
1988
10-1
Year
Channel
Electrons
1992 1996 2000 2004 2008 2012 2016 2020
100
101
102
103
104
16M
64M
256M
1G
4G
16G
16M 64M
256M
1G
4G
16G Memory Capacity/Chip
4M

24. IEEE Nano 2003
• Problem:
– the demise of exponential scaling by lithography
(prohibitive cost)
• Fundamental issues:
– devices lithographically determined
– interconnection dominates
• Generic solution:
– self-assembly
• Present state-of-the-art:
– molecular device demonstrations
• Challenge:
– Complex self-assembled circuit
1990 1995 2000 2005 2010 2015
0.1
1
10
100
Fab
cost
($B
US)
Year of Construction
Moore’s Second Law
Moore’s Second Law
Doubling time
~ 3 years
by 2025
- 1.5 meter wafer
- 27 level metal
Microelectronics is Not a Silicon Technology
So Much as it is a Lithography Technology

25. IEEE Nano 2003
Electronics in 30 Years

26. IEEE Nano 2003
International Technology Roadmap for Semiconductors