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UART RECEIVER
INTRODUCTION
 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
 UART is a device that has the capability to both receive and transmit serial
data.
 A universal asynchronous receiver-transmitter is a computer hardware
device for asynchronous serialcommunication in which the data format and
transmission speeds are configurable.
 UART exchanges text data in an American Standard Code for
Information Interchange (ASCII) formatin which each alphabetical
character is encoded by 7 bits and transmitted as 8 data bits.
 Communication may be simplex (in one direction only, with no provision
for the receiving deviceto send information backto the transmitting device),
full duplex (both devices send and receive at the same time) or half
duplex (devices take turns transmitting and receiving)
 Latest standardUARTemploy FIFObuffer for improvedfunctional capability.
 A UART usually contains the following components:
 Baud rate clock generator: Multiple of the bit rate to improve
sampling in the middle of a bit period. For generating this timing
information, each UART uses an oscillator generating a frequency of
about 1.8432 MHz. This frequency is divided by 16 to generate the
time base for communication. Hence the maximum allowed
communication speed is 115200 bps. UARTs like the 16550 are
capable of handling higher input frequencies up to 24 MHz which
makes it possible to communicate with a maximum speed of 1.5
Mbps. ·
 Input and output shift registers: Each UART contains a shift register
which is the fundamental method of conversion between serial and
parallel forms. These registers shifts the data that has to be serially
transmitted or serially received.
 Transmitand receivecontrol:This controllogic checks for thecontrol
signals from host processor to start or stop the transmission and
reception of the data bits. In case of any error it also generates error
signals.
 Optional transmit and receive buffers: Buffers can be used to hold
the data temporarily.
 Optional parallel data bus buffer: This buffer improves the speed.
 Optional FIFO: The UART works by writing data from the host
processor to its FIFO buffers, and feeding the data from the buffer to
the serial device in the format dictated by the user.
DATA FRAMING
 UART transmitter controls transmission by fetching a data word in parallel
format and directing the UART to transmit it in a serial format.
 The receiver mustdetect transmission,receivethe data in serialformat,strip
of the start and stop bits, and store the data word in a parallel format.
 For transmission theUART protocolwraps this 8 bit sub word with a startbit
in theleast significantbit (LSB)and a stopbit in the mostsignificantbit (MSB)
resulting in a 10 bit word format.
 Parity bit is added when the entire data word has been sent. This bit can be
used to detect errors at the receiver side. Then one Stop Bit is sent by the
transmitter to indicate the end of the valid data bit.
 The UART is asynchronousin working, the receiver does not know when the
data will come, so receiver generate local clock in order to synchronize to
transmitter whenever start bit is received.
 Asynchronous transmission allows data to be transmitted without the
sender having to send a clock signal to the receiver.
 When a wordis givento theUART forAsynchronoustransmission,abitcalled
the “Start Bit” is added to the beginning of each word that is to be
transmitted. The Start Bit is used to alert the receiver that a word of data is
about to be sent, and to forcethe clock in the receiver into synchronization
with the clock in the transmitter.
 After the Start Bit, the individual bits of the word of data are sent, with the
Least Significant Bit (LSB) being sent first. Each bit in the transmission is
transmitted for exactly the same amount of time as all of the other bits.
 When the receiver receives the data it examines each bit and determine if
the bit is a 1 or a 0 for a particular period of time.
 For example, if it takes two seconds to send each bit, the receiver will
examine the signalto determine if it is a 1 or a 0 after onesecond haspassed,
then it will waittwo seconds and then examine the value of the next bit, and
so on. Then at least one stop bit is sent by the transmitter. Because
asynchronous data is “Self synchronous”, if there is no data to transmit, the
transmission line can be idle.
 In the receiver side once it receives all of the bits in the data word, it can
check for the Parity Bits. To accomplish this task both transmitter and
receiver must agree on whether a Parity Bit is to be used. Then Stop Bit is
encountered by receiver. A missing stop bit may result entire data to be
garbage. This will cause a Framing Error and will be reported to the host
processor when the data word is read. Framing Error can be caused due to
mismatch of transmitter and receiver clocks.
 The UART automatically discards the Start, Parity and Stop bits irrespective
of whether data is received correctly or not. If the sender and receiver are
configuredidentically, these bits are not passedto the host.To transmitnew
word, the Start Bit for the new word is sent as soon as the Stop Bit for the
previous word has been sent.
 The transmission speed in asynchronous communication is measured by
Baud Rate. A Baud Rate representsthe number of bits thatare actually being
sent over the media. The Baud rate includes the Start, Stop and Parity bits.
The Bit rate (Bits per Second-bps) represents the amount of data that is
actually sent from the transmitting device to the other device. Speeds for
UARTs are in bits per second (bit/s or bps), although often incorrectly called
the baud rate.
Where
Read_ not_ ready_ in =signals that the host is not ready to receive data.
Serial in = serial bit stream received by the unit.
enable = active enable bit
Sample counter= counts the samples of a bit.
Bit counter = counts the bits that have been sampled.
Read not ready out = signals that the receiver has received 8 bits.
inc sample counter = increments sample counter.
Clr Sample counter = clears Sample counter.
Inc Bit counter = increments Bit counter.
Clr Bit counter = clears Bit counter.
load = causes RCV shift register to transfer data to RCV data register.
shift = causes RCV shift register to shift towards the LSB.
Error1 = asserts if host is not ready to receive data.
Error2 = asserts if the stop bit is missing.

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UART Receiver Guide: Everything You Need to Know

  • 1. UART RECEIVER INTRODUCTION  UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER  UART is a device that has the capability to both receive and transmit serial data.  A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serialcommunication in which the data format and transmission speeds are configurable.  UART exchanges text data in an American Standard Code for Information Interchange (ASCII) formatin which each alphabetical character is encoded by 7 bits and transmitted as 8 data bits.  Communication may be simplex (in one direction only, with no provision for the receiving deviceto send information backto the transmitting device), full duplex (both devices send and receive at the same time) or half duplex (devices take turns transmitting and receiving)  Latest standardUARTemploy FIFObuffer for improvedfunctional capability.  A UART usually contains the following components:  Baud rate clock generator: Multiple of the bit rate to improve sampling in the middle of a bit period. For generating this timing information, each UART uses an oscillator generating a frequency of about 1.8432 MHz. This frequency is divided by 16 to generate the time base for communication. Hence the maximum allowed communication speed is 115200 bps. UARTs like the 16550 are capable of handling higher input frequencies up to 24 MHz which makes it possible to communicate with a maximum speed of 1.5 Mbps. ·  Input and output shift registers: Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. These registers shifts the data that has to be serially transmitted or serially received.
  • 2.  Transmitand receivecontrol:This controllogic checks for thecontrol signals from host processor to start or stop the transmission and reception of the data bits. In case of any error it also generates error signals.  Optional transmit and receive buffers: Buffers can be used to hold the data temporarily.  Optional parallel data bus buffer: This buffer improves the speed.  Optional FIFO: The UART works by writing data from the host processor to its FIFO buffers, and feeding the data from the buffer to the serial device in the format dictated by the user. DATA FRAMING  UART transmitter controls transmission by fetching a data word in parallel format and directing the UART to transmit it in a serial format.  The receiver mustdetect transmission,receivethe data in serialformat,strip of the start and stop bits, and store the data word in a parallel format.  For transmission theUART protocolwraps this 8 bit sub word with a startbit in theleast significantbit (LSB)and a stopbit in the mostsignificantbit (MSB) resulting in a 10 bit word format.  Parity bit is added when the entire data word has been sent. This bit can be used to detect errors at the receiver side. Then one Stop Bit is sent by the transmitter to indicate the end of the valid data bit.  The UART is asynchronousin working, the receiver does not know when the data will come, so receiver generate local clock in order to synchronize to transmitter whenever start bit is received.  Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver.  When a wordis givento theUART forAsynchronoustransmission,abitcalled the “Start Bit” is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is
  • 3. about to be sent, and to forcethe clock in the receiver into synchronization with the clock in the transmitter.  After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits.  When the receiver receives the data it examines each bit and determine if the bit is a 1 or a 0 for a particular period of time.  For example, if it takes two seconds to send each bit, the receiver will examine the signalto determine if it is a 1 or a 0 after onesecond haspassed, then it will waittwo seconds and then examine the value of the next bit, and so on. Then at least one stop bit is sent by the transmitter. Because asynchronous data is “Self synchronous”, if there is no data to transmit, the transmission line can be idle.  In the receiver side once it receives all of the bits in the data word, it can check for the Parity Bits. To accomplish this task both transmitter and receiver must agree on whether a Parity Bit is to be used. Then Stop Bit is encountered by receiver. A missing stop bit may result entire data to be garbage. This will cause a Framing Error and will be reported to the host processor when the data word is read. Framing Error can be caused due to mismatch of transmitter and receiver clocks.  The UART automatically discards the Start, Parity and Stop bits irrespective of whether data is received correctly or not. If the sender and receiver are configuredidentically, these bits are not passedto the host.To transmitnew word, the Start Bit for the new word is sent as soon as the Stop Bit for the previous word has been sent.  The transmission speed in asynchronous communication is measured by Baud Rate. A Baud Rate representsthe number of bits thatare actually being sent over the media. The Baud rate includes the Start, Stop and Parity bits. The Bit rate (Bits per Second-bps) represents the amount of data that is actually sent from the transmitting device to the other device. Speeds for UARTs are in bits per second (bit/s or bps), although often incorrectly called the baud rate.
  • 4. Where Read_ not_ ready_ in =signals that the host is not ready to receive data. Serial in = serial bit stream received by the unit. enable = active enable bit Sample counter= counts the samples of a bit. Bit counter = counts the bits that have been sampled. Read not ready out = signals that the receiver has received 8 bits. inc sample counter = increments sample counter. Clr Sample counter = clears Sample counter. Inc Bit counter = increments Bit counter. Clr Bit counter = clears Bit counter. load = causes RCV shift register to transfer data to RCV data register. shift = causes RCV shift register to shift towards the LSB. Error1 = asserts if host is not ready to receive data. Error2 = asserts if the stop bit is missing.