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Electronic Devices - Integrated Circuit.pdf

Planar process of IC fabrication Photolithography Chemical vapour deposition Vapour Phase Epitaxy Sputtering Etching Twin-tub process

1 of 46
Integrated Circuit
Monolithic Integrated Circiut Technology
Monolithic Integrated Circiut Technology
Advantages of IC Technology
Planar Process
1. Crystal Growth
Silicon Ingot
Silicon Wafer

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Electronic Devices - Integrated Circuit.pdf

  • 4. Advantages of IC Technology
  • 6. 1. Crystal Growth Silicon Ingot Silicon Wafer
  • 20. Chemical Vapour Deposition • Vapor deposition is the transformation of vapors into solids, frequently used to grow solid thin film and powder materials. • CVD is a generic name for a group of process that involves deposition of a solid on a heated surface from a chemical reaction in the vapor phase. • The process is shown schematically in Figure 1 below. Figure 1: Schematic representation of a chemical vapor deposition process
  • 21. Chemical Vapour Deposition • In Figure 1, it is observed that the main constituents of the CVD process are a gaseous precursor (AB2), energy (Heater), reactor, solid product (A) and gas phase product (B2). • In the CVD process, the substrate is loaded into the chamber using a substrate loading mechanism. • A vacuum system is used for the removal of all other gaseous species other than those required for the deposition. • Then the precursor gases are delivered into the reaction chamber using a gas delivery system and heated (by the energy source) as it approaches the deposition surface. • As the precursor gases pass over or come into contact with a heated substrate, they react or decompose forming a solid phase which is deposited onto the substrate. • Finally the volatile by-products are removed from the reaction chamber by an exhaust system. • There are several types of CVD, which are classified based on their heating source, the process pressure, the reactor configuration and other parameters e.g. Atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), metalorganic CVD (MOCVD), plasma enhanced CVD (PECVD) etc.
  • 22. Vapour Phase Epitaxy (VPE) or Chemical Vapor Deposition (CVD) • In this technique, the species required for the growth are transported to the substrate as vapours using high purity hydrogen as the carrier gas. • The species may be in the form of either elemental or compound gases. • In the case of elemental species, the atoms from the vapour, when they reach the heated surface of the substrate, undergo surface dissociation and combine to form the epitaxial material. • In case of compound gases, they dissociate out at over the substrate to form elements which then diffuse along the surface to form the epi layer. • Two types of reactors are used for VPE growth: Horizontal and vertical. Horizontal VPE Vertical VPE
  • 23. Thin Films • Thin films of metal are used for various purposes in the fabrication of semiconductor devices and integrated circuits. • These include the formation of metal-semiconductor ohmic contacts and gate metallization in MOS devices. • In addition, the electrical contacts between various devices in an integrated circuit are made by narrow channels of thin gold films. • Gold films are mostly used in devices. • The other most frequently used metals are Al, Cu, Ag, Ni and W and alloys of metals and nonmetals.
  • 24. Physical Vapour Deposition • In this technique, the desired metal is heated to a high temperature to convert it into vapour. • This vapour is made to reach the substrate surface to solidify into a thin film. • To avoid oxidation of the metal and to avoid collision of the metal atoms with gas atoms, vapour deposition is carried out in a chamber which is evacuated to around 10-6 Torr. • Usually, the metal is contained in a `boat` made of certain high melting point metal, such as tungsten, tantalum or molybdenum. • Heating is done by sending a high current of the order of 100-200A through the metal boat. • In certain cases, the evaporation boat made of graphite is used.
  • 25. Sputtering • Sputter deposition is a physical vapour deposition (PVD) method of depositing thin films by sputtering material from a ‘target’, then depositing it onto a ‘substrate’. • The sputtering chamber contains an inert gas like argon at low temperatures. • Two electrodes are placed inside the chamber and are connected to the positive and negative terminals of a high voltage source. • The cathode electrode, called the ‘target’ contains the metal to be deposited. The semiconductor substrate is placed near the target. • As a high voltage is applied between the cathode and the anode, positive ions and electrons are produced. • Positive ions are energized by the electric field and strike the target at high velocity. • In the process, the energy of the ion is transferred to a target atom which is ejected out and is deposited over the substrate. • Even very high melting point metals can be deposited by sputtering and sputtering can also be used for the deposition of non-metallic thin films. However, the quality of sputtered films is not as good as vacuum evaporated films.
  • 26. Etching • Etching refers to the removal of material from the wafer surface. • The process is usually combined with lithography in order to select specific areas on the wafer from which material is to be removed. • Etching represents one way of permanently transferring the mask pattern from the photoresist to the wafer surface. • The complementary process to etching is deposition (or growth), where new material is added. • Unlike oxidation (or nitridation), where the underlying Si is consumed to form the oxide (nitride) layer, in deposition, new material is added without consuming the underlying wafer. • There are two main types of etching: A. Dry Etching B. Wet Etching
  • 27. Wet Etching • In wet etching, the wafers are immersed in a tank of the etchant (mix of chemicals). • There is a chemical reaction between the wafer surface and the etchants that helps in material removal. • Either a photoresist layer or a hard mask like oxide or nitride layer is used to protect the rest of the wafer. • The time for etching depends on the amount and type of material that needs to be removed. • KOH (potassium hydroxide) is a common etchant used to remove Si. Usually, 30% KOH solution is used, which has a etch rate of ~100 µm/hr at 90◦C. Thus, an entire 4″ wafer, with thickness of 500 µm, can be etched through in approximately 5 hours. • After etching, the wafers are rinsed, usually in DI water, for removal of etchant and then finally dried. • Wet etching is used for removal of material from large areas (trench sizes > 3 µm). • For smaller areas, where greater precision in removal of material is required, dry etch is preferred.
  • 28. Wet Etching • The wet etching process is anisotropic i.e. The etch rate depends on the plane of the Si wafer, from which atoms are being removed. • This means that wet etching of Si(100) will produce a trapezoidal profile, with a specific angle of 54.74 deg, as shown in figure 4. • Etching uniformity is important to get a uniform thickness over the entire wafer surface. This is usually determined by process conditions like etchant temperature, concentration, and agitation (using stirrers).
  • 29. Dry Etching • Dry etching, as the name suggest, is removal of material in the absence of solvent. • The process was introduced because wet etching has some limitations in its applicability, which are listed below: 1. Wet etching is used for large pattern sizes, usually larger than 2 µm. 2. It is anisotropic process - sloped sidewalls rather than straight walls. Figure 10: Various steps from (1) - (5) in the dry etch process. Gases are transported to the wafer surface, where they adsorb and react with the wafer surface material, at the step edges. The gases then desorb from the surface.
  • 30. Classification of Dry Etch • There are three main types of dry etching: 1. Plasma etch 2. Ion beam milling 3. Reactive ion etch
  • 31. Photolithography • Photolithography is the process of transferring geometric shapes on a mask to the surface of a silicon wafer. • The steps involved in the photolithographic process are wafer cleaning; barrier layer formation; photoresist application; soft baking; mask alignment; exposure and development; and hard-baking.
  • 32. A. Wafer Cleaning, Barrier Formation and Photoresist Application • In the first step, the wafers are chemically cleaned to remove particulate matter on the surface as well as any traces of organic, ionic, and metallic impurities. • After cleaning, silicon dioxide, which serves as a barrier layer, is deposited on the surface of the wafer. • After the formation of the SiO2 layer, photoresist is applied to the surface of the wafer. • High-speed centrifugal whirling of silicon wafers is the standard method for applying photoresist coatings in IC manufacturing. • This technique, known as "Spin Coating," produces a thin uniform layer of photoresist on the wafer surface.
  • 33. Positive and Negative Photoresist • There are two types of photoresist: positive and negative. • For positive resists, the resist is exposed with UV light wherever the underlying material is to be removed. • In these resists, exposure to the UV light changes the chemical structure of the resist so that it becomes more soluble in the developer. • The exposed resist is then washed away by the developer solution, leaving windows of the bare underlying material. In other words, "whatever shows, goes." • The mask, therefore, contains an exact copy of the pattern which is to remain on the wafer. • Negative resists behave in just the opposite manner. • Exposure to the UV light causes the negative resist to become polymerized, and more difficult to dissolve. • Therefore, the negative resist remains on the surface wherever it is exposed, and the developer solution removes only the unexposed portions. • Masks used for negative photoresists, therefore, contain the inverse (or photographic "negative") of the pattern to be transferred. • Negative resists were popular in the early history of integrated circuit processing, but positive resist gradually became more widely used since they offer better process controllability for small geometry features. Positive resists are now the dominant type of resist used in VLSI fabrication processes.
  • 34. Positive and Negative Photoresist
  • 35. B. Soft Baking • Soft-baking is the step during which almost all of the solvents are removed from the photoresist coating. • Soft-baking plays a very critical role in photo-imaging. • The photoresist coatings become photosensitive, or imageable, only after softbaking. • Oversoft-baking will degrade the photosensitivity of resists by either reducing the developer solubility or actually destroying a portion of the sensitizer. • Undersoft- baking will prevent light from reaching the sensitizer. • Positive resists are incompletely exposed if considerable solvent remains in the coating. • This undersoft-baked positive resists is then readily attacked by the developer in both exposed and unexposed areas, causing less etching resistance.
  • 36. C. Mask Alignment and Exposure • One of the most important steps in the photolithography process is mask alignment. • A mask or "photomask" is a square glass plate with a patterned emulsion of metal film on one side. • The mask is aligned with the wafer, so that the pattern can be transferred onto the wafer surface. • Each mask after the first one must be aligned to the previous pattern. • Once the mask has been accurately aligned with the pattern on the wafer's surface, the photoresist is exposed through the pattern on the mask with a high intensity ultraviolet light. • There are three primary exposure methods: contact, proximity, and projection.
  • 37. I. Contact Printing • In contact printing, the resist-coated silicon wafer is brought into physical contact with the glass photomask. • The wafer is held on a vacuum chuck, and the whole assembly rises until the wafer and mask contact each other. • The photoresist is exposed with UV light while the wafer is in contact position with the mask. • Because of the contact between the resist and mask, very high resolution is possible in contact printing (e.g. 1-micron features in 0.5 microns of positive resist). • The problem with contact printing is that debris, trapped between the resist and the mask, can damage the mask and cause defects in the pattern.
  • 38. II. Proximity Printing • The proximity exposure method is similar to contact printing except that a small gap, 10 to 25 microns wide, is maintained between the wafer and the mask during exposure. • This gap minimizes (but may not eliminate) mask damage. • Approximately 2- to 4-micron resolution is possible with proximity printing.
  • 39. III. Projection Printing • Projection printing, avoids mask damage entirely. • An image of the patterns on the mask is projected onto the resist-coated wafer, which is many centimeters away. • In order to achieve high resolution, only a small portion of the mask is imaged. • This small image field is scanned or stepped over the surface of the wafer. • Projection printers that step the mask image over the wafer surface are called step-and-repeat systems. • Step-and-repeat projection printers are capable of approximately 1-micron resolution.
  • 40. D. Development • One of the last steps in the photolithographic process is development. • The figure below shows response curves for negative and positive resist after exposure and development. • At low-exposure energies, the negative resist remains completely soluble in the developer solution. • As the exposure is increased above a threshold energy ET, more of the resist film remains after development. • At exposures two or three times the threshold energy, very little of the resist film is dissolved. • For positive resists, the resist solubility in its developer is finite even at zero-exposure energy. • The solubility gradually increases until, at some threshold, it becomes completely soluble. • These curves are affected by all the resist processing variables: initial resist thickness, prebake conditions, developer chemistry, developing time, and others.
  • 42. E. Hard Baking • Hard-baking is the final step in the photolithographic process. • This step is necessary in order to harden the photoresist and improve adhesion of the photoresist to the wafer surface.
  • 43. Duel-well Process or Twin-tub Process • In Duel-well process both p-well and n-well for NMOS and PMOS transistors respectively are formed on the same substrate. • The main advantage of this process is that the threshold voltage, body effect parameter and the transconductance can be optimized separately. • The starting material for this process is p+ substrate with epitaxially grown p-layer which is also called as epilayer. • The process steps of twin-tub process are shown in Figure below. • The process starts with a p-substrate surfaced with a lightly doped p-epitaxial layer.
  • 44. Duel-well Process or Twin-tub Process Step 1 : A thin layer of SiO2 is deposited which will serve as the pad oxide. Step 2 : A thicker sacrificial silicon nitride layer is deposited by chemical vapour deposition. Step 3 : A plasma etching process is used to create trenches used for insulating the devices. Step 4 : The trenches are filled with SiO2 which is called as the field oxide. .
  • 45. Duel-well Process or Twin-tub Process Step 5 : To provide flat surface chemical mechanical planarization is performed and also sacrificial nitride and pad oxide is removed. Step 6 : The p-well mask is used to expose only the p-well areas, after this implant and annealing sequence is applied to adjust the well doping. This is followed by second implant step to adjust the threshold NMOS transistor. Step 7 : The n-well mask is used to expose only the n-well areas, after this implant and annealing sequence is applied to adjust the well doping. This is followed by a second implant step to adjust the threshold voltage of PMOS transistor. Step 8 : A thin layer of gate oxide and polysilicon is chemically deposited and patterned with the help of polysilicon mask.
  • 46. Duel-well Process or Twin-tub Process Step 9 : Ion implantation to dope the source and drain regions of the PMOS (p +) and NMOS (n+) transistors is used this will also form n+ polysilicon gate and p+ polysilicon gate for NMOS and PMOS transistors respectively. Step 10 : Then the oxide or nitride spacers are formed by chemical vapour deposition (CVD). Step 11 : In this step contact or holes are etched, metal is deposited and patterned. After the deposition of last metal layer final passivation or overglass is deposited for protection.