In 1965, Gordon Moore’s forecast that the number of components (transistors) on an integrated circuit would double every year until it reached an astonishing 65,000 by 1975 [1]. Moore’s statement was an economic one . The cost per component is nearly inversely proportional to the number of components.

1. MORE THAN MOORE’S
Riadh Al-Haidari

2. 2
S L I D E T I T L E H E R E O R S E C T I O N T I T L E
Moore’s Law
 In 1965, Gordon Moore’s forecast that
the number of components (transistors)
on an integrated circuit would double
every year until it reached an
astonishing 65,000 by 1975 [1].
 Moore’s statement was an economic
one .
 The cost per component is nearly
inversely proportional to the number of
components.
IMAGE GOES HERE

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S L I D E T I T L E H E R E O R S E C T I O N T I T L E
Moore’s Law
 Moore’s Law defines a half-century of
progress and that because the
semiconductor industry decided it would.
 His roadmap was like a promise land for
governments, academic and industrial
researchers to pour money and time into
upholding Moore’s Law
 This effort had created a self-fulfilling
prophecy that kept progress on track with
uncanny accuracy [1].
IMAGE GOES HERE
Electronics Magazine in which
Moore’s posted his article in April
1965 .
Wikimedia

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S L I D E T I T L E H E R E O R S E C T I O N T I T L E
The Economics value of Moore’s Law
• Relationships between Moore’s Law and fabrication cost trends for integrated
circuits can be described by the following identity [3].
• As number of elements(transistors) increases in silicon wafer area, the
transistor fabrication cost decrease (higher performance lower cost), while
wafer-processing cost per area of silicon roughly constant [3].
• Semiconductor Manufacturing is a general-purpose technology, so huge efforts
has been done to wafer processing techniques which leads to roughly constant
cost of wafer processing

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S L I D E T I T L E H E R E O R S E C T I O N T I T L E
Moore’s Law slow down
• The number of transistors per unit area doubling about every 24 months, a rate
now at the limits of physics.
• TSMC (Taiwan Semiconductor Manufacturing Company) can already scale its
process to seven nanometers (= 0.000007 millimeters).
• Less than five nanometers (~2 atomic layers), the process becomes technically
critical, as physical tunnel effects would undermine the switching effect of
semiconductors, and extremely expensive [4].
• With less 5 nm will lead to increase the number of physics-related problems, such
as multiple types of noise, thermal effects and electromigration, so we need
alternative to trade-off cost-performance [4]

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S L I D E T I T L E H E R E O R S E C T I O N T I T L E
More than Moore
• More than Moore (MtM) refers to the
technologies and products that are
based upon or derived from silicon
technologies but is not scaled by
Moore’s law [5].
• Moore’s law concentrate essentially
on digital function While MtM focusing
mainly on non-digital function and
heterogeneous integration[5].

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S L I D E T I T L E H E R E O R S E C T I O N T I T L E
More than Moore
• Three major methods are underway in “More Than Moore”
model [4]:
I. Heterogeneous Integration (System-in-Package, SiP)
II. Improvements in multi-chip performance such as fan-out wafer-level
packaging.
III. Huge advanced packaging

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S L I D E T I T L E H E R E O R S E C T I O N T I T L E
Chips (Chiplets) in More Than
Moore
• Packing more transistors on a monolithic IC is
becoming harder and more expensive.
• New method (Heterogeneous Integration ) to improve
cost-performance by adding more functionality
through integration.
• This enables the packaged-chip to perform a specific
and advanced function in a small form factor [8]
Integration
Intel Agilex FPGA Chiplet application. Source: Intel
Heterogeneous
Integration (HI)
Source ASE
Group [8]

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S L I D E T I T L E H E R E O R S E C T I O N T I T L E
Chiplets
• Pros
 This technology enables the continued increase in functional density and
decrease in cost per function required to maintain the progress in cost and
performance for electronics
 Higher performance, lower latency, smaller size, lighter weight, lower power
requirement per function, Lowe cost due to [9].
• Cons
• Increased thermal density, hot spots and circuit density and many technical
problems due to different material, shape size on the substrate [9]
• Changing the whole chip if any component fails.

10. References
• [2] https://www.technologyreview.com/2020/02/24/905789/were-not-prepared-for-the-end-of-moores-law/
• [3] Flamm, Kenneth. "Moore's law and the economics of semiconductor price trends." International Journal of Technology, Policy and Management 3.2 (2003): 127-141.
• [4] Flamm, Kenneth. "Measuring Moore’s law: evidence from price, cost, and quality indexes." Measuring and Accounting for Innovation in the 21st Century. University of Chicago Press,
2019.
• [5] Zhang, G. Q., Mart Graef, and Fred van Roosmalen. "The rationale and paradigm of" more than Moore"." 56th Electronic Components and Technology Conference 2006. IEEE, 2006.
• [6] https://semiengineering.com/more-than-moore-reality-check/
• [7] Arden, Wolfgang, et al. "More-than-Moore white paper." Version 2 (2010): 14.
• [8]https://ase.aseglobal.com/en/heterogeneous_integration#:~:text=Heterogeneous%20Integration%20refers%20to%20the,functionality%20and%20improved%20operating%20charact
eristics.
• [9] https://www.semiconductors.org/wp-content/uploads/2018/06/2_2015-ITRS-2.0-Herogeneous-Integration.pdf