1. DESIGN DESIGN
REVIEW REVIEW
CONNECTING
Design considerations for the Programming the Digital Potentiometers Resources
anti-aliasing filter The potentiometers are programmed from an [1] Software drivers for the AN16 module
The frequency plots in Fig.1 provide a I2C serial bus with two allocated to each filter together with full code listings of sample
ThE aNalOGUE
graphical representation of aliasing. In this controlling the resistive components which set programs can be downloaded from the EDP
example we are going to sample a signal the cut-off frequency. [1] Advantage is taken Design Centre on the DesignSpark website at:
which has a maximum frequency component of a simplification of the Sallen-Key filter which http://www.designspark.com/design-centre.
of fmax (the band in green) using a sampling occurs when the two resistances and two
WORlD TO
frequency of fs. The plot on the left shows capacitances are in the ratio 2 to 1. [2] [2] Analysis of the Sallen-Key Architecture, TI
all the new frequencies present in the non- Application Report, SLOA024B.
aliased sampled signal. Note that we now
RS EDP
have new bands of frequencies (in blue) each
with a width of 2 x fmax and centred on the Share your views on this article
sampling frequency ƒs and its harmonics. This at www.designspark.com
is a correctly sampled signal because fs > 2 x
fmax. By contrast the plot on the right shows
extensive aliasing where the various bands
overlap leading to the production of erroneous
frequencies in the green baseband. dB
analogue Input module: Setting up the anti-aliasing filter 0 2-Pole Filters, AN0 or AN1
The practical problem is that few ‘raw’ signals Roll-off = -40dB/decade
have a nice, clean fmax. In order to avoid
aliased components being produced, a low- -
Get the Specification pass anti-aliasing filter needs to be placed in 20
4-Pole Filter, AN0 + AN1
circuit before the ADC. Roll-off = -80dB/decade
Before the considering the analogue input f > 2f : No aliasing f < 2f : aliasing
S max S max
to a digital system, the designer must have -
available a certain amount of numerical data: Fig.2 shows the trade-off between sampling 40
Signal Power Signal Power rate and the order of the low-pass filter. The
• The maximum frequency component of Aliased Frequencies designer can massively over-sample and then -
the analogue signal use a simple low-order filter or select a lower 60
rate and then be faced with the need for a
• The Dynamic Range of the analogue complex multi-pole type. However the ability
signal (ratio of the maximum to the of the DSP device to process the algorithm
minimum input signal level) between consecutive samples must be 100 1000 10000 100000 1000000 f Hz
• The required Signal-to-Noise ratio of the considered before the sampling rate is set. Filter cut-off range
digitized signal It can save a lot of trouble later if the DSP AN0 or AN1
program is tested and timed on a suitable
fig. 3 frequency response of digitally-controlled filters on aN0 and aN1
development system before the sampling rate
The first point is what concerns us here when is fixed and the filter designed.
deciding on the cut-off frequency of the input fig.1 aliasing
analogue low-pass-filter. anti-aliasing filters on the analogue
Input module (EDP-am-aN16)
Signal Power
Decide on the sampling rate Sampling rate mUCh greater than Nyquist Sallen-Key filters are used on the Analogue
The sampling rate is set according to the Input module which provides filter circuits for
Nyquist criterion which states that it must be up to 16 input channels. Eight have simple
Lower Order, shallow roll-off LPF required Rf = 6772556u/Fcut_off; /* Calculate filter R2 resistor value */
at least twice that of the maximum frequency passive 1-pole filters, six have fixed cut-off R2_Pot = 12000u*Rf/(12000u-Rf); /* Digital pot in parallel with 12k resistor */
component present in the analogue signal. This (12kHz) 2-pole Sallen-Key filters with a roll-off R1_Pot = R2_Pot/2u; /* R1 resistor value = R2/2 */
ensures accurate reproduction of the signal, of -40dB/decade and two have 2-pole filters
but a much higher rate will ease the design whose cut-off frequency can be set by digital Set_resistance(1u,R1_Pot); /* Call AN16 driver and set Pot channel 1 */
of a vital circuit that precedes the ADC: potentiometers. These two filters on channels Set_resistance(2u,R2_Pot); /* Call AN16 driver and set Pot channel 2 */
the Anti-Aliasing filter. AN0 and AN1 can be cascaded by means of
Signal Power a solder-link to provide a single 4-pole filter on
AN0 with -80dB/decade roll-off. listing 1. C code for calculating the aN0 filter resistance values
Sampling rate JUST greater than Nyquist
High Order, steep roll-off LPF required
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fig.2 Designing the anti-aliasing filter: Cut-off and Roll-off See the latest on EDP at www.designspark.com/theme/rs-edp
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