UNIT-I 191EEC303T LIC.pdf

EASWARI ENGINEERING COLLEGE
(AN AUTONOMOUS INSTITUTION)
( A Unit of SRM Group of Educational Institutions,
Affiliated to Anna University, Chennai and ISO certified )
Accredited by NAAC with A grade and NBA
191EEC303T- LINEAR INTEGRATED CIRCUITS
UNIT – 1 IC FABRICATION
Ms.B.PONKARTHIKA
ASSISTANT PROFESSOR
DEPARTMENT OF EEE
EASWARI ENGINEERING COLLEGE
CHENNAI
B.PONKARTHIKA/EEE/EEC/191EEC303T
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Why its called
as linear IC?

Integrated Circuits
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 First op amps built in 1930’s-1940’s
 Technically feedback amplifiers due to
only having one useable input
 Used in WW-II to help how to strike
military targets
 Buffers, summers, differentiators,
inverters
 Took ±300V to ± 100Vto power
http://en.wikipedia.org/wiki/Image:K2-w_vaccuum_tube_op-amp.jpg1
History
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 Vacuum Tube Era, 1950s
 1st used inAnalog Computers
 Addition
 Subtraction
 Integration
 Differentiation
 Heavy
 $$$
 Prone to failure
K2-W tubes general purpose
Op-Amp. 1952
Analog Computer
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IC Fabrication Technology: Brief History
 1940s - setting the stage - the initial inventions that made
integrated circuits possible.
 In 1945, Bell Labs established a group to develop a
semiconductor replacement for the vacuum tube. The group
led by William Shockley, included, John Bardeen, Walter
Brattain and others.
 In 1947 Bardeen and Brattain and Shockley succeeded in
creating an amplifying circuit utilizing a point-contact
"transfer resistance" device that later became known as a
transistor.
 In 1951 Shockley developed the junction transistor, a more
practical form of the transistor.
 By 1954 the transistor was an essential component of the
telephone system and the transistor first appeared in
hearing aids followed by radios.
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The transistor invented at Bell lab. in
1947
In 1956 the importance of the invention of the transistor byBardeen, Brattain and
Shockley was recognized bythe Nobel Prize in physics.
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First Point Contact Transistor and Testing Apparatus (1947)
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1958 - Integrated circuit invented
September 12th 1958 Jack Kilby at Texas instrument had
built a simple oscillator IC with five integrated components
(resistors, capacitors, distributed capacitors and
transistors)
In 2000 the importance of the IC was recognized when
Kilby shared the Nobel prize in physics with two others.
Kilby was sited by the Nobel committee "for his part in the
invention of the integrated circuit ”
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1959- Planar technology invented
 Kilby's invention had a serious
drawback, the individual circuit
elements were connected
together with gold wires
making the circuit difficult to
scale up to any complexity.
 The metal layer connected
down to the junctions through
the holes in the silicon dioxide
and was then etched into a
pattern to interconnect the
circuit. Planar technology set
the stage for complex
integrated circuits and is the
process used today.
Planar technology
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IC Fabrication Technology: History (cont.)
 1960 - Epitaxial deposition developed
 Bell Labs developed the technique of Epitaxial Deposition whereby a
single crystal layer of material is deposited on a crystalline substrate.
Epitaxial deposition is widely used in bipolar and sub-micron CMOS
fabrication.
 1960 - First MOSFET fabricated
 Kahng at Bell Labs fabricates the first MOSFET.
 1961 - First commercial ICs
 Fairchild and Texas Instruments both introduce commercial ICs.
 1962 - Transistor-Transistor Logic invented
 1962 - Semiconductor industry surpasses $1-billion in sales
 1963 - First MOS IC
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 1964 – Bob Widlar designs the first op-amp: the 702.
 Using only 9 transistors, it attains a gain of over 1000
 Highly expensive: $300 per op-amp
 1965 – Bob Widlar designs the 709 op-amp which
more closely resembles the current uA741
 This op-amp achieves an open-loop gain of around 60,000.
 The 709’s largest flaw was its lack of short circuit protection.
History
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 After Widlar left Fairchild, Dave Fullagar continued op-
amp design and came up with the uA741 which is the
most popular operational amplifier of all time.
 This design’s basic architecture is almost identical to Widlar’s
309 op-amp with one major difference: the inclusion of a
fixed internal compensation capacitor.
 This capacitor allows the uA741 to be used without any additional,
external circuitry, unlike its predecessors.
 The other main difference is the addition of extra transistors
for short circuit protection.
 This op-amp has a gain of around 250,000
History
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An integrated circuit (IC) is a miniature, low cost electronic
circuit consisting of active and passive components fabricated
together on a single crystal of silicon. The active components
are transistors and diodes and passive components are resistors
and capacitors.
What is IC?

ADVANTAGES AND DISADVANTAGES OF
INTEGRATED CIRCUITS:
The advantages of integrated circuits are as follows:
1. Small in size due to the reduced device dimension
2. Low weight due to very small size
3. Low power requirement due to lower dimension and lower
threshold power requirement
4. Low cost due to large-scale production
5. High reliability due to the absence of a solder joint
6. Facilitates integration of large number of devices
7. Improves the device performance even at high-frequency
region
The disadvantages of integrated circuits are as follows:
1. IC resistors have a limited range
2. Generally inductors (L) cannot be formed using IC
3. Transformers cannot be formed using IC
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Classification of IC’s
 On the basis of fabrication techniques used
 On the basis of the chip size
 On the basis of applications
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Classification of IC :
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On Basisof Fabrication
 Monolithic IC’s
 Hybrid or Multi-
chip ICs.
 Thin and Thick
Film IC’s.
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Monolithic Ic’s
Monolithic circuit is built into a
single stone or single crystal i.e. in
monolithic ICs, all circuit
components, and their
interconnections are formed into or
on the top of a single chip of silicon.
Monolithic ICs are by far the most
common type of ICs used in
practice, because of mass
production , lower cost and higher
reliability.
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Hybrid Ic’s
The circuit is fabricated by
interconnecting a number of
individual chips.
Hybrids ICs are widely used for high
power audio amplifier applications .
Have better performance than
monolithic ICs
Process is too expensive for mass
production
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Thin And Thick FilmIc’s
These devices are larger than
monolithic ICs but smaller than
discrete circuits. These ICs can be
used when power requirement is
comparatively higher.
With a thin-or thick-film IC, the
passive components likeresistors
and capacitors are integrated, but the
transistors and diodes are connected
as discrete components to form a
complete circuit.
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 The essential difference between the thin- and thick-
film ICs is not their relative thickness but the method
of deposition of film.
 In thick film type the resistors and interconnection
patterns are printed on a ceramic substrate.
 In thin film type the resistors and interconnection
patterns are deposited by vacuum evaporation
technique on a glass or glazed ceramic substrate.
 Both have similar appearance, properties and general
characteristics.
Thin And Thick FilmIc’s
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‘Small scale integration (SSI)
‘Medium scale integration (MSI)
‘Large scale integration (LSI)
‘Very large scale integration (VLSI)
‘Ultra large scale integration (ULSI)
On Basis of Chip Size

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Small scale integration (SSI) has
3 to 30 gates/chip or Up to 100
electronic components per chip
Medium scale integration (MSI)
has 30 to 300 gates/chip or
100 to 3,000 electronic
components per chip
SSI AND MSI
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LSI AND VLSI
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Large scale integration (LSI)-300 to
3,000 gates/chip or 3,000 to 100,000
electronic components per chip.
Verylarge scale integration (VLSI)-
more than 3,000 gates/chip or 100,000
to 1,000,000 electronic components per
chip
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ULSI
Ultra Large-Scale Integration
(ULSI)- More than 1 million
electronic components per chip
The Intel 486 and Pentium
microprocessors, for example, use
ULSI technology. The line between
VLSI and ULSI is vague.
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On Basis of Applications
 LINEAR INTEGRATED CIRCUITS
 DIGITAL INTEGRATED CIRCUITS
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Linear Integrated Circuits
•When the input and output
relationship of a circuit is linear,
linear ICs are used. Input and
output can take place on a
continuous range of values.
•Example operational amplifiers,
power amplifiers, microwave
amplifiers multipliers etc.
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Digital Integrated Circuits
• When the circuit is either in
on-state or off-state and not
in between the two, the
circuit is called the digital
circuit. ICs used in such circuits
are called the digital ICs. They
find wide applications in
computers and logic circuits.
• Example logic gates, flip flops,
counters, microprocessors,
memory chips etc. 33
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Op-amp ID code
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Prefix Designator Suffix
LM 741C N
Prefix Manufacturer
AD/OP Analog Devices
CA/HA Harris
KA Fairchild
LM National Semiconductor
MC ON Semiconductor
NE/SE Signetics
OPA Burr-Brown
RC/RM Raytheon
SG Silicon General
TI Texas Instruments
Code Application Temp.(°C)
C Commercial 0 to 70
I Industrial -25 to 85
M Military -55 to 125
Code Package Type
D,VD Surface mount package
J Ceramic dual-in-line (DIP)
N,P,VP Plastic DIP
DM Micro SMP
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Fundamentals of Monolithic IC
Technology
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Basic Planar Process
The basic processes used to fabricate ICs using silicon
planar technology can be categorized as follows:
1. Silicon wafer (substrate) preparation
2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Isolation techniques
8. Metallization
9. Assembly processing and packaging
(or) Integrated resistor and capacitor
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Fundamental Processing Steps
1.Silicon Manufacturing
a) Czochralski method.
b) Wafer Manufacturing
c) Crystal structure
2.Photolithography
a) Photoresists
b) Photomask and Reticles
c) Patterning

3.Oxide Growth & Removal
a) Oxide Growth & Deposition
b) Oxide Removal
c) Other effects
d) Local Oxidation
4. Diffusion & Ion Implantation
a) Diffusion
b) Other effects
c) Ion Implantation

1. Silicon Wafer Preparation
The following steps are used in the preparation of Si-wafers:
1. Crystal growth and doping
2. Ingot trimming and grinding
3. Ingot slicing
4. Wafer polishing and etching
5. Wafer cleaning
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The starting material for crystal growth is highly purified
(99.99999) polycrystalline silicon. The Czochralski crystal
growth process is the most often used for producing single
crystal silicon ingots. The polycrystalline silicon together with
an appropriate amount of dopant is put in a quartz crucible and
is then placed in a furnace. The material is then heated to a
temperature in excess of the silicon melting point of 1420°C. A
small single crystal rod of silicon called a seed crystal is then
dipped into the silicon-melt and slowly pulled out as shown in
Figure
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Silicon Ingot & Ingot Slicing
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Wafer Polishing and Etching
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2. Epitaxial Growth
• The word epitaxy is derived from Greek word epi
meaning ‘upon’ and the past tense of the word
teinon meaning ‘arranged’. So, one could describe
epitaxy as, arranging atoms in single crystal fashion
upon a single crystal substrate, so that the resulting
layer is an extension of the substrate crystal
structure.
• The basic chemical reaction used for the epitaxial
growth of pure silicon is the hydrogen reduction of
silicon tetrachloride.
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3. Oxidation
• SiO2 has the property of preventing the diffusion of almost
all impurities through it. It serves two very important
purposes.
1. SiO2 is an extremely hard protective coating and is
unaffected by almost all reagents except hydrofluoric acid.
Thus, it stands against any contamination.
2. By selective etching SiO2, diffusion of impurities through
carefully defined windows in the SiO2 can be accomplished to
fabricate various components.
• The silicon wafers are stacked up in a quartz boat and then
inserted into quartz furnace tube. The Si-wafers are raised to
a high temperature in the range of 950 to 1115°C and at the
same time, exposed to a gas containing O2 or H2O or both.
The chemical reaction is
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This oxidation process is called thermal oxidation because
high temperature is used to grow the oxide layer. The thickness of
the film is governed by time, temperature and the moisture content.
The thickness of oxide layer is usually in the order of 0.02 to 2 mm.

4. Photolithography
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Photolithography
• Photolithography involves two processes, namely:
1.Making of a photographic mask
2.Photo etching
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Masking:
To protect some area of wafer when working on another area, a
process called photolithography is used. A photoresist film is applied
on the wafer. The wafer is aligned to a mask using photo aligner. Then it
is exposed to ultraviolet light through mask. Before that the wafer must
be aligned with the mask. Generally, there are automatic tools for
alignment purpose.

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Etching:
It removes material selectively from the surface of wafer to create patterns.
The pattern is defined by etching mask. The parts of material are protected by
this etching mask. Either wet (chemical) or dry (physical) etching can be used
to remove the unmasked material. To perform etching in all directions at same
time, isotropic etching will be used. Anisotropic etching is faster in one
direction. Wet etching is isotropic, but the etching time control is difficult. Wet
etching uses liquid solvents for removing materials. It is not suited to transfer
pattern with submicron feature size. It does not damage the material. Dry
etching uses gases to remove materials. It is strongly anisotropic. But it is less
selective. It is suited to transfer pattern having small size. The remaining photo
resist is finally removed using additional chemicals or plasma. Then the wafer
is inspected to make sure that the image is transferred from mask to the top
layer of wafer.

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Another important process in the fabrication of monolithic ICs is
the diffusion of impurities in the silicon chip. This uses a high
temperature furnace having a flat temperature profile over a useful
length (about 20” length). A quartz boat containing about 20 cleaned
wafers is pushed into the hot zone with temperature maintained at about
a 1000°C. Impurities to be diffused are rarely used in their elemental
forms. Normally, compounds such as B2O3 (Boron oxide), BCl3 (Boron
chloride) are used for Boron and P2O5 (Phosphorous pentaoxide) and
POCl3 (Phosphorous oxychloride) are used as sources of Phosphorous. A
carrier gas, such as dry oxygen or nitrogen is normally used for sweeping
the impurity to the high temperature zone. The depth of diffusion
depends upon the time of diffusion which normally extends to 2 hours.
The diffusion of impurities normally takes place both laterally as
well as vertically. Therefore, the actual junction profiles will be curved as
shown in NPN transistor Fig.
5. Diffusion
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6.Ion Implantation
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7. Isolation Technique
• Once all components are fabricated on a
single crystal wafer, they must be electrically
isolated from each other. The problem is not
encountered in discrete circuits, because
physically all components are isolated. There
are two methods of isolation in Integrated
circuits. They are
• P-N junction isolation and
• Dielectric isolation
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8. Metallization
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The purpose of this process is to produce a thin
metal film layer that will serve to make
interconnections of the various components on the
chip. Aluminum is usually used for the metallization
of most ICs as it offers several advantages.
1. It is relatively a good conductor.
2.It is easy to deposit aluminum films using
vacuum deposition.
3. Aluminum makes good mechanical bonds with
silicon.
4. Aluminum forms low resistance, non-rectifying
(i.e., ohmic) contact with p-type silicon and the
heavily doped n-type silicon.

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9.Assembly processing and packaging

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Fabrication of a Typical Circuit /
Realization of Monolithic IC Technology
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Fabrication of
Resistors

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Integrated Resistors:
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A resistor in a monolithic integrated circuit is obtained
by utilizing the bulk resistivity of the diffused volume of
semiconductor region. The commonly used methods for
fabricating integrated resistors are
1. Diffused
2. Epitaxial
3. Pinched and
4. Thin film techniques.

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Diffused Resistor:
The diffused resistor is formed in any one of the isolated
regions of epitaxial layer during base or emitter diffusion processes.
This type of resistor fabrication is very economical as it runs in parallel
to the bipolar transistor fabrication. The N-type emitter diffusion and P-
type base diffusion are commonly used to realize the monolithic
resistor.
The diffused resistor has a severe limitation in that, only small
valued resistors can be fabricated. The surface geometry such as the
length, width and the diffused impurity profile determine the resistance
value. The commonly used parameter for defining this resistance is
called the sheet resistance. It is defined as the resistance in
ohms/square offered by the diffused area.
In the monolithic resistor, the resistance value is expressed by
R = Rs l/w where R= resistance offered (in ohms)
Rs = sheet resistance of the particular fabrication process involved (in
ohms/square)
l = length of the diffused area and
w = width of the diffused area.

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The sheet resistance of the base and emitter diffusion in 200Ω/Square and
2.2Ω/square respectively.

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Design Rules:

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The sheet resistance offered by the diffusion regions can be increased by
narrowing down its cross-sectional area. This type of resistance is normally
achieved in the base region. Figure shows a pinched base diffused resistor. It can
offer resistance of the order of mega ohms in a comparatively smaller area. In the
structure shown, no current can flow in the N-type material since the diode realized
at contact 2 is biased in reversed direction. Only very small reverse saturation
current can flow in conduction path for the current has been reduced or pinched.
Therefore, the resistance between the contact 1 and 2 increases as the width
narrows down and hence it acts as a pinched resistor.

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Thin film resistor fabrication:
Thin film resistors are fabricated by sputtering a high-resistance film of
Tantalum- Nitride (TaN) or NiChrome (NiCr) under the conductor layer and
selectively etching the resistor elements. The following table shows how typical
characteristics of Tantalum-Nitride (TaN) and Nichrome (NiCr) films can be used to
obtain desired performance.
Film Type
Sheet
Resistivity
(ohm/square
)
TCR
(ppm/°C)
Passivated
Tolerances
(no trim)
Laser
Trimmed
Tolerances
TaN 10–150 -100 ± 50 ± 10% ± 0.5–10%
NiCr 50–225 0 ± 50 ± 10% ± 0.5–10%

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Fabrication of Inductors

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Fabrication of
Capacitors

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Monolithic/ Junction Capacitors:
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MOS &Thin Film Capacitors:

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Fabrication of Diodes

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Fabrication of
Transistors

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Fabrication of FET

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MOSFET Fabrication:

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MOSFET Fabrication- Polysilicon Gate:

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NMOS Fabrication Steps:
1. By the process of Chemical Vapour Deposition (CVD), a thin layer of
Si3N4 is deposited on the entire wafer surface. With the first
photolithographic step, the areas where the transistors are to be fabricated
are clearly defined. Through chemical etching, Si3N4 is removed outside the
transistor areas. In order to suppress the unwanted conduction between
transistor sites, an impurity such as Boron is implanted in the exposed
regions. Next, SiO2 layer of about 1 micro meters thickness is grown in
these inactive, or field regions by exposing the wafer to oxygen in an
electric furnace. This is known as selective or local oxidation process. The
Si3N4 is impervious to oxygen and thus inhibits growth of the thick oxide in
the transistor regions.

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NMOS Fabrication Steps:
2.Next, the Si3N4 is removed by an etchant that does not attack SiO2. A layer
of oxide about 0.1 micro meters thick is grown in the transistor areas. Then a
layer of poly-Silicon is grown over the entire wafer by CVD process. The
second photolithographic step shows the desired patterns for gate electrodes.
The unwanted poly-Silicon is removed by chemical or plasma etching. In order
to introduce a source and drain in particular regions for the MOS device, an
n-type dopant, such as phosphorus or arsenic, is introduced. This is done by
either Diffusion or Ion Implantation method. The thick field oxide and the
polysilicon gate are barriers to the dopant, but in this process, the poly-Si
becomes heavily n-type.

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3. Again, through CVD process, an insulating layer, SiO2, is deposited. As
shown in the figure above, the third photolithographic step shows the
areas in which contacts to the transistors are to be made. Chemical or
plasma etching selectively exposes bare silicon or poly-Si in the contact
areas.
4. Al is used for the interconnection. As shown in the figure above, the
fourth masking step shows the Al as desired for the circuit
connections.

Schematic Diagram of a CMOS Circuit:
Its possible to fabricate NMOS &
PMOS enhancement devices on the
same silicon chip. These devices are
called complementary MOSFETs. Figure
10-23(b)shows that one nMOS and one
pMOS are placed on a common substrate. It
looks like two tubs are placed on a same
base. The source, gate and drain are
indicated by S, G and D respectively.
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With the help of twin-tub method, a complete CMOS can be
realized.
CMOS Circuit:
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Fabrication of PV Cell

PHOTO VOLTAIC GENERATION
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FABRICATION OF SOLAR/PHOTOVOLTAIC CELL
In 1883, first photo voltaic cell was made by
Charles Fritts, who coated the semiconductor
selenium with an extremely thin layer of gold to
form the junctions. It was only 1% efficient.
Basically
A solar cell is a junction (usually a PN junction)
with sunlight shining on it.
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STEPS OF FABRICATION
1. First step is refining silicon
2. Silicon dioxide (SiO2) is the most abundant mineral in the
earth's crust.
3. The manufacture of the hyper pure silicon for
photovoltaics starts with locating a source of silicon
dioxide in the form of sand.
4. The silica is reduced (oxygen removed) through a
reaction with carbon in the form of coal, charcoal and
heating to 1500-2000 °C in an electrode arc furnace.
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Silicon di oxide + Carbon = Silicon + Carbon di oxide
The resulting silicon is 98% pure. It contains Fe, Al, and B, to
remove these traces , further purification is done. Powdered Si is
reacted with anhydrous HCl at 300◦C to form SiHCl3
During this reaction impurities such as Fe, Al, and B react to form
their halides (e.g. FeCl3, AlCl3, and BCl3).
The SiHCl3 has a low boiling point of 31.8◦C and distillation is used
to purify the SiHCl3 from the impurity halides.
Finally, the pure SiHCl3 is reacted with hydrogen at 1100◦C for ~200
– 300 hours to produce a very pure form of silicon.
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Above reaction takes place inside large vacuum
chambers and the silicon is deposited onto thin polysilicon
rods (small grain size silicon) to produce high-purity
polysilicon rods of diameter 150-200mm.
Silicon used for solar cells can be single crystalline, multi
crystalline, polycrystalline or amorphous. The key
difference between these materials is degree to which the
semiconductor has a regular, perfectly ordered crystal
structure.
After getting the required silicon from above mentioned
chemical procedure , different methods of solar cells
fabrication are applied , each method involves doping of
silicon to make p-n junction , and required processes to
make a furnished solar cell.
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METHODS OF FABRICATION
SCREEN PRINTED SOLAR CELL FABRICATION
TECHNOLOGY
 Screen-printed solar cells were first developed in the 1970's. Most
mature solar cell fabrication technology. The key advantage of screen-
printing is the relative simplicity of the process.
 It involves cutting a wafer of 10*10 square cm,0.5mm thick , this wafer is
then p-type doped with born to add up holes .
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Buried Contact Fabrication Technology
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THANKYOU

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