PREPARED BY:
Ms.PRIYANKA BISARYA
Sr.Lect.EC Dept.
1
SISTEC-E
 Description of I.C
 How to read I.C
 Pulling ingots
 Wafers
 Patterning
 Fabrication cycle
 Testing
 Packaging
2
...
The integrated circuit (IC) chip has found its way into
everything from toasters to communications satellites.
This small ...
4
SISTEC-E
ICs can be made very compact, having up to
several billion transistors and other electronic
components in an ar...
5
SISTEC-E
6
SISTEC-E
1.Read the serial number from the top side of the
IC. The top side of the IC is facing up when the chip
is standing on its...
8
SISTEC-E
9
SISTEC-E
 Monocrystalline silicon
is produced from
purified polycrystalline
silicon by “pulling” an
ingot
◦ polysilicon is melted
...
 Produces an ingot of pure silicon
◦ 400 mm - 1000 mm long (15” - 39”)
◦ 150 mm - 200 mm in diameter (6” - 8”)
 Growth i...
12
SISTEC-E
13
SISTEC-E
 Wafers and Chips
◦ Integrated circuit (IC) chips are manufactured on
silicon wafers
◦ Transistors are placed on the wafe...
Chip Manufacturing Process
COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED
15
SISTEC-E
 Standard Chips
◦ Small number of transistors (< 100)
◦ Simple and fixed functions
◦ Logic designer must decide how to in...
Integrated circuit showing
memory blocks, logic and
input/output pads around
the periphery
17
SISTEC-E
18
SISTEC-E
19
SISTEC-E
Silicon chip High lead solder die attach
Tin/lead plated copper
lead frame
20
SISTEC-E
 3C : Computer--- /Communication / Consumables
 Personal Computer--- Desktop Computer (DT) /
Notebook (NB)
 Communicati...
 Dynamic Random Access Memory chips (DRAMs) -
serve as the primary memory for computers
 Microprocessors (MPUs) - act as...
 Front-End Processing (Wafer fabrication)
 Back-End Processing (Assembly and Testing)
23
SISTEC-E
A logic circuit diagram is drawn to determine the
electronic circuit required for the requested function.
Once the logic c...
 The photomask is a copy of the circuit pattern,
drawn on a glass plate coated with a metallic film.
 The glass plate le...
The
photomask
of a RF IC
Chip
26
SISTEC-E
 A high-purity, single-crystal silicon called
"99.999999999% (eleven-nine)" is grown from a
seed to an ingot.
 The wafer...
 The wafer is placed in a high-temperature furnace to
make the silicon react with oxygen or water vapor, and
to develop o...
 A resin called "photoresist" is coated over
the entire wafer. (~1μm thick coating.)
 Photoresist is a special resin sim...
 Placed over the photoresist-coated wafer, which
is then irradiated to have the circuit diagram
transcribed onto it.
 An...
Lithography area in clean room 31
SISTEC-E
32
SISTEC-E
 The photoresist chemically reacts and dissolves in
the developing solution, only on the parts that were
not masked durin...
 "Etching" refers to the physical or chemical etching
of oxide films and metallic films using the resist
pattern as a mas...
35
SISTEC-E
 The photo resist remaining on the wafer surface is
no longer necessary after etching is complete.
Ashing by oxygen plasm...
 After the oxide film and nitride film are developed,
a resist pattern is formed on the regions that will
become the devi...
38
SISTEC-E
 A transistor is a semiconductor device with a switching
function and three terminals: source, drain, and gate.
 An insu...
Polysilicon Gate
Cross-Section Image
40
SISTEC-E
 Interconnecting the devices, such as transistors,
formed on the silicon wafer completes the circuit.
 the wafer is firs...
 Each IC on the completed wafer is electronically
tested by the tester.
 After this inspection, the front-end processing...
43
SISTEC-E
 In back end processing, a wafer completed
in front end processing is cut into individual
IC chips and encapsulated into ...
 After the IC chips are cut apart,
they are sealed into packages.
The IC chips must first be
attached to a platform calle...
 The mounted IC chips are connected to the
lead frames.
46
SISTEC-E
 The IC chips and the lead frame islands are
encapsulated with molding resin for
protection.
47
SISTEC-E
 The packaged IC chips are tested and selected.
48
SISTEC-E
 The final step of IC chip manufacturing is the
printing onto the package surface and the
finishing of leads. After this ...
 Ingot is finely shaped using abrasive belts
◦ flat spot added for alignment during processing
 Sawed into wafers about ...
 Silicon dioxide is created by interaction between
silicon and oxygen or water vapor
◦ Si + O2 = SiO2 or Si + 2H2O = SiO2...
 Patterning creates a regular pattern on the surface
of the chip, which is used to create features of the
IC
◦ involves a...
 Lithography (continued)
◦ mask placed very close
to wafer, flooded with
uv light
◦ solvents remove
exposed (unexposed)
r...
 Etching (continued)
◦ anisotropic etching works faster in one direction than the
other
◦ wet etching uses liquid solvent...
 Metalization is used to create contacts with the
silicon and to make interconnections on the chip
 Desired properties a...
 Aluminum is common choice but
◦ Al causes spikes into Si, giving leaky junctions
◦ high currents carry Al atoms with the...
 Silicon processing steps are performed on whole wafers
◦ 150mm to 200mm in diameter
57
SISTEC-E
 Each wafer contains
many individual chips
◦ 5mm to 15 mm square
 Chips are scribed with a
diamond saw or
diamond-tipped...
 Each chip is cemented into a package.
 Wire leads from pins on the package to bonding pads on the
chip are installed.
...
Step I: The Beginning-Choosing a substrate
Before actual wafer fabrication, we must choose the starting wafers. The
major ...
 In order to electrically isolate
individual device a fairly thick
layer of SiO2 in between each
of the active devices (c...
 For resister, usually a
conducting layer has
been deposited. The
resister value is
estimated by
R=ρL / W.t
3
Lecture # 2...
 In order to transfer resister
information from the design to
the wafer, a process known as
photolithography is used.
 F...
 In order to interconnect the
different resistors on the
chip, another insulating layer
must be deposited.
 To make the ...
 Finally, the fabrication
process can be completed,
depositing a highly conductive
metal layer by using a third
mask laye...
 The resister IC technology
discussed above uses
 Three photolithography
steps
 Three etch steps
 Four thin film depos...
67
SISTEC-E
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  1. 1. PREPARED BY: Ms.PRIYANKA BISARYA Sr.Lect.EC Dept. 1 SISTEC-E
  2. 2.  Description of I.C  How to read I.C  Pulling ingots  Wafers  Patterning  Fabrication cycle  Testing  Packaging 2 SISTEC-E
  3. 3. The integrated circuit (IC) chip has found its way into everything from toasters to communications satellites. This small electronic device, a miniature package of transistors, has revolutionized product design and increased capability while shrinking size and cost in numerous items. 1 3 SISTEC-E
  4. 4. 4 SISTEC-E ICs can be made very compact, having up to several billion transistors and other electronic components in an area the size of a fingernail. The width of each conducting line in a circuit (the line width) can be made smaller and smaller as the technology advances; in 2008 it dropped below 100 nanometres and in 2013 it is expected to be in the tens of nanometres.
  5. 5. 5 SISTEC-E
  6. 6. 6 SISTEC-E
  7. 7. 1.Read the serial number from the top side of the IC. The top side of the IC is facing up when the chip is standing on its pins. You may require a magnifying glass while reading the IC serial information. 7 SISTEC-E
  8. 8. 8 SISTEC-E
  9. 9. 9 SISTEC-E
  10. 10.  Monocrystalline silicon is produced from purified polycrystalline silicon by “pulling” an ingot ◦ polysilicon is melted using radio frequency induction heaters ◦ “seed crystal” of monocrystalline silicon is dipped into melt ◦ silicon grows around structure of seed as seed is slowly withdrawn 10 SISTEC-E
  11. 11.  Produces an ingot of pure silicon ◦ 400 mm - 1000 mm long (15” - 39”) ◦ 150 mm - 200 mm in diameter (6” - 8”)  Growth is a slow process ◦ 10 - 20 hours  Silicon is often doped as it’s grown 11 SISTEC-E
  12. 12. 12 SISTEC-E
  13. 13. 13 SISTEC-E
  14. 14.  Wafers and Chips ◦ Integrated circuit (IC) chips are manufactured on silicon wafers ◦ Transistors are placed on the wafers through a chemical etching process ◦ Each wafer is cut into chips (dies) which are then packaged individually 14 SISTEC-E
  15. 15. Chip Manufacturing Process COPYRIGHT 1998 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED 15 SISTEC-E
  16. 16.  Standard Chips ◦ Small number of transistors (< 100) ◦ Simple and fixed functions ◦ Logic designer must decide how to interconnect multiple chips for desired function ◦ Agreed upon / standard functionality ◦ Popular in the 1980s – too large in physical size for much industry use now (good for teaching though!) 16 SISTEC-E
  17. 17. Integrated circuit showing memory blocks, logic and input/output pads around the periphery 17 SISTEC-E
  18. 18. 18 SISTEC-E
  19. 19. 19 SISTEC-E
  20. 20. Silicon chip High lead solder die attach Tin/lead plated copper lead frame 20 SISTEC-E
  21. 21.  3C : Computer--- /Communication / Consumables  Personal Computer--- Desktop Computer (DT) / Notebook (NB)  Communication--- ADSL / Cable Modem / IEEE802.11X / Bluetooth / VoIP  Consumables--- Game / DVD / Digital Camera  3C merge--- Digital Home 21 SISTEC-E
  22. 22.  Dynamic Random Access Memory chips (DRAMs) - serve as the primary memory for computers  Microprocessors (MPUs) - act as the brains of computers.  Application Specific Integrated Circuits (ASICs) - are custom semiconductors designed for very specific functions  Digital Signal Processors (DSPs) - process signals, such as image and sound signals or radar pulses.  Programmable memory chips (EPROMs, EEPROMs, and Flash) - are used to perform functions that require programming on the chip. 22 SISTEC-E
  23. 23.  Front-End Processing (Wafer fabrication)  Back-End Processing (Assembly and Testing) 23 SISTEC-E
  24. 24. A logic circuit diagram is drawn to determine the electronic circuit required for the requested function. Once the logic circuit diagram is complete, simulations are performed multiple times to test the circuit’s operation. 24 SISTEC-E
  25. 25.  The photomask is a copy of the circuit pattern, drawn on a glass plate coated with a metallic film.  The glass plate lets light pass, but the metallic film does not.  Due to increasingly high integration and miniaturization of the pattern, the size of the photomask is usually magnified four to ten times the actual size. 25 SISTEC-E
  26. 26. The photomask of a RF IC Chip 26 SISTEC-E
  27. 27.  A high-purity, single-crystal silicon called "99.999999999% (eleven-nine)" is grown from a seed to an ingot.  The wafers are generally available in diameters of 150 mm, 200 mm, or 300 mm, and are mirror- polished and rinsed before shipment from the wafer manufacturer. 27 SISTEC-E
  28. 28.  The wafer is placed in a high-temperature furnace to make the silicon react with oxygen or water vapor, and to develop oxide films on the wafer surface (thermal oxidation).  To develop nitride films and polysilicon films, the chemical vapor deposition (CVD) method is used, in which a gaseous reactant is introduced to the silicon substrate, and chemical reaction produce the deposited layer material.  The metallic layers used in the wiring of the circuit are also formed by CVD, spattering (PVD: physical vapor deposition) 28 SISTEC-E
  29. 29.  A resin called "photoresist" is coated over the entire wafer. (~1μm thick coating.)  Photoresist is a special resin similar in behavior to photography films that changes properties when exposed to light. 29 SISTEC-E
  30. 30.  Placed over the photoresist-coated wafer, which is then irradiated to have the circuit diagram transcribed onto it.  An irradiation device called the "stepper" is used to irradiate the wafer through the mask with ultraviolet (UV) light. 30 SISTEC-E
  31. 31. Lithography area in clean room 31 SISTEC-E
  32. 32. 32 SISTEC-E
  33. 33.  The photoresist chemically reacts and dissolves in the developing solution, only on the parts that were not masked during exposure (positive method).  Development is performed with an alkaline developing solution.  After the development, photoresist is left on the wafer surface in the shape of the mask pattern. 33 SISTEC-E
  34. 34.  "Etching" refers to the physical or chemical etching of oxide films and metallic films using the resist pattern as a mask.  Etching with liquid chemicals is called "wet etching" and etching with gas is called "dry etching". 34 SISTEC-E
  35. 35. 35 SISTEC-E
  36. 36.  The photo resist remaining on the wafer surface is no longer necessary after etching is complete. Ashing by oxygen plasma or the likes is performed to remove the residual photo resist. 36 SISTEC-E
  37. 37.  After the oxide film and nitride film are developed, a resist pattern is formed on the regions that will become the device insulation layer.  Ion implantation is performed on the wafer, forming a p-type diffusion layer.  Next, the oxide film and nitride film on the diffusion layer are etched.  Using the nitride film pattern as the mask, the oxide film that will become the device insulation layer is developed. 37 SISTEC-E
  38. 38. 38 SISTEC-E
  39. 39.  A transistor is a semiconductor device with a switching function and three terminals: source, drain, and gate.  An insulation layer called "gate oxide" is first formed on the wafer surface.  A polysilicon film is deposited onto the gate oxide, and a polysilicon gate for controlling the flow of electrons between the source region and the drain region is formed by lithography and etching.  After the polysilicon gate is formed, an n-type diffusion layer consisting of both the source and the drain regions is formed by implantation of impurities 39 SISTEC-E
  40. 40. Polysilicon Gate Cross-Section Image 40 SISTEC-E
  41. 41.  Interconnecting the devices, such as transistors, formed on the silicon wafer completes the circuit.  the wafer is first covered with a thick and flat interlayer insulation film (oxide film). Next, contact holes are drilled by lithograph and etching, through the interlayer insulation film, above the devices to be connected. Nine-layer Copper Interconnect Architecture 41 SISTEC-E
  42. 42.  Each IC on the completed wafer is electronically tested by the tester.  After this inspection, the front-end processing is complete. 42 SISTEC-E
  43. 43. 43 SISTEC-E
  44. 44.  In back end processing, a wafer completed in front end processing is cut into individual IC chips and encapsulated into packages. 44 SISTEC-E
  45. 45.  After the IC chips are cut apart, they are sealed into packages. The IC chips must first be attached to a platform called the "lead frame“. 45 SISTEC-E
  46. 46.  The mounted IC chips are connected to the lead frames. 46 SISTEC-E
  47. 47.  The IC chips and the lead frame islands are encapsulated with molding resin for protection. 47 SISTEC-E
  48. 48.  The packaged IC chips are tested and selected. 48 SISTEC-E
  49. 49.  The final step of IC chip manufacturing is the printing onto the package surface and the finishing of leads. After this step, the IC chips are complete. 49 SISTEC-E
  50. 50.  Ingot is finely shaped using abrasive belts ◦ flat spot added for alignment during processing  Sawed into wafers about 600 microns thick ◦ only a few microns are actually used for IC devices ◦ then etched, polished, and cleaned ◦ stacked in carriers. 50 SISTEC-E
  51. 51.  Silicon dioxide is created by interaction between silicon and oxygen or water vapor ◦ Si + O2 = SiO2 or Si + 2H2O = SiO2 + 2H2 ◦ protects surface from contaminants ◦ forms insulating layer between conductors ◦ form barrier to dopants during diffusion or ion implantation ◦ grows above and into silicon surface  Polysilicon ◦ silicon without a single crystal structure ◦ created when silicon is epitaxially grown on SiO2 ◦ also a conductor, but with much more resistance than metal or diffused layers ◦ commonly used (heavily doped) for gate connections in most MOS processes 40% 60% 51 SISTEC-E
  52. 52.  Patterning creates a regular pattern on the surface of the chip, which is used to create features of the IC ◦ involves alternative lithography and etching steps ◦ each of several layers involves a separate pattern  Lithography ◦ patterns are contained on masks  eg, chrome on glass ◦ surface of the wafer is covered with photoresist  organic material sensistive to uv light or X-rays  spin and bake  positive resist becomes more soluable when exposed  resist will be removed where mask is clear  negative resist becomes less soluable when exposed  resist will be removed where mask is opaque 52 SISTEC-E
  53. 53.  Lithography (continued) ◦ mask placed very close to wafer, flooded with uv light ◦ solvents remove exposed (unexposed) resist  Etching removes material from wafer surface where resist has been removed ◦ isotropic etching works at same rate in all directions of material 53 SISTEC-E
  54. 54.  Etching (continued) ◦ anisotropic etching works faster in one direction than the other ◦ wet etching uses liquid solvents to remove materials  eg, HF for SiO2 ◦ dry etching uses gas to remove materials  less undercutting  can monitor reactants during process, determine automatically when etching is finished  Finally, remaining photoresist is removed ◦ organic solvents or chromic acid ◦ pure oxygen, to oxidize organic resist materials 54 SISTEC-E
  55. 55.  Metalization is used to create contacts with the silicon and to make interconnections on the chip  Desired properties are ◦ low resistivity  in ohms/square ◦ good adhesion to silicon and insulators ◦ good coverage of steps in chip surface ◦ immunity to corrosion ◦ ductility (so temperature cycles don’t cause failures) 55 SISTEC-E
  56. 56.  Aluminum is common choice but ◦ Al causes spikes into Si, giving leaky junctions ◦ high currents carry Al atoms with them, creating shorts ◦ low melting point prohibits high heat processing later  Latest step is to use copper ◦ IBM has been shipping chips with copper for a year  smaller, 50% less power consumption ◦ other fabs to follow soon 56 SISTEC-E
  57. 57.  Silicon processing steps are performed on whole wafers ◦ 150mm to 200mm in diameter 57 SISTEC-E
  58. 58.  Each wafer contains many individual chips ◦ 5mm to 15 mm square  Chips are scribed with a diamond saw or diamond-tipped scribe, or a laser, and fractured along the scribe lines into chips 58 SISTEC-E
  59. 59.  Each chip is cemented into a package.  Wire leads from pins on the package to bonding pads on the chip are installed.  A cover is cemented over the cavity and marked. 59 SISTEC-E
  60. 60. Step I: The Beginning-Choosing a substrate Before actual wafer fabrication, we must choose the starting wafers. The major choices are the type (N or P), resistivity, and orientation. In most IC circuits, the substrate has a resistivity in the range of 25- 50Ωcm, which corresponds to a doping level on the order of 1015 cm-3 . The other major parameter we need to specify in the starting substrate is the crystal orientation. Virtually all modern silicon integrated circuits are manufactured today from wafer with a (100) surface orientation. The principal reason for this is that the properties of Si/Sio2 interface are significantly better when a (100) crystal is used. 1 Lecture # 2 60 SISTEC-E
  61. 61.  In order to electrically isolate individual device a fairly thick layer of SiO2 in between each of the active devices (chapter 6) is needed to grow. The region between the thick SiO2 layers, where devices will be built, are called the “active” region of the substrate. 2 Lecture # 2 61 SISTEC-E
  62. 62.  For resister, usually a conducting layer has been deposited. The resister value is estimated by R=ρL / W.t 3 Lecture # 2 62 SISTEC-E
  63. 63.  In order to transfer resister information from the design to the wafer, a process known as photolithography is used.  For this process a material known as photoresist is first spread on the wafer. It is usually baked at about 100o C in order to drive off  solvants from the layer (photolithographic process will be covered in chapter 5 through. 4 Lecture # 2 63 SISTEC-E
  64. 64.  In order to interconnect the different resistors on the chip, another insulating layer must be deposited.  To make the electrical contact to the resistor, holes must be opened in the insulating layer using the same photolithographic process. Insulator material 5 64 SISTEC-E
  65. 65.  Finally, the fabrication process can be completed, depositing a highly conductive metal layer by using a third mask layer. metal 6 Lecture # 2 How many layers consist of this Technology? 65 SISTEC-E
  66. 66.  The resister IC technology discussed above uses  Three photolithography steps  Three etch steps  Four thin film deposition steps (the lower insulator film, the resistor film, the upper insulator, and the interconnect metal). 7 Lecture # 2 66 SISTEC-E
  67. 67. 67 SISTEC-E

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